CN103199866A - 8b/10b decoding circuit based on rd- - Google Patents
8b/10b decoding circuit based on rd- Download PDFInfo
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Abstract
The invention discloses an 8b/10b decoding circuit based on rd-. 10 bit data of external input are divided to front 6 bit data and rear 4 bit data to be respectively fed into a 6b preprocessing module and a 4b preprocessing module, and first data character data and first control character data, generated after the front 6 bit data are preprocessed through the 6b preprocessing module, are respectively sent to a 5b/6b data character decoder based on the rd- and a 5b/6b control character decoder based on the rd-; second data character data and second control character data, generated after the rear 4 bit data are preprocessed through the 4b preprocessing module, are respectively sent to a 3b/4b data character decoder based on the rd- and a 3b/4b control character decoder based on the rd-; and data are all sent to a data merging module after the data are decoded by four decoders, and appropriate data are chosen and synthesized into 8 bit data to be outputted. The 8b/10b decoding circuit based on the rd- can save a large quantity of resources of a memorizer.
Description
Technical field
The present invention relates to a kind of decoding circuit, relate in particular to a kind of 8b/10b decoding circuit based on rd-.
Background technology
8b/10b also is called 8 bits/10 bits, is the encoding mechanism that present many high-speed serial bus adopts, as bus such as 1394b, Serial ATA, PCI Express, Infini-band, Fibre Channel (netted passage), RapidIO or network etc.
One of characteristic of 8b/10b coding is to guarantee the DC balance, adopt the 8b/10b coded system, can make " 0 ", " 1 " quantity of sending keep basically identical, continuous " 1 " or " 0 " is no more than 5, be to insert one " 0 " or " 1 " behind per 5 continuous " 1 " or " 0 ", thereby guarantee signal DC balance, it in other words, unlikely generations DC lacks of proper care when link is overtime.Encode by 8b/10b, can guarantee that the serial data that transmits can correctly be restored at receiving terminal, in addition, utilize some special codes (in the PCI-Express bus, being the K sign indicating number), the work that can help receiving terminal to reduce, and can find the error of transmission of data bit in early days, suppress wrong the continuation and take place.8b/10b coding is that one group of 8 continuous bit data is resolved into two groups of data, one group 3, one group 5, through becoming one group 4 data and one group 6 data respectively behind the coding, sends thereby form one group 10 data.On the contrary, decoding is 1 group 10 input data to be passed through conversion obtain 8 bit data positions.Data value can be unified is expressed as DX.Y or KX.Y, and wherein D is expressed as data character, and K is expressed as control character, and X represents low 5 EDCBA of the initial data imported, and Y represents high 3 HGF of the initial data imported.
Existing 8b/10b decoding circuit adopts the method for tabling look-up to realize the 8b/10b decoding mostly, is decoded as example with the 8b/10b of data character, and the register that it is 8 bits that existing 8b/10b decoding circuit needs 512 width is stored related data, and the memory resource that takies is more.
Summary of the invention
Technical problem to be solved by this invention provides a kind of 8b/10b decoding circuit based on rd-, can save memory resource in a large number.
For solving the problems of the technologies described above, the 8b/10b decoding circuit based on rd-provided by the invention is by 6b pretreatment module, 4b pretreatment module, based on the 5b/6b data character decoder of rd-, based on the 5b/6b control character decoder of rd-, based on the 3b/4b data character decoder of rd-, merge module and two XOR modules constitute based on 3b/4b control character decoder, the data of rd-;
Outer input data is 10 Bit datas, and this 10 Bit data is split as preceding 6 Bit datas and back 4 Bit datas, and described preceding 6 Bit datas are input to described 6b pretreatment module, and described back 4 Bit datas are input to described 4b pretreatment module;
One current character polar signal is input to described 6b pretreatment module and the first XOR module respectively; This current character polar signal is represented the polarity of current input character, described 6b pretreatment module is carried out pretreatment operation to described preceding 6 Bit datas under the control of current character polar signal, and export the first data character data, the first control character data and the first change in polarity indications signal;
The first XOR module is used for described current character polar signal and the described first change in polarity indications signal are carried out the XOR processing and export the second character polar signal;
The described second character polar signal is input to described 4b pretreatment module and the second XOR module respectively; Described 4b pretreatment module is carried out pretreatment operation to described back 4 Bit datas under the control of the second character polar signal, and exports the second data character data, the second control character data and the second change in polarity indications signal;
The second XOR module is used for the described second character polar signal and the described second change in polarity indications signal are carried out the XOR processing, produces next character polar signal, and described next character polar signal is externally exported;
The described first data character data are input to described 5b/6b data character decoder based on rd-and handle, and export the first data character decoded data and first data character decoding indications signal;
The described first control character data are input to described 5b/6b control character decoder based on rd-and handle, and export the first control character decoded data and first control character decoding indications signal;
The described second data character data are input to described 3b/4b data character decoder based on rd-and handle, and export the second data character decoded data and second data character decoding indications signal;
The described second control character data are input to described 3b/4b control character decoder based on rd-and handle, and export the second control character decoded data and second control character decoding indications signal;
The described first data character decoded data, first data character decoding indications signal, the first control character decoded data, first control character decoding indications signal, the second data character decoded data, second data character decoding indications signal, the second control character decoded data and second control character decoding indications signal are input to described data and merge module, handle and export output data and an indicator signal of one 8 bits.
The present invention can save memory resource in a large number, 8b/10b with data character is decoded as example, the present invention only needs the register of 83 bits and 32 5 bits to store data, and shared storage resources only is 4.492% of existing 8b/10b decoding circuit, and resource is saved the effect highly significant.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Accompanying drawing is that the embodiment of the invention is based on the 8b/10b decoding circuit structure chart of rd-.
Embodiment
It is inconsistent that related rd refers to the operation character among the present invention, is also referred to as polarity, refers to namely in the character that the number of 1 number and 0 is inconsistent; Wherein, rd+ is more than 1 to 0 in the character, and this moment is inconsistent for just (+); Rd-is that 1 to 0 in the character is few, and this moment is inconsistent for negative (-).
By reference to the accompanying drawings, described 8b/10b decoding circuit based on rd-, 10 Bit datas that the outside is imported are split as preceding 6 Bit datas and back 4 Bit datas, send into 6b pretreatment module and 4b pretreatment module respectively.Preceding 6 Bit datas are after the preliminary treatment of 6b pretreatment module, and the first data character data data_6b of generation and the first control character data ctl_6b are sent to respectively based on the 5b/6b data character decoder of rd-with based on the 5b/6b control character decoder of rd-.Back 4 Bit datas are after the preliminary treatment of 4b pretreatment module, and the second data character data data_4b of generation and the second control character data ctl_4b are sent to respectively based on the 3b/4b data character decoder of rd-with based on the 3b/4b control character decoder of rd-.At last, the data behind four decoder decodes all are sent to data and merge module, and these data merge module and select suitable data from these data, are merged into the data of 8 bits and pass through data output end dout output.The first XOR module produces the second change in polarity indications signal rd_6b by the first change in polarity indications signal rd_flag_6b of 6b pretreatment module output and current character polar signal crd are carried out xor operation, is used for controlling the 4b pretreatment module and does further computing.The second XOR module is carried out xor operation by the second change in polarity indications signal rd_flag_4b and the second change in polarity indications signal rd_6b to the output of 4b pretreatment module, produces next character polar signal nrd and output.
Described 6b pretreatment module with the process that preceding 6 bits input data change into the data that can carry out the rd-decoding is, if the current character polar signal crd of outside input is the rd+ territory, then will import data and be transformed into the rd-territory according to data character transformation rule and control character transformation rule from the rd+ territory respectively, be sent to based on the 5b/6b data character decoder of rd-with based on the 5b/6b control character decoder of rd-by its output respectively; If the current character polar signal crd of outside input is the rd-territory, then directly will imports data and be sent to based on the 5b/6b data character decoder of rd-with based on the 5b/6b control character decoder of rd-by its output respectively; In the semipolar variation of data preprocessing process, export by the first change in polarity indications signal rd_flag_6b.
Described 4b pretreatment module with the process that back 4 bits input data change into the data that can carry out the rd-decoding is, if the current character polar signal crd of outside input is the rd+ territory, then will import data and be transformed into the rd-territory according to data character transformation rule and control character transformation rule from the rd+ territory respectively, be sent to based on the 3b/4b data character decoder of rd-with based on the 3b/4b control character decoder of rd-by its output respectively; If the current character polar signal crd of outside input is rd-, then directly will imports data and be sent to based on the 3b/4b data character decoder of rd-with based on the 3b/4b control character decoder of rd-by its output respectively; In the semipolar situation of change of data preprocessing process, export by the second change in polarity indications signal rd_flag_4b.
Described 5b/6b data character decoder based on rd-is based on the regular decoder that carries out the 5b/6b decode operation of rd-decoding of data character, that does is operating as: the described first data character data data_6b is carried out the 5b/6b decoding according to the rd-decoding rule of data character, produce the described first data character decoded data dout_data_6b, described first data character decoding indications signal flag_data_6b is used for then representing whether this decode operation is successful.
Described 5b/6b control character decoder based on rd-is based on the regular decoder that carries out the 5b/6b decode operation of rd-decoding of control character, that does is operating as: the described first control character data ctl_6b is carried out the 5b/6b decoding according to the rd-decoding rule of control character, produce the described first control character decoded data dout_ctl_6b, described first control character decoding indications signal flag_ctl_6b is used for then representing whether this decode operation is successful.
Described 3b/4b data character decoder based on rd-is based on the regular decoder that carries out the 3b/4b decode operation of rd-decoding of data character, that does is operating as: the described second data character data data_4b is carried out the 3b/4b decoding according to the rd-decoding rule of data character, produce described second data character decoded data dout_data_4b output, described second data character decoding indications signal flag_data_4b is used for then representing whether this decode operation is successful.
Described 3b/4b control character decoder based on rd-is based on the regular decoder that carries out the 3b/4b decode operation of rd-decoding of control character, that does is operating as: the described second control character data ctl_4b is carried out the 3b/4b decoding according to the rd-decoding rule of control character, produce the described second control character decoded data dout_ctl_4b, described second control character decoding indications signal flag_ctl_4b is used for then representing whether this decode operation is successful.
It is to select suitable data from four groups of input data that described data merge module, is merged into data and the output of eight bits; That does is operating as: if described first data character decoding indications signal flag_data_6b and described second data character decoding indications signal flag_data_4b represent that decode operation separately is successful, then with the described first data character decoded data dout_data_6b as low 5, the described second data character decoded data dout_data_4b is as high 3, be merged into the described output data of 8 bit bit wides, and described indicator signal symbol represents current output is data character; If described first control character decoding indications signal flag_ctl_6b and described second control character decoding indications signal flag_ctl_4b represent that decode operation separately is successful, then with the described first control character decoded data dout_ctl_6b as low 5, the described second control character decoded data dout_ctl_4b is as high 3, be merged into the described output data of 8 bit bit wides, and described indicator signal symbol represents current output is control character.
The described first XOR module is that the current character polar signal crd of outside input and the first change in polarity indications signal rd_flag_6b of 6b pretreatment module are done XOR, and exports the second change in polarity indications signal rd_6b by output.
The described second XOR module is that the second change in polarity indications signal rd_flag_4b to the second change in polarity indications signal rd_6b and 4b pretreatment module does XOR, and exports next character polar signal nrd by output.
Be a specific embodiment below.
By reference to the accompanying drawings, when the data of outside input are 10 ' b10_1000_0011, and current character polar signal crd is when being the rd+ territory, and preceding 6 Bit datas that data split are 6 ' b00_0011, and back 4 Bit datas are 4 ' b1010.
In the 6b pretreatment module, after preceding 6 Bit datas and current character polar signal crd send into the 6b pretreatment module, because current character polar signal crd is the rd+ territory, opposite with the polarity of decoding, be transformed into the rd-territory according to data character transformation rule and control character transformation rule from the rd+ territory respectively so will import data 6 ' b00_0011, the first data character data data_6b that obtains and the first control character data ctl_6b are 6 ' b11_1100, and change has taken place the represented polarity of the first change in polarity indications signal rd_flag_6b of 6b pretreatment module.
In the first XOR module, because change has taken place the represented polarity of the first change in polarity indications signal rd_flag_6b, so the second change in polarity indications signal rd_6b is the negate of current character polar signal crd, be the rd-territory.
In the 4b pretreatment module, after back 4 Bit datas and the second change in polarity indications signal rd_6b send into the 4b pretreatment module, because the polarity of the second change in polarity indications signal rd_6b is the rd-territory, identical with the polarity of decoding, so will import data directly by its output output, the second data character data data_4b and the second control character data ctl_4b are 4 ' b1010, and change has also taken place the represented polarity of the second change in polarity indications signal rd_flag_4b of 4b pretreatment module output.
In the second XOR module, because change has taken place the represented polarity of the second change in polarity indications signal rd_flag_4b, so next character polar signal nrd is the negate of the second change in polarity indications signal rd_6b, be the rd+ territory.
In the 5b/6b data character decoder based on rd-, after input data 6 ' b11_11001 carried out carrying out the 5b/6b decoding based on the rd-decoding rule of data character, obtaining the first data character decoded data dout_data_6b is 5 ' b0, and first data character decoding indications signal flag_data_6b is expressed as failure.
In the 5b/6b control character decoder based on rd-, after input data 6 ' b11_1100 carried out carrying out the 5b/6b decoding based on the rd-decoding rule of control character, the first control character decoded data dout_ctl_6b that obtains is 5 ' b1_1100, and first control character decoding indications signal flag_ctl_6b is expressed as success.
In the 3b/4b data character decoder based on rd-, after input data 4 ' b1010 carried out carrying out the 3b/4b decoding based on the rd-decoding rule of data character, the second data character decoded data dout_data_4b that obtains is 3 ' b010, and second data character decoding indications signal flag_data_4b is expressed as success;
In the 3b/4b control character decoder based on rd-, after input data 4 ' b1010 carried out carrying out the 3b/4b decoding based on the rd-decoding rule of control character, the second control character decoded data dout_ctl_4b that obtains is 3 ' b101, and second control character decoding indications signal flag_ctl_4b is expressed as success.
Merge in the module in data, after receiving four groups of data after decoded, because first data character decoding indications signal flag_data_6b is expressed as failure, and first control character decoding indications signal flag_ctl_6b and second control character decoding indications signal flag_ctl_4b are expressed as success, so the output data are made up of the first control character decoded data dout_ctl_6b and the second control character decoded data dout_ctl_4b, wherein the first control character decoded data dout_ctl_6b does low 5, the second control character decoded data dout_ctl_4b does high 3, data after the merging are: 8 ' b1011_1100, and indicator signal symbol is expressed as control character, i.e. K28.5.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. 8b/10b decoding circuit based on rd-is characterized in that: by 6b pretreatment module, 4b pretreatment module, based on the 5b/6b data character decoder of rd-, based on the 5b/6b control character decoder of rd-, based on the 3b/4b data character decoder of rd-, merge module and two XOR modules constitute based on 3b/4b control character decoder, the data of rd-;
Outer input data is 10 Bit datas, and this 10 Bit data is split as preceding 6 Bit datas and back 4 Bit datas, and described preceding 6 Bit datas are input to described 6b pretreatment module, and described back 4 Bit datas are input to described 4b pretreatment module;
One current character polar signal is input to described 6b pretreatment module and the first XOR module respectively; This current character polar signal is represented the polarity of current input character, described 6b pretreatment module is carried out pretreatment operation to described preceding 6 Bit datas under the control of current character polar signal, and export the first data character data, the first control character data and the first change in polarity indications signal;
The first XOR module is used for described current character polar signal and the described first change in polarity indications signal are carried out the XOR processing and export the second character polar signal;
The described second character polar signal is input to described 4b pretreatment module and the second XOR module respectively; Described 4b pretreatment module is carried out pretreatment operation to described back 4 Bit datas under the control of the second character polar signal, and exports the second data character data, the second control character data and the second change in polarity indications signal;
The described second XOR module is used for the described second character polar signal and the described second change in polarity indications signal are carried out the XOR processing, produces next character polar signal, and described next character polar signal is externally exported;
The described first data character data are input to described 5b/6b data character decoder based on rd-and handle, and export the first data character decoded data and first data character decoding indications signal;
The described first control character data are input to described 5b/6b control character decoder based on rd-and handle, and export the first control character decoded data and first control character decoding indications signal;
The described second data character data are input to described 3b/4b data character decoder based on rd-and handle, and export the second data character decoded data and second data character decoding indications signal;
The described second control character data are input to described 3b/4b control character decoder based on rd-and handle, and export the second control character decoded data and second control character decoding indications signal;
The described first data character decoded data, first data character decoding indications signal, the first control character decoded data, first control character decoding indications signal, the second data character decoded data, second data character decoding indications signal, the second control character decoded data and second control character decoding indications signal are input to described data and merge module, handle and export output data and an indicator signal of one 8 bits.
2. decoding circuit as claimed in claim 1, it is characterized in that: described 6b pretreatment module changes into described preceding 6 Bit datas the data that can carry out rd-decoding computing, if the described current character polar signal of outside input is rd+, then described preceding 6 Bit datas are transformed into the rd-territory according to data character transformation rule and control character transformation rule from the rd+ territory respectively, and will transform the first data character data that the back produces, the first control character data are sent to respectively based on the 5b/6b data character decoder of rd-with based on the 5b/6b control character decoder of rd-; If the described current character polar signal of outside input is rd-, then described preceding 6 Bit datas directly produce the first data character data, the first control character data, and be sent to respectively based on the 5b/6b data character decoder of rd-with based on the 5b/6b control character decoder of rd-; The change in polarity situation that takes place in the data preprocessing process is exported by the first change in polarity indications signal.
3. decoding circuit as claimed in claim 1, it is characterized in that: described 4b pretreatment module changes into the data that can carry out rd-decoding computing with described back 4 Bit datas, if the described second character polar signal is rd+, then described back 4 Bit datas are transformed into the rd-territory according to data character transformation rule and control character transformation rule from the rd+ territory respectively, and will transform the second data character data that the back produces, the second control character data are sent to respectively based on the 3b/4b data character decoder of rd-with based on the 3b/4b control character decoder of rd-; If the described second character polar signal is rd-, then described back 4 Bit datas directly produce the second data character data, the second control character data, and be sent to respectively based on the 3b/4b data character decoder of rd-with based on the 3b/4b control character decoder of rd-; The change in polarity situation that takes place in the data preprocessing process is exported by the second change in polarity indications signal.
4. decoding circuit as claimed in claim 1, it is characterized in that: described 5b/6b data character decoder based on rd-is based on the regular decoder that carries out the 5b/6b decode operation of rd-decoding of data character, that does is operating as: the described first data character data are carried out the 5b/6b decoding according to the rd-decoding rule of data character, produce the described first data character decoded data, described first data character decoding indications signal is used for then representing whether this decode operation is successful.
5. decoding circuit as claimed in claim 1, it is characterized in that: described 5b/6b control character decoder based on rd-is based on the regular decoder that carries out the 5b/6b decode operation of rd-decoding of control character, that does is operating as: the described first control character data are carried out the 5b/6b decoding according to the rd-decoding rule of control character, produce the described first control character decoded data, described first control character decoding indications signal is used for then representing whether this decode operation is successful.
6. decoding circuit as claimed in claim 1, it is characterized in that: described 3b/4b data character decoder based on rd-is based on the regular decoder that carries out the 3b/4b decode operation of rd-decoding of data character, that does is operating as: the described second data character data are carried out the 3b/4b decoding according to the rd-decoding rule of data character, produce the described second data character decoded data, described second data character decoding indications signal is used for then representing whether this decode operation is successful.
7. decoding circuit as claimed in claim 1, it is characterized in that: described 3b/4b control character decoder based on rd-is based on the regular decoder that carries out the 3b/4b decode operation of rd-decoding of control character, that does is operating as: the described second control character data are carried out the 3b/4b decoding according to the rd-decoding rule of control character, produce the described second control character decoded data, described second control character decoding indications signal is used for then representing whether this decode operation is successful.
8. decoding circuit as claimed in claim 1 is characterized in that: it is to select suitable data from four groups of input data that described data merge module, is merged into data and the output of 8 bits; That does is operating as: if described first data character decoding indications signal and described second data character decoding indications signal represent that all decode operation separately is successful, then with the described first data character decoded data as low 5, the described second data character decoded data is as high 3, be merged into the described output data of 8 bit bit wides, and described indicator signal represents current output is data character; If described first control character decoding indications signal and described second control character decoding indications signal represent that all decode operation separately is successful, then with the described first control character decoded data as low 5, the described second control character decoded data is as high 3, be merged into the described output data of 8 bit bit wides, and described indicator signal represents current output is control character.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1529941A (en) * | 2001-05-08 | 2004-09-15 | 国际商业机器公司 | 8B/10B encoding and decoding for high speed applications |
| US20040233075A1 (en) * | 2003-05-22 | 2004-11-25 | Park Chang Won | 8B/10B encoder/decoder including logic gates |
| CN101674089A (en) * | 2009-10-19 | 2010-03-17 | 中国科学院声学研究所 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1529941A (en) * | 2001-05-08 | 2004-09-15 | 国际商业机器公司 | 8B/10B encoding and decoding for high speed applications |
| US20040233075A1 (en) * | 2003-05-22 | 2004-11-25 | Park Chang Won | 8B/10B encoder/decoder including logic gates |
| CN101674089A (en) * | 2009-10-19 | 2010-03-17 | 中国科学院声学研究所 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
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