CN103199101A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN103199101A CN103199101A CN2012100040349A CN201210004034A CN103199101A CN 103199101 A CN103199101 A CN 103199101A CN 2012100040349 A CN2012100040349 A CN 2012100040349A CN 201210004034 A CN201210004034 A CN 201210004034A CN 103199101 A CN103199101 A CN 103199101A
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Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conduction-type substrate which is provided with an upper surface of the substrate. The semiconductor structure comprises a protected element, at least one annular buried channel and at least one annular doping section, wherein the protected element is formed in the substrate, the at least one annular buried channel is formed below the upper surface of the substrate, through a top view, the buried channel encloses the protected element and is provided with a first depth, the at least one annular doping section is formed below the upper surface of the substrate, through a top view, the doping section encloses the buried channel, the doping section is in a second conduction-type and is provided with a second depth, and the second depth is no less than the first depth.
Description
Technical field
The present invention relates to a kind of semiconductor structure and manufacture method thereof, refer to a kind of semiconductor structure and manufacture method thereof that improves crash guard voltage especially.
Background technology
Please refer to Fig. 3, show the equipotential line simulation drawing of prior art protective ring (guard ring) structure under reverse bias.The protective ring structure generally is coupled to earthing potential or suspension joint, the protected element (not shown) that its purpose centers in protection protective ring structure.In detail; when protected element operation; in protected element periphery; if there is not the protective ring structure; when the peripheral wellblock of protected element is subjected to reverse bias; equipotential line in the exhaustion region can form intensive tip in protected element periphery, and the physical structure that electric field can surpass protected element can bear.Therefore, its crash guard voltage is relatively low.
As shown in Figure 3, prior art protective ring structure comprises buries groove 23 and doped region 25, in order to relax the equipotential line of protected element periphery, makes electric field descend, and the voltage that protected element can bear increases, thereby improves its crash guard voltage.
Yet along with the needs of element application and area micro, crash guard voltage more and more is difficult to keep.
In view of this; the present invention is namely at above-mentioned the deficiencies in the prior art; a kind of semiconductor structure and manufacture method thereof are proposed; under the situation that does not increase element area and too much fabrication steps; improve the crash guard voltage of protected element; increasing the range of application of protection component, and can be integrated in the processing procedure of low voltage component.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art and defective, proposes a kind of semiconductor structure and manufacture method thereof.
For reaching above-mentioned purpose, the invention provides a kind of semiconductor structure, be formed in the one first conductivity type substrate, this first conductivity type substrate has a upper surface, and this semiconductor structure comprises: protected element is formed in this first conductivity type substrate; At least one first ring-type is buried groove, is formed at this upper surface below, looks it by top view, and this first ring-type is buried groove around this protected element, and this first ring-type to bury groove downward from this upper surface, have first degree of depth; And at least one ring-type doped region, be formed at this upper surface below, look it by top view, this ring-type doped region buries groove around this first ring-type, and the conductivity type of this ring-type doped region is second conductivity type, and this ring-type doped region is downward from this upper surface, has second degree of depth; Wherein, this second degree of depth is not less than this first degree of depth.
For reaching above-mentioned purpose, with regard to another viewpoint, the present invention also provides a kind of semiconductor structure manufacture method, comprises: one first conductivity type substrate is provided, and it has a upper surface; Form a protected element in this first conductivity type substrate; Form at least one first ring-type and bury groove in this upper surface of base plate below, look it by top view, this first ring-type is buried groove around this protected element, and this first ring-type to bury groove downward from this upper surface, have first degree of depth; And form at least one ring-type doped region in this upper surface below, and look it by top view, this doped region buries groove around this first ring-type, and the conductivity type of this ring-type doped region is second conductivity type, and this ring-type doped region is downward from this upper surface, has second degree of depth; Wherein, this second degree of depth is not less than this first degree of depth.
In a kind of preferred embodiment, this protected element should comprise a high voltage device.
In the above-described embodiments, this semiconductor structure should more comprise one second conductivity type substrate, be positioned at this first conductivity type substrate below, wherein this high voltage device is an insulated gate bipolar transistor (insulate gate bipolar transistor, IGBT), this second conductivity type substrate is in order to the collector as this IGBT.
In another kind of preferred embodiment, this ring-type doped region should comprise: at least one second ring-type is buried groove, is formed at this upper surface below, looks it by top view, and this second ring-type is buried groove and buried groove around this first ring-type; And at least one coating-doping district, bury groove corresponding to this second ring-type, be formed at this second ring-type and bury in peripheral this first conductivity type substrate of groove, in this upper surface below, coat this second ring-type and bury groove.
In the above-described embodiments, this second ring-type is buried groove and this first ring-type and is buried groove and should utilize the same process step to form, and this coating-doping district implants speeding-up ion by ion embedding technology with different angles and forms.
Illustrate in detail below by specific embodiment, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and reaches.
Description of drawings
Figure 1A-1F shows first embodiment of the present invention;
Fig. 2 A-2C shows second embodiment of the present invention;
Fig. 3,4 and 5 shows the equipotential line simulation drawing of semiconductor structure (protective ring structure) under reverse bias of three kinds of different depth d1 and depth d 2 ratios;
Fig. 6 shows in the semiconductor structure of the present invention protected element embodiment more specifically.
Symbol description among the figure
10,11 substrates
13,23 bury groove
15,25,352 doped regions
17 protected elements
19IGBT
191 bodies
193 emitter-base bandgap gradings
195 grids
197 collectors
111 upper surfaces
131 grooves
132 oxide layers
351 photoresistances
D1, the d2 degree of depth
Embodiment
Graphic among the present invention all belongs to signal, mainly is intended to represent the orbution up and down between fabrication steps and each layer, as for shape, thickness and width then not according to scale.
See also Figure 1A-1F, show first embodiment of the present invention.Wherein, Figure 1A-1E shows the manufacturing process cross-sectional schematic of present embodiment; Fig. 1 F shows the top view of present embodiment semiconductor structure.Shown in Figure 1A, substrate 11 at first is provided, it is for example and without limitation on P type silicon substrate (not shown), formed N-type epitaxial layer.Then, below substrate 11 upper surfaces 111, form at least one annular ditch groove 131, shown in Figure 1B cutaway view.Annular ditch groove 131 is such as but not limited to utilizing in same substrate, and (shallow trench isolation, STI) the part same process step in the structure forms to form shallow trench isolation.Then in substrate 11 upper surfaces 111, form oxide layer 132, shown in Fig. 1 C, so, will form insulating barrier in annular ditch groove 131 internal side wall and bottom.Wherein, started at by substrate 11 upper surfaces 111, the degree of depth of annular ditch groove 131 is depth d 1 as shown in the figure.Next in annular ditch groove 131 inside that covered by oxide layer 132, such as but not limited to the polycrystalline silicon material of inserting P type or N-type, and the ring-type that forms shown in Fig. 1 D is buried groove 13.
Then, for example forming photoresistance by little shadow technology is shielding, treat the regional (not shown) of implant impurity with definition, and with ion embedding technology, with p type impurity, with the form of speeding-up ion, implant in the zone of definition, form at least one ring-type doped region 15, ring-type doped region 15 is positioned at substrate 11 upper surfaces 111 belows, shown in cutaway view Fig. 1 E.Wherein, started at by substrate 11 upper surfaces 111, the degree of depth of ring-type doped region 15 is depth d 2 as shown in the figure.It is noted that depth d 2 is not less than aforementioned depth d 1.
Fig. 1 F shows the top view of present embodiment semiconductor structure.Wherein, a plurality of ring-types are buried groove 13 around protected element 17, and a plurality of ring-type doped region 15 buries groove 13 around ring-type.Wherein, protected element 17 is for example and without limitation to high voltage device, and this high voltage device be for example and without limitation to insulated gate bipolar transistor (insulate gate bipolar transistor, IGBT).It should be noted that the cutaway view shown in Figure 1A-1E for example is among Fig. 1 F, the cutaway view that hatching line AA ' cuts out.
Depth d 2 is not less than depth d 1 and is emphasis of the present invention, looks it by cutaway view Fig. 1 E, and preferred implementation is that depth d 2 is greater than depth d 1.The advantage of this kind arrangement is on component specification, can improve the crash guard voltage of protected element 17.
Fig. 2 A-2C shows second embodiment of the present invention.Shown in Fig. 2 A, substrate 11 at first is provided, it is for example and without limitation on P type silicon substrate (not shown), formed N-type epitaxial layer.Then, below substrate 11 upper surfaces, form at least one annular ditch groove 131, annular ditch groove 131 is such as but not limited to utilizing in same substrate, and the part same process step that forms in the sti structure forms.Then in substrate 11 upper surfaces, form oxide layer 132, this can form insulating barrier in annular ditch groove 131 internal side wall and bottom.Wherein, started at by substrate 11 upper surfaces, the degree of depth of annular ditch groove 131 is depth d 1 as shown in the figure.Then, form photoresistance 351 by little shadow technology and be shielding, treat the zone of implant impurity with definition, and with ion embedding technology, with p type impurity, with the form of speeding-up ion, implant in the zone of definition, form at least one coating-doping district 352, coating-doping district 352 is positioned at substrate 11 upper surfaces below, shown in cutaway view Fig. 2 B.Wherein, the degree of depth in coating-doping district 352 is started at by substrate 11 upper surfaces, is the depth d 2 shown in Fig. 2 B.It is noted that depth d 2 is not less than aforementioned depth d 1.Next remove after the photoresistance 351, in annular ditch groove 131 inside that covered by oxide layer 132, such as but not limited to the polycrystalline silicon material of inserting P type or N-type, and the ring-type of formation shown in Fig. 2 C buries groove 13 and ring-type is buried groove 35.
Different with first embodiment is, the coating-doping district 352 of present embodiment is different with the doped region 15 of first embodiment, the one, annular ditch groove 131 peripheries of the coating-doping district 352 of present embodiment in institute's defined range, the doping p type impurity coats the annular ditch groove of choosing 131, the advantage of this practice is, reduce in the ion embedding technology, speeding-up ion will run through the difficulty of the dark substrate degree of depth; And another difference exists, and present embodiment need be implanted with different angles and accelerate the p type impurity ion when forming coating-doping district 352 with ion embedding technology, illustrates as dotted arrow among the figure, to reach needed Impurity Distribution.
First embodiment and second embodiment, compared to prior art, its etc. the voltage profile line density less, representative is under the same operation situation, during element conductive or not conducting just, the electric field of the embodiment of the invention is less, therefore can bear higher voltage, in other words, crash guard voltage is bigger.See also Fig. 3,4 and 5, show the equipotential line simulation drawing of semiconductor structure (protective ring structure) under reverse bias of three kinds of different depth d1 and depth d 2 ratios.Shown in Fig. 3,4 and 5, obviously find out when depth d 1 greater than (prior art as shown in Figure 3), equal (embodiment of the invention as shown in Figure 4), with less than (embodiment of the invention as shown in Figure 5) depth d 2 time, the equipotential line simulation drawing of semiconductor structure (protective ring structure) under reverse bias.According to Simulation result, Fig. 3, Fig. 4, with the reverse bias that the shown semiconductor structure of Fig. 5 can bear, be respectively 408V, 496V and 507V.Therefore, utilize the present invention can obviously increase the crash guard voltage of element.
In other words, please consult Fig. 3,4 and 5 simultaneously, embodiments of the invention as can be seen are compared to prior art, its etc. the voltage profile line density less, representative is under the same operation situation, and P type substrate 10 is electrically connected to negative voltage, and N-type substrate 11 is electrically connected to positive voltage, during with the formation reverse bias, the electric field of the embodiment of the invention is less, therefore can bear higher voltage, and crash guard voltage is bigger.
Fig. 6 shows that in the semiconductor structure of the present invention, protected element is embodiment more specifically, and as shown in the figure, protected element is such as but not limited to comprising a kind of high voltage device, N channel IGBT 19, comprise P type body 191, emitter-base bandgap grading 193, grid 195, with collector 197.Wherein, N-type substrate 10 is electrically connected the collector 197 of IGBT 19, when IGBT 19 reverse bias are operated, just collector 197 is electrically connected to negative voltage, when P type substrate 11 is electrically connected to positive voltage, utilize semiconductor structure of the present invention, can improve crash guard voltage.
Below at preferred embodiment the present invention is described, just the above for making those skilled in the art be easy to understand content of the present invention, is not to limit interest field of the present invention only.Under same spirit of the present invention, those skilled in the art can think and various equivalence changes.For example, not influencing under the main characteristic of element, can add other fabrication steps or structure, as deep-well district etc.; And for example, little shadow technology is not limited to the light shield technology, also can comprise the little shadow technology of electron beam; For another example, the ring-type shown in second embodiment is buried the annular ditch groove 131 that groove 13 and ring-type bury in the groove 35 and is utilized same process to form, and is a kind of embodiment wherein, can also utilize different processing procedures to form, as long as can form the result that depth d 2 is not less than depth d 1; Again for another example, similar to the explanation of first embodiment, other embodiment can also be applied to other N-type coating-doping district 352 or 15, when being applied to N-type coating-doping district 352 or 15, as long as relevant P type and N-type impurity are exchanged.Protection scope of the present invention should contain above-mentioned and other all equivalences change.
Claims (10)
1. a semiconductor structure is formed in the one first conductivity type substrate, and this first conductivity type substrate has a upper surface, it is characterized in that this semiconductor structure comprises:
Protected element is formed in this first conductivity type substrate;
At least one first ring-type is buried groove, is formed at this upper surface below, looks it by top view, and this first ring-type is buried groove around this protected element, and this first ring-type to bury groove downward from this upper surface, have first degree of depth; And
At least one ring-type doped region is formed at this upper surface below, looks it by top view, and this ring-type doped region buries groove around this first ring-type, and the conductivity type of this ring-type doped region is second conductivity type, and this ring-type doped region is downward from this upper surface, has second degree of depth;
Wherein, this second degree of depth is not less than this first degree of depth.
2. semiconductor structure as claimed in claim 1, wherein, this protected element comprises a high voltage device.
3. semiconductor structure as claimed in claim 2, wherein, also comprise one second conductivity type substrate, be positioned at this first conductivity type substrate below, wherein this high voltage device is an insulated gate bipolar transistor, and this second conductivity type substrate is electrically connected the collector of this insulated gate bipolar transistor.
4. semiconductor structure as claimed in claim 1, wherein, this ring-type doped region comprises:
At least one second ring-type is buried groove, is formed at this upper surface below, looks it by top view, and this second ring-type is buried groove and buried groove around this first ring-type; And
Groove buries corresponding to this second ring-type at least one coating-doping district, is formed at this second ring-type and buries in peripheral this first conductivity type substrate of groove, in this upper surface below, coats this second ring-type and buries groove.
5. semiconductor structure as claimed in claim 4, wherein, this second ring-type is buried groove and this first ring-type and is buried groove and utilize the same process step to form, and this coating-doping district implants speeding-up ion by ion embedding technology with different angles and forms.
6. a semiconductor structure manufacture method is characterized in that, comprises:
One first conductivity type substrate is provided, and it has a upper surface;
Form a protected element in this first conductivity type substrate;
Form at least one first ring-type and bury groove in this upper surface of base plate below, look it by top view, this first ring-type is buried groove around this protected element, and this first ring-type to bury groove downward from this upper surface, have first degree of depth; And
Form at least one ring-type doped region in this upper surface below, look it by top view, this doped region buries groove around this first ring-type, and the conductivity type of this ring-type doped region is second conductivity type, and this ring-type doped region is downward from this upper surface, has second degree of depth;
Wherein, this second degree of depth is not less than this first degree of depth.
7. semiconductor structure manufacture method as claimed in claim 6, wherein, this protected element comprises a high voltage device.
8. semiconductor structure manufacture method as claimed in claim 7, wherein, also comprise formation one second conductivity type substrate in this first conductivity type substrate below, wherein this high voltage device is an insulated gate bipolar transistor, and this second conductivity type substrate is electrically connected the collector of this insulated gate bipolar crystal.
9. semiconductor structure manufacture method as claimed in claim 6, wherein, this step that forms at least one ring-type doped region comprises:
Form at least one second ring-type and bury groove in this upper surface below, look it by top view, this second ring-type is buried groove and is buried groove around this first ring-type; And
Form at least one coating-doping district, bury groove corresponding to this second ring-type and bury in peripheral this first conductivity type substrate of groove in this second ring-type, in this upper surface below, coat this second ring-type and bury groove.
10. semiconductor structure manufacture method as claimed in claim 9, wherein, this second ring-type is buried groove and this first ring-type and is buried groove and utilize the same process step to form, and this coating-doping district implants speeding-up ion by ion embedding technology with different angles and forms.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100040349A CN103199101A (en) | 2012-01-06 | 2012-01-06 | Semiconductor structure and manufacturing method thereof |
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| CN2012100040349A CN103199101A (en) | 2012-01-06 | 2012-01-06 | Semiconductor structure and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667590A (en) * | 2008-09-04 | 2010-03-10 | 三洋电机株式会社 | Semiconductor device and method of manufacturing the same |
| US20110042714A1 (en) * | 2009-08-19 | 2011-02-24 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US20110210372A1 (en) * | 2010-03-01 | 2011-09-01 | Stmicroelectronics (Tours) Sas | High-voltage vertical power component |
| CN102214582A (en) * | 2011-05-26 | 2011-10-12 | 上海先进半导体制造股份有限公司 | Method for manufacturing terminal structure of deep-groove super-junction metal oxide semiconductor (MOS) device |
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- 2012-01-06 CN CN2012100040349A patent/CN103199101A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667590A (en) * | 2008-09-04 | 2010-03-10 | 三洋电机株式会社 | Semiconductor device and method of manufacturing the same |
| US20110042714A1 (en) * | 2009-08-19 | 2011-02-24 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US20110210372A1 (en) * | 2010-03-01 | 2011-09-01 | Stmicroelectronics (Tours) Sas | High-voltage vertical power component |
| CN102214582A (en) * | 2011-05-26 | 2011-10-12 | 上海先进半导体制造股份有限公司 | Method for manufacturing terminal structure of deep-groove super-junction metal oxide semiconductor (MOS) device |
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Application publication date: 20130710 |