CN103187090A

CN103187090A - Storage arrays and storage

Info

Publication number: CN103187090A
Application number: CN2013100888526A
Authority: CN
Inventors: 俞冰
Original assignee: Xian Sinochip Semiconductors Co Ltd
Current assignee: Xian Sinochip Semiconductors Co Ltd
Priority date: 2013-03-19
Filing date: 2013-03-19
Publication date: 2013-07-03

Abstract

The invention relates to a storage array and a storage adopting the same. The storage array comprises normal storage arrays and special storage arrays, wherein the special storage arrays are arranged on the two sides of the normal storage arrays. The storage array is characterized in that the special storage arrays comprise bit lines which are folded, and storage units are connected to the two ends of each folded bit line. The storage array and a storage adopting the same provided by the invention can omit relevant control circuits and fuse structures, and save testing time and chip area.

Description

A kind of storage array and storer

Technical field

The present invention relates to a kind of storage array, and the storer that contains this storage array.

Background technology

Referring to Fig. 1, along with dwindling of process, for reducing the chip area of unit size, generally adopt the open bit lines less affected by adjacent ones structure.1,3,5th, storage array is made up of one or more word line wl and bit line (BL_0, BL_e), and 2,4th, the sense amplifier array is made up of one or more sense amplifiers.When storage array 3 is operated, word line WL in 3 is activated, other word line is in unactivated state, the bit line of information by linking to each other with storage unit of the storage unit that links to each other with this word line, be even bitlines BL_e and odd bit lines BL_o, be delivered to the sense amplifier in 2,4, can carry out read-write operation to storage unit by this sense amplifier.Be input to 2,4 bit line has two kinds, a kind of storage array that to operate that comes from, be used for transmitting the information of storage unit, another kind comes from the storage array that is not activated, as the benchmark of sense amplifier, therefore need 2 and 4 two sense amplifier arrays to handle the data of a storage unit on the word line.And need all in addition for the read-write operation of any one storage array that two adjacent storage arrays provide reference bit line.

Because the open bit lines less affected by adjacent ones structure namely needs adjacent storage array that reference bit line is provided, in order to read and write the storage array on border, needing to add extra storage array provides reference bit line.

Referring to Fig. 2, wherein 0,1,2,3,4,5,6,7 is normal storage array, 0 ' with 7 ' be extra storage array.Normal storage array has the storage unit of identical chip area and similar number with extra storage array.Because the storage unit in two extra storage arrays that add can not be read and write, and has adopted structure shown in Fig. 3 in order to increase operation rate, wherein 1,2,3,4,5,6,7 is the normal storage array, 0 ' with 0 " be special storage array.The normal storage array has the storage unit of identical chip area and similar number with special storage array.Special storage array 0 ' and 0 " in, have only half storage unit to be read and write respectively, namely 0 ' with 0 " form a normal storage array.With respect to the structure among Fig. 2, the chip area that whole storer uses reduces, and has improved utilization factor.But because 0 ' and 0 " in the word line logically be identical wordline address, therefore need waste the microarray biochip area for two identical control circuits of special elements outfit.

When storer was made, because the degeneration of the restriction of manufacturing process and stability, some storage unit possibly can't be worked, and in order to improve the product yield, has introduced the repair mode of redundant storage unit.These redundant storage units can be used for repairing the storage unit of inefficacy.In order to use these redundancy units, must be permanently logged in the circuit by the address of the storage unit of its replacement, but because the storage unit of these inefficacies just appearance, therefore address of introducing these storage unit that are replaced of laser fuse technical notes after producing.These fuses have adopted special process and special layout to take a large amount of chip areas, owing to carry out a large amount of time of action need of laser fuse, also make cost of products promote simultaneously.In the structure of Fig. 3, ' " middle word line has identical logical address but is again diverse location physically, therefore need " all dispose fuse, cause chip area and waste of time to make the cost of products raising for 0 ' and 0 with 0 because special storage array 0.

Summary of the invention

The technical matters of the present invention for existing in the solution background technology, and a kind of new storage array and the storer that contains this storage array are provided.

Technical solution of the present invention is: the present invention is a kind of storage array, comprises bit line, and its special character is: described bit line is folding bit line, and the two ends of folding bit line are connected to storage unit respectively.

Above-mentioned bit line is folding from the middle part, and two sections after folding are isometric.

Above-mentioned folded bit line is many, becomes symmetric offset spread.

A kind of storer that contains above-mentioned storage array, comprise normal storage array and special storage array, special storage array is arranged on the both sides of normal storage array, its special character is: described special storage array comprises bit line, bit line is folding bit line, and the two ends of folding bit line are connected to storage unit respectively.

Above-mentioned folded bit line is many, becomes symmetric offset spread.

The present invention proposes a kind of folded bit line structure, folding bit line length is identical with traditional bit line length, and the number of the storage unit that it linked to each other also the bit line with traditional is identical.All be in the normal storage array half and contain the chip area of special storage array of folding bit line and storage unit, so it has saved area of chip; Simultaneously because the storage unit that is connected with folding bit line in the special storage array does not need to carry out read-write operation, thereby corresponding control circuit and fuse-wires structure be can save, test duration and chip area saved.

Description of drawings

Fig. 1 is the chip structure synoptic diagram of available technology adopting open bit lines less affected by adjacent ones structure;

Fig. 2 is the array structure synoptic diagram of a kind of storer of the prior art;

Fig. 3 is the array structure synoptic diagram of another kind of storer of the prior art;

Fig. 4 is storage array of the present invention and storage array comparison diagram of the prior art;

Fig. 5 is the array structure synoptic diagram of storer of the present invention.

Embodiment

Referring to Fig. 4, the present invention has adopted a kind of new structure to reduce chip area and to shorten the test duration, and wherein 1 be the structure of the bit line in the background technology memory construction, and 2 be the structure of bit line proposed by the invention, and bit line is the bit line structure that folds.Identical in the bit line length and 1 in 2, and the number of the storage unit that is linked to each other is also identical.Bit line is folding from the middle part, and two sections after folding are isometric; Folded bit line is many, becomes symmetric offset spread.

Referring to Fig. 5, the memory construction of the bit line that the utilization that the present invention proposes is folding, wherein 0,1,2,3,4,5,6,7 is the normal storage array, I and II are special storage array.The chip area of special storage array I and II and storage unit all are half in the normal storage array.Special storage array I and II are used to

normal storage array

0 and 7 that reference bit line is provided, and storage unit wherein can not be read and write.As reference bit line, for guaranteeing that its resistance is identical with resistance and the electric capacity of normal bit line with electric capacity, it needs to have identical size with normal bit line and link to each other with the storage unit of same number, to guarantee can not introduce the cisco unity malfunction that unnecessary noise causes amplifier, therefore the bit line of special storage array I and II all adopts folding bit line.

Claims

1. a storage array comprises bit line, it is characterized in that: described bit line is folding bit line, and the two ends of described folding bit line are connected to storage unit respectively.

2. storage array according to claim 1 is characterized in that: described bit line is folding from the middle part, and two sections after folding are isometric.

3. storage array according to claim 1 and 2, it is characterized in that: described folded bit line is many, becomes symmetric offset spread.

4. storer that contains above-mentioned storage array, comprise normal storage array and special storage array, described special storage array is arranged on the both sides of normal storage array, it is characterized in that: described special storage array comprises bit line, described bit line is folding bit line, and the two ends of described folding bit line are connected to storage unit respectively.

5. storer according to claim 4 is characterized in that: described bit line is folding from the middle part, and two sections after folding are isometric.

6. according to claim 4 or 5 described storeies, it is characterized in that: described folded bit line is many, becomes symmetric offset spread.