CN103176450B - Servo drive and servo-control system - Google Patents
Servo drive and servo-control system Download PDFInfo
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- CN103176450B CN103176450B CN201310042883.8A CN201310042883A CN103176450B CN 103176450 B CN103176450 B CN 103176450B CN 201310042883 A CN201310042883 A CN 201310042883A CN 103176450 B CN103176450 B CN 103176450B
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Abstract
The invention discloses a kind of servo drive and servo-control system.Including: power module, processing module and addressable port module, the outfan of power module connects processing module and the power input of addressable port module respectively, provides power supply for processing module and addressable port module；Addressable port module at least includes first, second position feedback interface unit and power interface unit；The outfan of first, second position feedback interface unit is all connected with processing module, to being applied to obtain increment type, the coded data of absolute type encoder and carried out respective handling pass to processing module；The input of power interface unit connects the outfan of power module, according to configuration parameter be selectively first or the external encoder that connected of the second position feedback interface unit running voltage is provided.By the way, the present invention can compatible polytype, including the photoelectric rotary coder of identical or different running voltage.
Description
Technical field
The present invention relates to fields of numeric control technique, particularly relate to a kind of servo drive and servo-control system.
Background technology
Along with industrialization and the deep development of automatic technology, based on the motor of link control, the most high-end Serve Motor Control has become as the indispensable part affecting work efficiency and performance in full-automatic production line, industrial robot and digital control system.
Such as, in the three close-loop control theory of servomotor, in addition to electric current loop, the feedback of speed ring and position ring is required for obtaining the real time data of machine shaft and processes and control.And obtain machine shaft data the most efficiently, quickly and accurately and become the most important index affecting control accuracy and response speed in motor control.
Obtained the real time data of machine shaft motion by the additional encoder being connected to machine shaft end, be current comparative maturity, efficiently and accurately feedback system.Due to the convenience in technique and use, photoelectric rotary coder is in occupation of dominant position in the market.But, the encoder product that brand is numerous, operation principle, different communication protocol and the different running voltages that different coding device is the most different, not only allows terminal user be difficult to choose, and also allows motor drive relevant designer and engineer to hover between kinds of schemes selects.
As it is shown in figure 1, Fig. 1 is a kind of servo-control system common in the art.This servo-control system includes actuator 10, grating scale 11, servomotor 12, photoelectric rotary coder 13 and servo-driver 14.Wherein, servo-driver 14 includes FPGA unit 141, the turned position value of the machine shaft that photoelectric rotary coder 13 feeds back is counted, samples and segments by FPGA unit 141, and the result after processing passes to the motion-control module (DSP unit 142 as in Fig. 1) within servo-driver 14 and is analyzed calculating so that servo-driver 14 can run by control servomotor 12 accurate, high-precision.
So, the encoder interfaces on servo-driver directly influences dynamic property and the stable state accuracy of whole servosystem.
The photoelectric rotary coder Interface design scheme of servo-driver product is roughly divided into two categories below in the market:
(1) use single encoder interfaces, only support motor and the encoder specified.This kind of servo-driver is general with motor and a whole set of sale of encoder binding, a or a few money motor encoder only supporting to specify with a servo-driver.As only supported increment type TTL incremental encoder or absolute value SSI encoder, its encoder type supported when buying motor driver just it is specified that the device kind that can not alternate coding.Further, it normally only supports a kind of running voltage, such as 5V or 15V.
(2) use hybrid encoder interfaces, support absolute value encoder and incremental encoder simultaneously.This kind of servo-driver typically selects a kind of bus type communication protocol, can support the use with the encoder supporting same bus agreement.As EnDat communication protocol is compatible with incremental encoder or absolute value encoder or hybrid encoder.The encoder model that this kind of servo-driver is supported is more, and can alternate coding device kind the most according to the actual requirements.But, it the most only supports a kind of running voltage, such as 5V or 15V.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of servo drive and servo-control system, it is possible to compatible polytype, including the photoelectric rotary coder of identical or different running voltage.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of servo drive, including: power module, processing module and addressable port module, the outfan of power module connects processing module and the power input of addressable port module respectively, and then provides power supply for processing module and addressable port module；Addressable port module at least includes primary importance feedback interface unit, second position feedback interface unit and power interface unit；The outfan of primary importance feedback interface unit connects processing module, passes to processing module after being used for obtaining the coded data of incremental encoder and coded data being carried out respective handling；The outfan of second position feedback interface unit connects processing module, passes to processing module after being used for obtaining the coded data of absolute value encoder and coded data being carried out respective handling；The input of power interface unit connects the outfan of power module, and the external encoder connected by primary importance feedback interface unit or second position feedback interface unit according to the type selecting ground of configuration parameter, i.e. external encoder provides running voltage；Wherein, processing module includes FPGA unit, and the power input of FPGA unit connects the outfan of power module；The outfan of primary importance feedback interface unit and second position feedback interface unit connects the input/output terminal of FPGA unit respectively；Primary importance feedback interface unit includes sinusoidal wave incremental encoder interface circuit；Sinusoidal wave incremental encoder interface circuit includes the first operational amplifier, the second operational amplifier and ADC analog-digital converter；The outfan of the first operational amplifier and the second operational amplifier connects the input of ADC analog-digital converter respectively, and the outfan of ADC analog-digital converter connects the input/output terminal of FPGA unit；Primary importance feedback interface unit also includes TTL incremental encoder interface circuit；First operational amplifier of TTL incremental encoder interface circuit multiplexing sine wave incremental encoder interface circuit and the second operational amplifier, and farther include the first comparator, the second comparator and the 3rd comparator；The outfan of the first comparator, the second comparator and the 3rd comparator connects the input/output terminal of FPGA unit respectively, and, one input of the first comparator connects the outfan of the first operational amplifier, another input connects reference voltage, and an input of the second comparator connects the outfan of the second operational amplifier, another input connects reference voltage.
Wherein, the SIN differential signal of outside sinusoidal wave incremental encoder is become SIN single-ended signal and is sent to ADC analog-digital converter and carries out processing and obtain corresponding SIN signal after being changed by the first operational amplifier, the COS differential signal of outside sinusoidal wave incremental encoder is become COS single-ended signal and is sent to ADC analog-digital converter and carries out processing and obtain corresponding COS signal after being changed by the second operational amplifier, further, SIN signal and COS signal are finally transmitted to FPGA unit and carry out respective handling.
Wherein, the A phase differential signal of outside TTL incremental encoder becomes A phase single-ended signal after the first operational amplifier conversion, under the effect of the first comparator, A phase single-ended signal obtains A phase signals after comparing with reference voltage, the B phase differential signal of outside TTL incremental encoder becomes B phase single-ended signal after the second operational amplifier conversion, under the effect of the second comparator, B phase single-ended signal obtains B phase signals after comparing with reference voltage, the Z phase differential signal of outside TTL incremental encoder directly obtains Z phase signals after the 3rd comparator conversion, and, A phase signals, B phase signals and Z phase signals are finally transmitted to FPGA unit and carry out respective handling.
Wherein, second position feedback interface unit includes absolute value encoder interface circuit；Absolute value encoder interface circuit includes RS485 transceiver and RS485 transmitter, and wherein, one end of RS485 transceiver connects the input/output terminal of FPGA unit, and the input of RS485 transmitter connects the input/output terminal of FPGA unit；The DATA differential signal of outside absolute value encoder is converted into DATA single-ended signal through RS485 transceiver, DATA single-ended signal is transferred to FPGA unit and carries out respective handling, further, CLOCK single-ended signal is converted into CLOCK differential signal through RS485 transmitter and DATA single-ended signal is transferred to after RS485 transceiver is converted into DATA differential signal outside absolute value encoder carries out respective handling by FPGA unit.
Wherein, the first running voltage or the second running voltage are provided for external encoder to the external encoder type selecting that power interface unit is connected according to primary importance feedback interface unit or second position feedback interface unit.
Wherein, power interface unit is the DC/DC electric pressure converter of two-way output, and DC/DC electric pressure converter includes input, the first outfan, the second outfan and controls end；Wherein, the input of DC/DC electric pressure converter connects the outfan of power module, and the first outfan of DC/DC electric pressure converter exports the first running voltage, and the second outfan of DC/DC electric pressure converter exports the second running voltage；The feedback voltage level controlling end detection external encoder feedback of DC/DC electric pressure converter, and internal to feedback voltage level and the DC/DC electric pressure converter reference voltage level arranged is compared, when feedback voltage level differs with reference voltage level, carry out PWM pulsewidth modulation, so make external encoder stable be in the first running voltage or the second running voltage.
Wherein, the first running voltage is 5V, and the second running voltage is 10V.
Wherein, processing module includes DSP unit and host computer interface unit；The input/output terminal of DSP unit connects the input/output terminal of FPGA unit, and the input/output terminal of host computer interface unit connects the input/output terminal of DSP unit, and wherein, host computer interface unit is USB interface or Ethernet interface or RS232 serial ports.
For solving above-mentioned technical problem, another technical solution used in the present invention is: providing a kind of servo-control system, servo-control system includes the servo drive described by any of the above-described embodiment.
Wherein, servo-control system also includes servomotor, photoelectric rotary coder and host computer, and wherein, servo drive connects servomotor, photoelectric rotary coder and host computer respectively；Photoelectric rotary coder is arranged on servomotor, for measuring the relevant parameter of servo motor rotor, and relevant parameter is transferred to servo drive；Relevant parameter is processed and passes to host computer by servo drive；Host computer realizes the control to servomotor according to the relevant parameter obtained after processing.
nullThe invention has the beneficial effects as follows: be different from the situation of prior art，The present invention is by improving the addressable port of servo drive，Primary importance feedback interface unit is set、Second position feedback interface unit and power interface unit，Wherein，Primary importance feedback interface unit and second position feedback interface unit provide the addressable port of at least two type for external encoder，And，Can be according to primary importance feedback interface unit、The type of the external encoder that second position feedback interface unit is connected，By power interface Unit selection for primary importance feedback interface unit、The external encoder that second position feedback interface unit is connected provides running voltage，Can be compatible dissimilar、The photoelectric rotary coder of different operating voltage，And then the encoder type selecting scope of support can be expanded、Increase encoder type selecting motility、Reduce buying expenses and the shortcoming overcoming single running voltage to cause.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of servo-control system of prior art；
Fig. 2 is the structural representation of servo drive the first embodiment of the present invention；
Fig. 3 is the structural representation of servo drive the second embodiment of the present invention；
Fig. 4 is the electrical block diagram of servo drive shown in Fig. 3；
Fig. 5 is the structural representation of servo drive the 3rd embodiment of the present invention.
Detailed description of the invention
The present invention is described in detail with detailed description of the invention below in conjunction with the accompanying drawings.
It is the structural representation of servo drive the first embodiment of the present invention refering to Fig. 2, Fig. 2.Embodiment of the present invention includes: power module 101, processing module 102 and addressable port module 103.
Wherein, the outfan 1011,1012 of power module 101 connects power input 1021 and the power input of addressable port module 103 of processing module 102 respectively, and then provides power supply for processing module 102 and addressable port module 103.
Further, addressable port module 103 at least includes primary importance feedback interface unit 1031, second position feedback interface unit 1032 and power interface unit 1033.Wherein, the outfan 10310 of primary importance feedback interface unit 1031 connects processing module 102, passes to processing module 102 after being used for obtaining the coded data of incremental encoder and coded data being carried out respective handling；The outfan 10320 of second position feedback interface unit 1032 connects processing module 102, passes to processing module 102 after being used for obtaining the coded data of absolute value encoder and coded data being carried out respective handling.
Further, the input 10330 of power interface unit 1033 connects the outfan 1012 of power module 101, and the external encoder connected by primary importance feedback interface unit 1031 or second position feedback interface unit 1032 according to the type selecting of configuration parameter, i.e. external encoder ground provides running voltage.
nullEmbodiment of the present invention，By the addressable port of servo drive is improved，Primary importance feedback interface unit 1031 is set、Second position feedback interface unit 1032 and power interface unit 1033，Wherein，Primary importance feedback interface unit 1031 and second position feedback interface unit 1032 provide the addressable port of at least two type for external encoder，And，Can be according to primary importance feedback interface unit 1031、The type of the external encoder that second position feedback interface unit 1032 is connected，By power interface unit 1033 selectively primary importance feedback interface unit 1031、The external encoder that second position feedback interface unit 1032 is connected provides running voltage，Can be compatible dissimilar、The photoelectric rotary coder of different operating voltage，And then the encoder type selecting scope of support can be expanded、Increase encoder type selecting motility、Reduce buying expenses and the shortcoming overcoming single running voltage to cause.
Being the structural representation of servo drive the second embodiment of the present invention refering to Fig. 3 and Fig. 4, Fig. 3, Fig. 4 is the electrical block diagram of servo drive shown in Fig. 3.In embodiment of the present invention, processing module 202 includes FPGA (Field-ProgrammableGateArray, field programmable gate array) unit 2021 and DSP (DigitalSignalProcessing, Digital Signal Processing) unit 2022.
This FPGA unit 2021 includes power input 20210, the power input 20210 of FPGA unit 2021 connects the outfan 2011 of power module 201, one group of input/output terminal 20211 of FPGA unit 2021 is also connected with the input/output terminal 20220 of DSP unit 2022, further, the power input 20221 of DSP unit 2022 connects the outfan 2011 of power module 201.
Further, the outfan 20310 of primary importance feedback interface unit 2031 connects one group of input/output terminal 20211 (I/O of FPGA unit 2021, InputorOutput), the outfan 20320 of second position feedback interface unit 2032 also connects one group of input/output terminal 20211 of FPGA unit 2021.
Wherein, primary importance feedback interface unit 2031 includes that sinusoidal wave incremental encoder interface circuit, sinusoidal wave incremental encoder interface circuit include the first operational amplifier the 400, second operational amplifier 401 and ADC (Analog-to-DigitalConverter) analog-digital converter 402.
The outfan of the first operational amplifier 400 and the second operational amplifier 401 connects the input of ADC analog-digital converter 402 respectively, and the outfan of ADC analog-digital converter 402 connects one group of input/output terminal 20211 of FPGA unit 2021.
Wherein, the SIN differential signal of outside sinusoidal wave incremental encoder is become SIN single-ended signal and is sent to ADC analog-digital converter 402 and carries out processing and obtain corresponding SIN signal after being changed by the first operational amplifier 400, the COS differential signal of outside sinusoidal wave incremental encoder is become COS single-ended signal and is sent to ADC analog-digital converter 402 and carries out processing and obtain corresponding COS signal after being changed by the second operational amplifier 401, further, SIN signal and COS signal are finally transmitted to FPGA unit 2021 and carry out respective handling.
Further, primary importance feedback interface unit 2031 also includes TTL incremental encoder interface circuit.
First operational amplifier 400 and the second operational amplifier 401 of TTL incremental encoder interface circuit multiplexing sine wave incremental encoder interface circuit, and farther include the first comparator the 403, second comparator 404 and the 3rd comparator 405.
The outfan of first comparator the 403, second comparator 404 and the 3rd comparator 405 connects one group of input/output terminal 20211 of FPGA unit 2021 respectively, and, one input of the first comparator 403 connects the outfan of the first operational amplifier 400, another input connects reference voltage, and an input of the second comparator 404 connects the outfan of the second operational amplifier 401, another input connects reference voltage.
The A phase differential signal of outside TTL incremental encoder becomes A phase single-ended signal after the first operational amplifier 400 conversion, under the effect of the first comparator 403, A phase single-ended signal obtains A phase signals after comparing with reference voltage, the B phase differential signal of outside TTL incremental encoder becomes B phase single-ended signal after the second operational amplifier 401 conversion, under the effect of the second comparator 404, B phase single-ended signal obtains B phase signals after comparing with reference voltage, the Z phase differential signal of outside TTL incremental encoder directly obtains Z phase signals after the 3rd comparator 405 conversion, and, A phase signals, B phase signals and Z phase signals are finally transmitted to FPGA unit 2021 and carry out respective handling.
In conjunction with Fig. 4, the working method of primary importance feedback interface unit 2031 in servo drive the second embodiment of the present invention is carried out brief schematic illustration.
(1), when the external encoder connected when primary importance feedback interface unit 2031 is sinusoidal wave incremental encoder (or cosine wave encoder), sinusoidal wave incremental encoder connects sinusoidal wave incremental encoder interface circuit.
nullWherein，The coded data of sinusoidal wave incremental encoder includes SIN signal and COS signal，SIN signal is sent to the first operational amplifier 400 with the form of differential signal SIN+ and SIN-，After the processing and amplifying of the first operational amplifier 400，It is converted into the single-ended signal SIN+ after amplifying，Simultaneously，COS signal is also sent to the second operational amplifier 401 with the form of differential signal COS+ and COS-，After the processing and amplifying of the second operational amplifier 401，It is converted into the single-ended signal COS+ after amplifying，Subsequently，ADC analog-digital converter 402 obtains SIN+ and COS+ signal after single-ended signal SIN+ and COS+ is carried out relevant treatment，SIN+ and COS+ signal is transferred to FPGA unit 2021 and counts by ADC analog-digital converter 402、Sampling and segmentation，And the result after processing passes to the DSP unit 2022 of processing module 202 and is analyzed being calculated the result of needs.
When or servomotor itself higher to Serve Motor Control required precision runs slower, this sine wave incremental encoder interface circuit is used to connect sinusoidal wave incremental encoder, by ADC analog-digital converter 402, the amplitude of the sinusoidal wave incremental encoder collected can be converted into concrete data, because this amplitude degree of accuracy is higher, and then can improve the control accuracy to servomotor.
(2), when the external encoder connected when primary importance feedback interface unit 2031 is TTL incremental encoder, TTL incremental encoder connects TTL incremental encoder interface circuit.
nullWherein，The coded data of TTL incremental encoder includes A phase、B phase and Z phase signals，A phase signals is sent to the first operational amplifier 400 with the form of differential signal A+ and A-，After the processing and amplifying of the first operational amplifier 400，It is converted into the single-ended signal A+ after amplifying，Simultaneously，B phase signals is also sent to the second operational amplifier 401 with the form of differential signal B+ and B-，After the processing and amplifying of the second operational amplifier 401，It is converted into the single-ended signal B+ after amplifying，Z phase signals is transferred directly to the 3rd comparator 405 with the form of differential signal Z+ and Z-，After the process of the 3rd comparator 405，It is converted directly into single-ended signal Z+，Subsequently，A+、B+ and Z+ signal is all passed to FPGA unit 2021 and counts、Sampling，And the result after processing passes to the DSP unit 2022 of processing module 202 and is analyzed being calculated the result of needs.
Embodiment of the present invention, sinusoidal wave incremental encoder interface circuit and the TTL incremental encoder interface circuit of primary importance feedback interface unit 2031 can realize interface duplex, it is possible to integration system resource, make circuit structure simpler, advantageously reduce cost.
With continued reference to Fig. 4, second position feedback interface unit 2032 includes absolute value encoder interface circuit.
Wherein, absolute value encoder interface circuit includes RS485 transceiver 500 and RS485 transmitter 501, wherein, RS485 transceiver 500 can receive and can send data, further, RS485 transceiver 500 includes receiving unit 5001 and transmitting element 5002, the outfan receiving unit 5001 connects one group of input/output terminal 20211 of FPGA unit 2021, and the input of transmitting element 5002 connects one group of input/output terminal 20211 of FPGA unit 2021, the input of RS485 transmitter 501 connects one group of input/output terminal 20211 of FPGA unit 2021.
The DATA differential signal of outside absolute value encoder is converted into DATA single-ended signal through RS485 transceiver 500, DATA single-ended signal is transferred to FPGA unit 2021 and carries out respective handling, further, CLOCK single-ended signal is converted into CLOCK differential signal through RS485 transmitter 501 and DATA single-ended signal is transferred to after RS485 transceiver 500 is converted into DATA differential signal outside absolute value encoder carries out respective handling by FPGA unit 2021.
nullSpecifically，The coded data of absolute value encoder includes CLOCK signal and DATA signal，Wherein，Single-ended signal CLOCK+ is sent to RS485 transmitter 501 by FPGA unit 2021，Differential signal CLOCK+ and CLOCK-is obtained after RS485 transmitter 501 processes，This CLOCK+ and CLOCK-is obtained subsequently by absolute value encoder，After absolute value encoder gets CLOCK+ and CLOCK-，DATA signal is sent to RS485 transceiver 500 with the form of differential signal DATA+ and DATA-by absolute value encoder at synchronization，The synchronous transfer of data can be realized，Thereafter，DATA+ and DATA-is converted into single-ended signal DATA+ and is sent to FPGA unit 2021 after RS485 transceiver 500 processes.Wherein, because absolute value encoder can preserve coded data, at least can preserve DATA signal, FPGA can realize the check and correction of synchrodata at system cut-off or again read off DATA value that encoder preserves after restarting and proofread with the DATA value before power-off.
By FPGA unit 2021, single-ended signal DATA+ is sent to RS485 transceiver 500, DATA+ is converted into differential signal DATA+ and DATA-by this RS485 transceiver 500, this DATA+ and DATA-is received by absolute value encoder, absolute value encoder is receiving corresponding control or after configuration order, the register value (including the detected value of temperature sensor, CRC check value etc.) of himself can be passed to FPGA unit 2021..
With continued reference to Fig. 4, wherein, the external encoder that power interface unit 2033 is selectively primary importance feedback interface unit 2031 according to configuration parameter or second position feedback interface unit 2032 is connected provides the first running voltage V1 or the second running voltage V2.For example, this configuration parameter is the normal working voltage scope of external encoder or value that some is concrete, and external encoder is manually connected to power interface unit 2033 according to this configuration parameter to be provided on the pin of the first running voltage V1 or be connected to provide on the pin of the second running voltage V2.
Specifically, power interface unit is the DC/DC (DirectCurrenttoDirectCurrent of two-way output, DC converting becomes direct current) electric pressure converter 2033, DC/DC electric pressure converter 2033 includes input, the first outfan, the second outfan and controls end.
Wherein, the input of DC/DC electric pressure converter 2033 connects the outfan of power module 201, and the first outfan of DC/DC electric pressure converter 2033 exports the first running voltage V1, and the second outfan of DC/DC electric pressure converter 2033 exports the second running voltage V2.
nullThe feedback voltage level V_SENSE controlling end detection external encoder feedback of DC/DC electric pressure converter 2033，Wherein，Real work magnitude of voltage proportion relation current with external encoder for this feedback voltage level V_SENSE，I.e. this feedback voltage level V_SENSE can reflect its actual operational voltage value，Subsequently，Internal for feedback voltage level V_SENSE and the DC/DC electric pressure converter 2033 corresponding reference voltage level arranged is compared，Wherein，Corresponding first reference voltage level of first running voltage V1、Corresponding second reference voltage level of second running voltage V2，When feedback voltage level V_SENSE differs with corresponding reference voltage level，I.e.，When external encoder uses the first running voltage V1，Feedback voltage level V_SENSE and the first reference voltage level are compared，And external encoder is when using the second running voltage V2，Feedback voltage level V_SENSE and the second reference voltage level are compared.Then, carry out PWM pulsewidth modulation, i.e. make feedback voltage level identical with reference voltage level or essentially identical by PWM pulsewidth modulation, so make external encoder stable be in the first running voltage V1 or the second running voltage V2.And then ensure that the reliability of external encoder.
Wherein, the first running voltage V1 is 5V, and the second running voltage V2 is 10V.For the first running voltage V1 and the selection of the second running voltage V2 value, it is the operating voltage range of conventional encoder referring especially to standard, as the most common, the running voltage of different vendor and different agreement encoder is different, but predominantly 5V, 7-12V and 10-30V, and the first running voltage V1 value is 5V by embodiment of the present invention, it is 10V by the second running voltage V2 value, the most compatible above-mentioned running voltage mentioned, it is possible to meet most occasion demand to running voltage.Certainly, for the first running voltage V1 and the value of the second running voltage V2, with specific customization, or can be arranged voluntarily by user, be actually needed to meet.
Above-mentioned embodiment, compatible absolute value encoder, sinusoidal wave incremental encoder and TTL incremental encoder.
It is the structural representation of servo drive the 3rd embodiment of the present invention refering to Fig. 5, Fig. 5.With differing only in of second embodiment of the invention, in embodiment of the present invention, processing module 302 includes host computer interface unit 3023.Wherein, the input/output terminal 30230 of host computer interface unit 3023 connects the input/output terminal 30221 of DSP unit 3022.
Host computer connects the input/output terminal 30231 of host computer interface unit 3023, and host computer is by controlling DSP unit 3022 and then controlling servo drive.Wherein, host computer is PC (PersonalComputer, PC) or other control terminal.
Further, host computer interface unit 3023 is USB interface or Ethernet interface or RS232 serial ports.Multifarious interface can be provided to select so that the host computer of different interface type can be general.
Servo drive supports the encoder of EnDat, Biss, Hiperface, SSI, TTL and Sin/Cos communications protocol.What deserves to be explained is, because embodiment of the present invention is designed under meeting EnDat communications protocol, and EnDat agreement is a kind of communications protocol most stringent, that be most widely used, it is therefore, compatible that remaining is several such as the encoder of Biss, Hiperface, SSI, TTL and Sin/Cos communications protocol.
The present invention also provides for a kind of servo-control system.
This servo-control system includes the servo drive as described by above-mentioned any embodiment.
Specifically, this servo-control system also includes servomotor, photoelectric rotary coder and host computer.
Wherein, servo drive connects servomotor, photoelectric rotary coder and host computer respectively.
Photoelectric rotary coder is arranged on servomotor, for measuring the relevant parameter of servo motor rotor, and relevant parameter is transferred to servo drive；Relevant parameter is processed and passes to host computer by servo drive；Host computer realizes the control to servomotor according to the relevant parameter obtained after processing.
nullThe servo-control system of embodiment of the present invention，Because using the servo drive described by any of the above-described embodiment，By the addressable port of servo drive is improved，Primary importance feedback interface unit is set、Second position feedback interface unit and power interface unit，Wherein，Primary importance feedback interface unit and second position feedback interface unit provide the addressable port of at least two type for external encoder，And，Can be according to primary importance feedback interface unit、The type of the external encoder that second position feedback interface unit is connected，By power interface Unit selection for primary importance feedback interface unit、The external encoder that second position feedback interface unit is connected provides running voltage，Can be compatible dissimilar、The photoelectric rotary coder of different operating voltage，And then the encoder type selecting scope of support can be expanded、Increase encoder type selecting motility、Reduce buying expenses and the shortcoming overcoming single running voltage to cause.
These are only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every equivalent structure utilizing description of the invention and accompanying drawing content to be made or equivalence flow process conversion; or directly or indirectly it is used in other relevant technical fields, the most in like manner it is included in the scope of patent protection of the present invention.
Claims (10)
1. a servo drive, it is characterised in that including:
Power module, processing module and addressable port module, the outfan of described power module connects described processing module and the power input of described addressable port module respectively, and then provides power supply for described processing module and described addressable port module；
Described addressable port module at least includes primary importance feedback interface unit, second position feedback interface unit and power interface unit；
The outfan of described primary importance feedback interface unit connects described processing module, passes to described processing module after being used for obtaining the coded data of incremental encoder and described coded data being carried out respective handling；
The outfan of described second position feedback interface unit connects described processing module, passes to described processing module after being used for obtaining the coded data of absolute value encoder and described coded data being carried out respective handling；
The input of described power interface unit connects the outfan of described power module, and the external encoder connected by described primary importance feedback interface unit or described second position feedback interface unit according to the type selecting of configuration parameter, i.e. external encoder ground provides running voltage；
Wherein said processing module includes FPGA unit, and the power input of described FPGA unit connects the outfan of described power module；The outfan of described primary importance feedback interface unit and described second position feedback interface unit connects the input/output terminal of described FPGA unit respectively；
Described primary importance feedback interface unit includes that sinusoidal wave incremental encoder interface circuit, described sinusoidal wave incremental encoder interface circuit include the first operational amplifier, the second operational amplifier and ADC analog-digital converter；The outfan of described first operational amplifier and described second operational amplifier connects the input of described ADC analog-digital converter respectively, and the outfan of described ADC analog-digital converter connects the input/output terminal of described FPGA unit；
Described primary importance feedback interface unit also includes TTL incremental encoder interface circuit；Described first operational amplifier of sinusoidal wave incremental encoder interface circuit described in described TTL incremental encoder interface circuit multiplexing and described second operational amplifier, and farther include the first comparator, the second comparator and the 3rd comparator；The outfan of described first comparator, described second comparator and described 3rd comparator connects the input/output terminal of described FPGA unit respectively, and, one input of described first comparator connects the outfan of the first operational amplifier, another input connects reference voltage, and an input of described second comparator connects the outfan of the second operational amplifier, another input connects reference voltage.
Servo drive the most according to claim 1, it is characterised in that
The SIN differential signal of outside sinusoidal wave incremental encoder is become SIN single-ended signal and is sent to described ADC analog-digital converter and carries out processing and obtain corresponding SIN signal after being changed by described first operational amplifier, the COS differential signal of outside sinusoidal wave incremental encoder is become COS single-ended signal and is sent to described ADC analog-digital converter and carries out processing and obtain corresponding COS signal after being changed by described second operational amplifier, further, described SIN signal and described COS signal are finally transmitted to described FPGA unit and carry out respective handling.
Servo drive the most according to claim 2, it is characterised in that
The A phase differential signal of outside TTL incremental encoder becomes A phase single-ended signal after the first operational amplifier conversion, under the effect of described first comparator, described A phase single-ended signal obtains A phase signals after comparing with reference voltage, the B phase differential signal of outside TTL incremental encoder becomes B phase single-ended signal after the second operational amplifier conversion, under the effect of described second comparator, described B phase single-ended signal obtains B phase signals after comparing with reference voltage, the Z phase differential signal of outside TTL incremental encoder directly obtains Z phase signals after described 3rd comparator conversion, and, described A phase signals, B phase signals and Z phase signals are finally transmitted to described FPGA unit and carry out respective handling.
Servo drive the most according to claim 3, it is characterised in that
Described second position feedback interface unit includes absolute value encoder interface circuit；
Described absolute value encoder interface circuit includes RS485 transceiver and RS485 transmitter, and wherein, one end of described RS485 transceiver connects the input/output terminal of described FPGA unit, and the input of described RS485 transmitter connects the input/output terminal of described FPGA unit；
The DATA differential signal of outside absolute value encoder is converted into DATA single-ended signal through described RS485 transceiver, described DATA single-ended signal is transferred to described FPGA unit and carries out respective handling, further, CLOCK single-ended signal is converted into CLOCK differential signal through RS485 transmitter and DATA single-ended signal is transferred to after described RS485 transceiver is converted into DATA differential signal outside absolute value encoder carries out respective handling by described FPGA unit.
Servo drive the most according to claim 4, it is characterised in that
There is provided the first running voltage or the second running voltage for external encoder to the external encoder type selecting that described power interface unit is connected according to described primary importance feedback interface unit or described second position feedback interface unit.
Servo drive the most according to claim 5, it is characterised in that
Described power interface unit is the DC/DC electric pressure converter of two-way output, and described DC/DC electric pressure converter includes input, the first outfan, the second outfan and controls end；
Wherein, the input of described DC/DC electric pressure converter connects the outfan of described power module, and the first outfan of described DC/DC electric pressure converter exports the first running voltage, and the second outfan of described DC/DC electric pressure converter exports the second running voltage；
The feedback voltage level controlling end detection external encoder feedback of described DC/DC electric pressure converter, and internal to described feedback voltage level and the described DC/DC electric pressure converter reference voltage level arranged is compared, when described feedback voltage level differs with described reference voltage level, carry out PWM pulsewidth modulation, so make external encoder stable be in the first running voltage or the second running voltage.
Servo drive the most according to claim 6, it is characterised in that
Described first running voltage is 5V, and described second running voltage is 10V.
Servo drive the most according to claim 1, it is characterised in that
Described processing module includes DSP unit and host computer interface unit；The input/output terminal of described DSP unit connects the input/output terminal of described FPGA unit, and the input/output terminal of described host computer interface unit connects the input/output terminal of described DSP unit；
Wherein, described host computer interface unit is USB interface or Ethernet interface or RS232 serial ports.
9. a servo-control system, it is characterised in that described servo-control system includes the servo drive as described in any one of claim 1-8.
Servo-control system the most according to claim 9, it is characterised in that
Described servo-control system also includes servomotor, photoelectric rotary coder and host computer, and wherein, described servo drive connects described servomotor, described photoelectric rotary coder and host computer respectively；
Described photoelectric rotary coder is arranged on described servomotor, for measuring the relevant parameter of described servo motor rotor, and described relevant parameter is transferred to described servo drive；Described relevant parameter is processed and passes to described host computer by described servo drive；Described host computer realizes the control to described servomotor according to the relevant parameter obtained after described process.
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