CN103175495A - Standard silicon dioxide wafer and production method thereof - Google Patents
Standard silicon dioxide wafer and production method thereof Download PDFInfo
- Publication number
- CN103175495A CN103175495A CN2013100624763A CN201310062476A CN103175495A CN 103175495 A CN103175495 A CN 103175495A CN 2013100624763 A CN2013100624763 A CN 2013100624763A CN 201310062476 A CN201310062476 A CN 201310062476A CN 103175495 A CN103175495 A CN 103175495A
- Authority
- CN
- China
- Prior art keywords
- silicon dioxide
- wafer
- thickness
- layer
- passivation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a standard silicon dioxide wafer and a production method thereof. The standard silicon dioxide wafer comprises a wafer, a silicon dioxide layer formed on the wafer and in standard thickness, and a passivation layer formed on the silicon dioxide layer. The silicon dioxide layer can be separated from the external environment by the passivation layer, the thickness of the silicon dioxide layer is kept unchanged, and accordingly the interference of the standard silicon dioxide wafer upon measurement precision of a measuring machine is avoided.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of silicon dioxide standard wafer and manufacture method thereof.
Background technology
Along with the development of semiconductor technology, process constantly descends.Accordingly, the silicon dioxide thickness as dielectric layer is also constantly reducing in integrated circuit.Along with the decline of silicon dioxide thickness, in order to keep the stability of silicon dioxide thickness, accuracy and stability that the standard wafer of silicon dioxide is measured are had higher requirement.
Usually, the silicon dioxide standard wafer is to form the silicon dioxide of standard thickness on substrate.Before the film thickness of the silicon dioxide of measuring the board measurement products, first measure the thickness of the silicon dioxide of described silicon dioxide standard wafer, if measurement result within the limits prescribed, the accuracy of judgement measurement board meets the requirements, and can continue the silica membrane of product is carried out thickness measure; If measurement result exceeds the scope of regulation, the accuracy of judgement measurement board is undesirable, need correcting measuring board again, until measure the scope that the measurement result of board falls into regulation, could continue the silica membrane of product is carried out thickness measure.If variation has occured in the thickness of the silicon dioxide of silicon dioxide standard wafer, be stable even measure board like this, certain deviation can occur with standard thickness in the thickness of the silicon dioxide that it is measured.That is to say, adopt the silicon dioxide standard wafer to determine that the accuracy of measurement board and the prerequisite of stability are that the thickness of the silicon dioxide of silicon dioxide standard wafer is fixed.
As shown in Figure 1, silicon dioxide standard wafer 100 comprises the silica 1 02 of the standard thickness on wafer 101 and formation and described wafer 101.Usually, silicon dioxide standard wafer 100 is positioned in air for a long time, and steam and other pollutants in air can be adsorbed in the surface of silica 1 02, also can form one deck natural oxidizing layer on its surface because of the oxidation reaction of nature in addition.Therefore, the result that the measurement board is measured silica 1 02 thickness of the silicon dioxide standard wafer 100 after above-mentioned long-term placement can exceed specialized range, and the result of its detect thickness can be larger than standard thickness usually.But, for the operator, can't judge that whether above-mentioned deviation is to cause owing to measuring the unstable of board, therefore can cause a lot of puzzlements to the operator.
Therefore, be necessary to develop a kind of silicon dioxide standard wafer, the thickness of its silicon dioxide is remained unchanged.
Summary of the invention
The object of the present invention is to provide a kind of silicon dioxide standard wafer and manufacture method thereof, continue the phenomenon that changes with the thickness of the silicon dioxide that solves existing silicon dioxide standard wafer, thereby cause measuring the unsettled problem of board measurement result.
For solving the problems of the technologies described above, the invention provides a kind of silicon dioxide standard wafer, comprising: wafer, be formed at the silicon dioxide layer of the standard thickness on described wafer and be formed at passivation layer on described silicon dioxide layer.
Optionally, on described silicon dioxide standard wafer, passivation layer is polysilicon or silicon nitride.
Optionally, on described silicon dioxide standard wafer, the thickness of described passivation layer more than or equal to
Optionally, on described silicon dioxide standard wafer, the thickness of described passivation layer is
Optionally, on described silicon dioxide standard wafer, the thickness of silicon dioxide layer less than
Accordingly, the present invention also provides a kind of manufacture method of silicon dioxide standard wafer, comprising:
Step 1 a: wafer is provided;
Step 2: the silicon dioxide layer that forms standard thickness on described wafer;
Step 3: form passivation layer on described silicon dioxide layer.
Optionally, in the manufacture method of described silicon dioxide standard wafer, in described step 3, adopt the LPCVD method on described silicon dioxide layer deposit spathic silicon as described passivation layer.
Optionally, in the manufacture method of described silicon dioxide standard wafer, described step 3 comprises:
Adopt LPCVD method deposit spathic silicon on described silicon dioxide layer; And
Described polysilicon is carried out annealing in process, to form described passivation layer.
Optionally, in the manufacture method of described silicon dioxide standard wafer, the temperature of described annealing in process is 700 ℃～800 ℃, and the time is 30 minutes～45 minutes.
Optionally, in the manufacture method of described silicon dioxide standard wafer, in described step 3, adopt the LPCVD method on described silicon dioxide layer deposited silicon nitride as described passivation layer.
Optionally, in the manufacture method of described silicon dioxide standard wafer, the thickness of described passivation layer more than or equal to
Optionally, in the manufacture method of described silicon dioxide standard wafer, the thickness of described passivation layer
Optionally, in the manufacture method of described silicon dioxide standard wafer, the thickness of silicon dioxide layer less than
On silicon dioxide standard wafer provided by the invention, also comprise passivation layer on described silicon dioxide layer.Passivation layer can be kept apart described silicon dioxide layer and external environment; because being arranged, the protection silicon dioxide layer surface of passivation layer can not adsorb steam or other airborne pollutants; also can not exist simultaneously the surface by the problem of autoxidation, thereby the silicon dioxide layer thickness that makes keep immobilizing.Therefore, measure board when measuring above-mentioned silicon dioxide standard wafer, because the silicon dioxide layer thickness is to keep changeless, therefore when measurement result exceeds specialized range, the accuracy that can judge described measurement board goes wrong, and needs the measuring system of correcting measuring board again.
Description of drawings
Fig. 1 is the structural representation of existing silicon dioxide standard wafer;
Fig. 2 is the structural representation of the silicon dioxide standard wafer of one embodiment of the invention;
Fig. 3-Fig. 4 is the structural representation of device in each step in the manufacture method of silicon dioxide standard wafer of one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, silicon dioxide standard wafer and the manufacture method thereof that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the present invention lucidly.
As shown in Figure 2, the silicon dioxide standard wafer 200 of one embodiment of the invention comprises: wafer 201, be formed at the silicon dioxide layer 202 of the standard thickness on described wafer 201 and be formed at passivation layer 203 on described silicon dioxide layer 202.Wherein, described passivation layer 203 is polysilicon or silicon nitride.
In order to guarantee the protective effect of 203 pairs of silicon dioxide layers 202 of passivation layer, thickness that can described passivation layer 203 be set to more than or equal to
Preferably, the thickness of described passivation layer 203 is
Describe the manufacture method of silicon dioxide standard wafer in detail below in conjunction with Fig. 2 to Fig. 4.
Step 1: as shown in Figure 3, provide a wafer 201, the thickness of described wafer 201 is about 775 μ m;
Step 2: as shown in Figure 4, form the silicon dioxide layer 202 of standard thickness on described wafer 201;
Along with improving constantly of semiconductor integrated level, process constantly descends, and therefore the silicon dioxide thickness as dielectric layer is also constantly reducing.Accordingly, the thickness of the silicon dioxide layer 202 of silicon dioxide standard wafer 200 is corresponding reducing also, and is preferred, the thickness of silicon dioxide layer less than
Step 3: as shown in Figure 2, form passivation layer 203 on described silicon dioxide layer 202.
Specifically, the wafer 201 after step 2 is placed on Low Pressure Chemical Vapor Deposition(LPCVD, low-pressure chemical vapor phase deposition) in boiler tube, furnace tube temperature is risen to 500 ℃～700 ℃, preferably 620 ℃.Under low voltage control, pass into the reacting gas SiH4 of certain flow ratio, the certain thickness polysilicon of reactive deposition is as described passivation layer 203.In order to improve the protection effect of 203 pairs of silicon dioxide layers 202 of passivation layer, usually, the thickness requirement of passivation layer 203 is greater than 500 thickness
Preferably, the thickness of described passivation layer 203 is
So far, formed silicon dioxide standard wafer 200 as shown in Figure 2.
In the present embodiment, the employing polysilicon of described passivation layer 203.Should be understood that, all can be used as passivation layer to the material that silicon dioxide layer 202 can play isolated protective effect, for example can also form one deck silicon nitride as passivation layer 203 on described silicon dioxide layer 202 by LPCVD technique.
In order further to improve the protection effect of 203 pairs of silicon dioxide layers 202 of passivation layer; in another embodiment of the present invention; the wafer that has deposited polysilicon is put into the normal pressure boiler tube carry out the high temperature anneal; furnace tube temperature rises between 700 ℃～800 ℃; pass into the N2 of certain flow, the processing time is 30 minutes～45 minutes.As described passivation layer 203, the compactness of the polysilicon after annealing in process is improved with the polysilicon of annealed processing, so it is to the protection effect of silicon dioxide layer 202 also corresponding being improved.
In sum, also comprise passivation layer on described silicon dioxide layer.Described passivation layer can be kept apart described silicon dioxide layer and external environment; because being arranged, the protection silicon dioxide layer surface of passivation layer can not adsorb steam or other airborne pollutants; also can not exist simultaneously the surface by the problem of autoxidation, thereby the silicon dioxide layer thickness that makes keep immobilizing.Therefore, measure board when measuring above-mentioned silicon dioxide standard wafer, because the silicon dioxide layer thickness is to keep changeless, therefore when measurement result exceeds specialized range, the accuracy that can judge described measurement board goes wrong, and needs the measuring system of correcting measuring board again.
Foregoing description is only the description to preferred embodiment of the present invention, is not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure all belong to the protection domain of claims.
Claims (13)
1. silicon dioxide standard wafer comprises: wafer and be formed at the silicon dioxide layer of the standard thickness on described wafer, it is characterized in that, and also comprise the passivation layer that is formed on described silicon dioxide layer.
2. silicon dioxide standard wafer as claimed in claim 1, is characterized in that, passivation layer is polysilicon or silicon nitride.
3. silicon dioxide standard wafer as claimed in claim 1, is characterized in that, the thickness of described passivation layer more than or equal to
4. silicon dioxide standard wafer as claimed in claim 3, is characterized in that, the thickness of described passivation layer is
5. silicon dioxide standard wafer as claimed in claim 1, is characterized in that, the thickness of silicon dioxide layer less than
6. the manufacture method of a silicon dioxide standard wafer comprises:
Step 1 a: wafer is provided;
Step 2: the silicon dioxide layer that forms standard thickness on described wafer;
Step 3: form passivation layer on described silicon dioxide layer.
7. the manufacture method of silicon dioxide standard wafer as claimed in claim 6, is characterized in that, in described step 3, adopt the LPCVD method on described silicon dioxide layer deposit spathic silicon as described passivation layer.
8. the manufacture method of silicon dioxide standard wafer as claimed in claim 6, is characterized in that, described step 3 comprises:
Adopt LPCVD method deposit spathic silicon on described silicon dioxide layer; And
Described polysilicon is carried out annealing in process, to form described passivation layer.
9. the manufacture method of silicon dioxide standard wafer as claimed in claim 8, is characterized in that, the temperature of described annealing in process is 700 ℃～800 ℃, and the time is 30 minutes～45 minutes.
10. the manufacture method of silicon dioxide standard wafer as claimed in claim 6, is characterized in that, in described step 3, adopt the LPCVD method on described silicon dioxide layer deposited silicon nitride as described passivation layer.
11. the manufacture method of silicon dioxide standard wafer as claimed in claim 6 is characterized in that, the thickness of described passivation layer more than or equal to
12. the manufacture method of silicon dioxide standard wafer as claimed in claim 11 is characterized in that, the thickness of described passivation layer
13. the manufacture method of silicon dioxide standard wafer as claimed in claim 6 is characterized in that, the thickness of silicon dioxide layer less than
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310062476.3A CN103175495B (en) | 2013-02-27 | 2013-02-27 | Standard silicon dioxide wafer and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310062476.3A CN103175495B (en) | 2013-02-27 | 2013-02-27 | Standard silicon dioxide wafer and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103175495A true CN103175495A (en) | 2013-06-26 |
| CN103175495B CN103175495B (en) | 2015-11-25 |
Family
ID=48635528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310062476.3A Active CN103175495B (en) | 2013-02-27 | 2013-02-27 | Standard silicon dioxide wafer and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103175495B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100999388A (en) * | 2006-12-30 | 2007-07-18 | 南开大学 | Preparation method of polycrystalline silicon film of decorated and coated solution on surface with induction crystallization |
| CN101005098A (en) * | 2006-01-21 | 2007-07-25 | 井叶之 | Nano poly crystal silicon-aluminum nitride diaphragm silicon single crystal substrate base for high temperature mechanics magnitude sensor |
| CN101330018A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for depositing benzocyclobutene layer and method for preparing convex point |
| CN101872768A (en) * | 2010-06-11 | 2010-10-27 | 清华大学 | Ferroelectric dynamic random storage based on bismuth based storage materials and preparation method thereof |
| CN101872728A (en) * | 2009-04-24 | 2010-10-27 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of solder pad layer |
| CN102086019A (en) * | 2010-11-02 | 2011-06-08 | 中国电子科技集团公司第二十四研究所 | Method for manufacturing monolithic polysilicon cantilever structure |
| CN102420194A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Passivation layer of integrated circuit and manufacturing method of passivation layer |
| CN102543661A (en) * | 2010-12-27 | 2012-07-04 | 无锡华润上华科技有限公司 | Wafer manufacturing method |
| EP2524897A2 (en) * | 2011-05-19 | 2012-11-21 | General Electric Company | Method and device for preventing corrosion on sensors |
-
2013
- 2013-02-27 CN CN201310062476.3A patent/CN103175495B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101005098A (en) * | 2006-01-21 | 2007-07-25 | 井叶之 | Nano poly crystal silicon-aluminum nitride diaphragm silicon single crystal substrate base for high temperature mechanics magnitude sensor |
| CN100999388A (en) * | 2006-12-30 | 2007-07-18 | 南开大学 | Preparation method of polycrystalline silicon film of decorated and coated solution on surface with induction crystallization |
| CN101330018A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for depositing benzocyclobutene layer and method for preparing convex point |
| CN101872728A (en) * | 2009-04-24 | 2010-10-27 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of solder pad layer |
| CN101872768A (en) * | 2010-06-11 | 2010-10-27 | 清华大学 | Ferroelectric dynamic random storage based on bismuth based storage materials and preparation method thereof |
| CN102086019A (en) * | 2010-11-02 | 2011-06-08 | 中国电子科技集团公司第二十四研究所 | Method for manufacturing monolithic polysilicon cantilever structure |
| CN102543661A (en) * | 2010-12-27 | 2012-07-04 | 无锡华润上华科技有限公司 | Wafer manufacturing method |
| CN102420194A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Passivation layer of integrated circuit and manufacturing method of passivation layer |
| EP2524897A2 (en) * | 2011-05-19 | 2012-11-21 | General Electric Company | Method and device for preventing corrosion on sensors |
Non-Patent Citations (1)
| Title |
|---|
| 《电气电子绝缘技术手册》编辑委员会: "《电气电子绝缘技术手册》", 31 January 2008 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103175495B (en) | 2015-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102104728B1 (en) | Substrate processing device, manufacturing method of semiconductor device and recording medium | |
| JP5788355B2 (en) | Heat treatment system, heat treatment method, and program | |
| US20140209022A1 (en) | Raw material gas supply device, film forming apparatus, raw material gas supply method, and non-transitory storage medium | |
| US20140017901A1 (en) | Vapour etch of silicon dioxide with improved selectivity | |
| KR101998921B1 (en) | Heat treatment system, heat treatment method, and program | |
| CN102534548A (en) | Aminovinylsilane for CVD and ALD SIO2 films | |
| CN105448666A (en) | Method for changing curvature of silicon wafer substrate by stress of silicon dioxide | |
| CN101646804A (en) | Cvd film-forming apparatus | |
| CN101442004B (en) | Method for forming doped region wall by deposition carbonaceous film | |
| JP6596316B2 (en) | Heat treatment system, heat treatment method, and program | |
| CN105206549A (en) | Method used for improving stability of TEOS thin film on furnace tube machine | |
| CN103175495A (en) | Standard silicon dioxide wafer and production method thereof | |
| CN105526983A (en) | Structure of gas flow sensor and manufacturing method thereof | |
| CN103119197A (en) | Amorphous silicon nitride film and method for producing same | |
| CN101154557A (en) | Method for clearing pollutant on standard wafer surface and emendation method for depth-measuring device | |
| CN105529281A (en) | Semiconductor equipment leakage detection method | |
| US10811325B2 (en) | Self-healing semiconductor wafer processing | |
| TW392265B (en) | Method for fabricating reference sample for correcting setting value of measuring instrument which measures impurity concentration of BPSG film of semiconductor device, and its reference sample | |
| CN103305808A (en) | Production device for silicon oxide film and production method thereof | |
| JP6378639B2 (en) | Processing system, processing method, and program | |
| CN203333758U (en) | Production equipment of silicon dioxide film | |
| CN108431571A (en) | Pressure sensor | |
| CN108538738A (en) | Structure and method for detecting nitrogen concentration | |
| CN109119351B (en) | Stress detection method and stress detection system for dielectric film layer | |
| JP5334908B2 (en) | HMDS processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |