CN103166438B - Modulator based on field programmable gate array (FPGA) - Google Patents

Abstract

The invention relates to an FPGA (mixed random space voltage vector pulse width modulation method) and a modulator based on a field programmable gate array. According to the method, action time and pulse and pulse positioning of a basic voltage sector are controlled by two random variables, one of the two random variables is used for controlling the action time of the basic voltage vector by controlling distribution proportion of action time of two zero vectors, and the other random variable is used for performing pulse positioning by controlling the position of the widest high-level pulse. The modulator comprises a period register, a dead zone register, two groups of hop time registers, a counting and initial value reloading circuit, a register switching circuit and a pulse generation circuit, and an asymmetrical control pulse is generated through alternative comparison of the two groups of hop time registers. By the modulation method and the modulator, mechanical vibration, audio-frequency noise, electromagnetic radiation and the like due to a large peak value of a discrete set cluster spectrum are obviously avoided on the premise that fundamental wave voltage and switching frequency do not change.

Description

Based on the modulator of FPGA

Technical field

The invention belongs to alternating frequency conversion technique field, be specifically related to a kind of mixing stochastic space voltage vector pulse duration modulation method and modulator based on FPGA that can reduce harmonic wave peak value.

Background technology

That inverter as shown in Figure 1 has is simple in structure, realize the advantages such as convenient, is widely used in the occasion of the frequency controls such as electric automobile driving.The pulse-width modulation (PWM) adopting is the principle based on " volt-second balance ", with duty ratio constantly the potential pulse of conversion carry out equivalent command voltage according to time average.The essence of modulation strategy is to calculate according to command voltage the 6 path switching signal low and high level jumping moments that inverter needs with certain algorithm, produces 6 road pulse signals with logical circuit, then removes to open or close power switch pipe by drive circuit.Sine pulse width modulation (PWM) (SPWM) is a kind of very ripe, very classical three-phase PWM, the half that the fundamental voltage amplitude that can export is DC bus-bar voltage.The essence of space voltage vector PWM (SVPWM) is on the modulating wave of SPWM, to have injected three times of subharmonic, thereby has improved the utilance of direct voltage, has improved approximately 15.4% compared with SPWM.Its motor and inverter are regarded entirety as, to obtain loop circle flux as target, have that busbar voltage utilance is high, harmonic characterisitic good, facilitate the advantages such as numerical control system realization, occupy dominant position at present in conversion speed governing digital control system.

The conventional pulse duration modulation method of prior art is:

Every mutually upper and lower two switching tubes become complementary conducting.Different on off states can form 8 basic voltage vectors, comprises 6 non-zero basic voltage vectors with 2 Zero voltage vectors as shown in Figure 2.In figure: 1 represents upper arm conducting, and 0 represents underarm conducting.

6 non-zero basic voltage vectors are

${\stackrel{\→}{U}}_k=\frac{2}{3}(u_{\mathrm{AN}}+\mathrm{\α}{u}_{\mathrm{BN}}+{\mathrm{\α}}^2{u}_{\mathrm{CN}})=\frac{2}{3}{U}_{\mathrm{DC}}{e}^{j(k-1)\frac{\mathrm{\π}}{3}},(k=\mathrm{1,2},\·\·\·6)---\left(1\right)$

In formula: u _aN, u _bN, u _cNfor three-phase voltage the neutral point N of load (when load is delta connection with respect to).

Any one voltage vector in the hexagon inscribed circle of the end points composition with 6 non-zero basic voltage vectors

${\stackrel{\→}{U}}_s=U_o{e}^{\mathrm{j\θ}}---\left(2\right)$

In formula: U _ofor the amplitude of voltage vector; θ is the phase angle of voltage vector.

can be synthesized according to the principle of " volt-second balance " by two basic voltage vectors of being close to and Zero voltage vector.As shown in Figure 2, taking 1. sector as example, action time be T _s(carrier cycle, also referred to as modulation period, switch periods), T _sV1, T _sV2.The parallelogram law of being synthesized by vector,

$T_s{\stackrel{\→}{U}}_s=T_{\mathrm{SV}1}{\stackrel{\→}{U}}_1+T_{\mathrm{SV}2}{\stackrel{\→}{U}}_2---\left(3\right)$

Can obtain

$\left\{\begin{array}{c}{T}_{\mathrm{SV}1}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\π}}{3}-\mathrm{\θ})\\ T_{\mathrm{SV}2}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\θ}\end{array}\right.---\left(4\right)$

$T_{\mathrm{SV}1}+T_{\mathrm{SV}2}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\π}}{3}+\mathrm{\θ})---\left(5\right)$

In formula: U _ofor the amplitude of command voltage vector; θ is the phase angle of command voltage vector; U _dCfor direct voltage.

Other time need to be by Zero voltage vector with supplement, be its action time

T _SV0＝T _s-T _SV1-T _SV2 (6)

As long as make two non-zero basic voltage vectors action times and two Zero voltage vector effect total times meet relational expression above, can meet the voltage equivalence in average meaning.Space vector pulse width modulation has only specified the time of basic voltage vectors effect, does not specify order and the distribution of its effect.Conventionally adopt symmetrical type of action as shown in Figure 3,

${\stackrel{\→}{U}}_0\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_7\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_0---\left(7\right)$

Two Zero voltage vectors with action time be respectively

$T_{\mathrm{SV}00}=T_{\mathrm{SV}07}=\frac{T_{\mathrm{SV}0}}{2}---\left(8\right)$

Because pulse-width modulation is the general principle based on " volt-second balance ", in the time obtaining the fundamental voltage needing, inevitably bring harmonic wave.Harmonic wave brings energy loss, causes that the motor feels hot; Low-frequency harmonics can also cause torque pulsation, and then causes mechanical oscillation, causes audible noise.Although improving modulating frequency (also referred to as switching frequency, carrier frequency) can improve, and can reduce above audible noise if particularly modulating frequency is brought up to 18kHz, high switching frequency must increase switching loss.Precipitous pulse also causes serious electromagnetic interference, affects the normal operation of other electronic equipments.Particularly fixed switching frequency has caused switching frequency integral multiple and near harmonic wave to have larger amplitude; Two fixing zero vector methods of salary distribution action time, symmetrical high level arrangement have aggravated the peak value of collection bunch harmonic wave, can increase the weight of electromagnetic interference etc.

Therefore, how in obtaining required fundamental voltage, reduce the ill effects such as mechanical oscillation that the large peak value of discrete set bunch frequency spectrum brings, audible noise, electromagnetic radiation and be one and expect the problem solving.

Summary of the invention

The object of the invention is to propose a kind of equipment that mixes stochastic space voltage vector pulse duration modulation method that adopts, to reduce the certainty Using dSPACE of SVPWM collection bunch problem that harmonic spectrum peak value brings, launch to weaken the ill effects such as noise that can harmonic reduction causes under lower switching frequency by concentrating on modulating frequency multiple and near collection bunch frequency spectrum.

In order to achieve the above object, the invention provides a kind of stochastic space voltage vector pulse duration modulation method that mixes, control action time and the pulse location of basic voltage vectors by two stochastic variables, concrete control mode is, one of them stochastic variable is controlled the action time of basic voltage vectors by controlling the allocation proportion of two zero vector action times, another stochastic variable is carried out pulse location by the position of controlling the widest pulse of high level, and described two stochastic variables are presented as random number R ₁and R ₂.

Described mixing stochastic space voltage vector pulse duration modulation method, in the time of voltage vector pulse-width modulation under formula (7) seven segmentation type of action, action time and the pulse position of two basic Zero voltage vectors are subject to random number R ₁and R ₂control, specifically comprise the steps:

S1: according to the command voltage vector of controller output, the action time of calculating two adjacent basic voltage vectors and Zero voltage vector, Yi① district is example, and formula is

$\left\{\begin{array}{c}{T}_{\mathrm{SV}1}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\π}}{3}-\mathrm{\θ})\\ T_{\mathrm{SV}2}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\θ}\\ T_{\mathrm{SV}0}=T_s-T_{\mathrm{SV}1}-T_{\mathrm{SV}2}\end{array}\right.---\left(9\right)$

In formula: T _sfor carrier cycle (modulation period, switch periods), T _sV1, T _sV2be the action time of two adjacent basic voltage vectors, T _sV0for the action time of Zero voltage vector, U _ofor the amplitude of command voltage vector, θ is the phase angle of command voltage vector, U _dCfor direct voltage;

S2: be created on the random number R on interval [0,1] according to the probability distribution of setting ₁;

S3: calculate Zero voltage vector with t action time _sV00and T _sV07, formula is

$\left\{\begin{array}{c}{T}_{\mathrm{SV}00}=R_1{T}_{\mathrm{SV}0}\\ T_{\mathrm{SV}07}=(1-R_1)T_{\mathrm{SV}0}\end{array}\right.---\left(10\right);$

S4: be created on interval [K according to the probability distribution of setting ₁, K ₂] on random number R ₂, in the type of probability distribution and step S2, generate random number R ₁probability distribution used is separate;

S5: calculate seven segmentation type of action as shown in Figure 4, that is,

${\stackrel{\→}{U}}_0\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_7\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_0---\left(7\right)$

T action time of every section of basic voltage vectors ₁, T ₂, T ₃, T ₄, T ₅, T ₆, T ₇be respectively:

$\left\{\begin{array}{c}{T}_1=R_2{T}_{\mathrm{SV}00}\\ T_2=T_{\mathrm{SV}1}/2\\ T_3=T_{\mathrm{SV}2}/2\\ T_4=T_{\mathrm{SV}07}\\ T_5=T_{\mathrm{SV}2}/2\\ T_6=T_{\mathrm{SV}1}/2\\ T_7=(1-R_2)T_{\mathrm{SV}00}\end{array}\right.---\left(11\right);$

S6: calculated for 6 road impulse hits moment, and then the value of counter register variable, by logical circuit production burst signal.

Further, in described step S4, random number R ₂scope need meet following condition, with further determine random number R ₂scope, formula is:

$\left\{\begin{array}{c}{T}_1\≤\frac{1}{2}{T}_{\mathrm{SV}0}\\ T_1+T_4\≥\frac{1}{2}{T}_{\mathrm{SV}0}\end{array}\right.---\left(12\right)$

Or

$\left\{\begin{array}{c}{T}_7\≤\frac{1}{2}{T}_{\mathrm{SV}0}\\ T_4+T_7\≥\frac{1}{2}{T}_{\mathrm{SV}0}\end{array}\right.---\left(13\right)$

Formula (12) arranges and can obtain

$\left\{\begin{array}{c}{R}_2{R}_1{T}_{\mathrm{SV}0}\≤\frac{1}{2}{T}_{\mathrm{SV}0}\\ R_2{R}_1{T}_{\mathrm{SV}0}+(1-R_1)T_{\mathrm{SV}0}\≥\frac{1}{2}{T}_{\mathrm{SV}0}\end{array}\right.$

Arrange and can obtain again

$\left\{\begin{array}{c}{R}_2\≤\frac{1}{2R_1}\\ R_2\≥1-\frac{1}{2R_1}\end{array}\right.---\left(14\right)$

Formula (13) arranges and can obtain

$\left\{\begin{array}{c}(1-R_2)R_1{T}_{\mathrm{SV}0}\≤\frac{1}{2}{T}_{\mathrm{SV}0}\\ (1-R_1)T_{\mathrm{SV}0}+(1-R_2)R_1{T}_{\mathrm{SV}0}\≥\frac{1}{2}{T}_{\mathrm{SV}0}\end{array}\right.$

Arrange and can obtain again

$\left\{\begin{array}{c}(1-R_2)R_1\≤\frac{1}{2}\\ 1-R_2\≥1-\frac{1}{2R_1}\end{array}\right.$

Variable being changed to

$\left\{\begin{array}{c}{R}_2\≥1-\frac{1}{2R_1}\\ R_2\≤\frac{1}{2R_1}\end{array}\right.---\left(15\right)$

Formula (14) is actually a formula with (15),

$1-\frac{1}{2R_1}\≤R_2\≤\frac{1}{2R_1}---\left(16\right)$

Random number R ₂residing interval is [K ₁, K ₂], wherein

$K_1=\left\{\begin{array}{cc}0& R_1\≤\frac{1}{2}\\ 1-\frac{1}{2R_1}& R_1>\frac{1}{2}\end{array}\right.---\left(17\right)$

$K_2=\left\{\begin{array}{cc}1& R_1\≤\frac{1}{2}\\ \frac{1}{2R_1}& R_1>\frac{1}{2}\end{array}\right.---\left(18\right)$

Further, in described step S2 and S4, random number R ₁and random number R ₂the generation formula that can generate by pseudo random number, in real time produce and realize by software programming; The pseudo random number table that can be also 0～1 by span is stored in read-only memory, then random number is transformed to required scope generation random number from 0～1.

Mixing stochastic space voltage vector pulse duration modulation method provided by the invention, break in traditional certainty modulator approach the feature that two zero vector methods of salary distribution action time and high level pulse are arranged symmetrically with, weakened the large peak value of collection bunch harmonic wave of certainty space voltage vector pulse width modulation method.The present invention controls action time of basic voltage vectors and pulse location by two random numbers, the allocation proportion of two of random number controls zero vector action time, the location of another random number control impuls.Be that moment of zero is in Zero voltage vector in order to make current deviation in the time period of effect, to two Zero voltage vector all limited fields action time.

In order to solve the technical problem of electric machine phase current sampling in frequency conversion speed-adjusting system closed-loop control, the phase current sampling method of described mixing stochastic space voltage vector pulse duration modulation method is: the moment of phase current sampling is set in the mid point of modulation period, i.e. each modulation period place, as the moment of square frame institute mark in Fig. 5 (b).

Further, in order to improve the precision of current measurement, can make moment that the current sample moment avoids impulse hits to avoid the measurement of electric current to be subject to the impact that impulse hits disturbs, current sample moment and impulse hits moment have a S interval at least.Requirement according to control system to current sample error, observes the impact of impulse hits on electric current by experiment, and then definite time delay S.First inequality the right of formula (12) and formula (13) needs to deduct a time delay S, second inequality the right needs to add a time delay S, after impulse hits finishes, carry out again current measurement, now need to recalculate the span of random number R 2 according to formula (12)-(15).Formula (16) becomes

$1-\frac{1}{2R_1}+\frac{\mathrm{\λ}}{R_1}\≤R_2\≤\frac{1}{2R_1}-\frac{\mathrm{\λ}}{R_1}---\left(19\right)$

In formula: $\mathrm{\λ}=\frac{S}{T_{\mathrm{SV}0}}.$

Now, random number R ₂residing interval is [K ₁, K ₂], wherein

$K_1=\max \{1-\frac{1}{2R_1}+\frac{\mathrm{\λ}}{R_1},0\}---\left(20\right)$

$K_2=\min \{\frac{1}{2R_1}-\frac{\mathrm{\λ}}{R_1},1\}---\left(21\right)$

The symmetry of pulse has been broken in randomization in the present invention, and the pulse that generally popular digital control chip cannot produce asymmetric waveform now.Therefore, in order to achieve the above object, the present invention also provides a kind of modulator based on FPGA, and what it adopted is that above-mentioned any mixes stochastic space voltage vector pulse duration modulation method, and it is installed in the circuit of frequency conversion speed-adjusting system, mainly comprises:

(1) register district, it comprises two jumping moment register groups, one-period register, a dead band register.One-period register, is used for depositing modulation period; A dead band register, is used for setting Dead Time.Two jumping moment register groups, every group has 6 registers, the moment of depositing every phase upper arm impulse hits in these 12 registers.The moment of underarm impulse hits is determined jointly by register corresponding to upper arm jumping moment and dead band register.In every group, have two register control A phases, control forward position for one, another controls rear edge; In every group, have two register control B phases, control forward position for one, another controls rear edge; In every group, have two register control C phases, control forward position for one, another controls rear edge.Two groups are used alternatingly generation control impuls, if use first group of register a upper modulation period, this cycle is used second group, and the lower cycle will be used first group.

Count and initial value heavy cartridges circuit for (2) one, its Counter is accepted count pulse and is subtracted 1 counting according to pulse.When counter reduces to 0, then subtract 1 while overflowing, the pulse of output spill over, controls from the period register counting initial value of reloading, and starts the counting in next cycle.D type flip flop is sent into again in spill over pulse.The currency of counter send the comparator bank of pulse-generating circuit.

(3) register group commutation circuit, it comprises a d type flip flop and variable connector.This circuit is accepted the spill over from counter, controls two groups of registers alternately by variable connector, and send the comparator bank of pulse-generating circuit.

(4) pulse-generating circuit, comprises a comparator bank and d type flip flop group.Its effect is: the currency of counter and the set point in impulse hits moment compared, if identical, impulse hits.The saltus step of pulse realizes by the d type flip flop in d type flip flop group.When every phase upper arm compares, directly use the value of corresponding registers, underarm needs to participate in comparing by the value addition of the value of corresponding register and dead band register or after subtracting each other again, and to produce dead band, avoids the time delay of opening and turn-offing of switching tube to cause underarm to lead directly to.

Aspect the hardware based on FPGA realizes, the present invention is by making two register groups of control impuls jumping moment alternately participate in relatively realizing the generation of random pulses.The function of at present popular control chip is all the modulator approach being arranged symmetrically with for pulse, i.e. the same along participating in register assignment relatively before and after pulse, cannot realize mixing random space vector pulse duration modulation method provided by the invention.Main thought of the present invention is: at current period, the jumping moment register that does not participate in comparison is carried out to assignment; Finish (the lower cycle starts) moment at current period, two groups of buffer status switch, participate in relatively at the jumping moment register of current period assignment, current period participates in jumping moment register group relatively and becomes not relatively state, for assignment is prepared.The method thinking novelty, simple in structure, the speed of service is fast.

The beneficial effect of method of the present invention and modulator is:

(1) method of the present invention can significantly reduce the large peak value of certainty space vector width pulse modulation method collection bunch harmonic wave generally adopting in constant prerequisites such as ensureing fundamental voltage, on-off times;

(2) perception is accounted for to the frequency conversion speed-adjusting system of leading load, the mid point moment phase current deviation of modulation period is approximately zero, and method of the present invention is sampled by the mid point in modulation period, has improved control precision and the effect of system;

(3) modulator of the present invention can make full use of FPGA circuit customization flexibly feature, and other circuit of governing system and algorithm are integrated in a FPGA;

(4) modulator of the present invention utilizes the executed in parallel characteristic of FPGA to improve and controls the speed that software is carried out, and is the mutual fusion of advanced control algorithm and modulation algorithm more, with and application in frequency conversion speed-adjusting system guarantee is provided.

Brief description of the drawings

Fig. 1 is two level three-phase inverters and motor method of attachment schematic diagram;

Fig. 2 is basic voltage vectors and synthetic method schematic diagram;

Fig. 3 is the 7 sections of type of action schematic diagrames of symmetrical expression that generally adopt;

Fig. 4 is 7 sections of type of action schematic diagrames that the present invention adopts;

Fig. 5 is phase voltage, current deviation, sampling instant and the upper arm control signal figure of the embodiment of the present invention, wherein 5 (a) are A phase voltage figure, 5 (b) are A phase current deviation and sampling instant figure, 5 (c) are the switching signal figure of A phase upper arm, 5 (d) are the switching signal figure of B phase upper arm, and 5 (e) are the switching signal figure of C phase upper arm;

Fig. 6 is the flow chart of pulse duration modulation method provided by the invention;

Fig. 7 is an application scheme schematic diagram of the present invention;

Fig. 8 is the logical circuitry of modulator of the present invention;

Fig. 9 is 6 road method for generating pulse figure of the present invention;

Figure 10 is the spectrogram of 7 sections of type of action modulator approach phase voltages of symmetrical expression of generally adopting;

Figure 11 is the spectrogram of embodiment of the present invention phase voltage, and wherein 11 (a) and 11 (b) are that the A phase voltage pulse that inverter is exported is sampled within two different primitive periods, carry out the amplitude spectrum that Fourier transform obtains.

[main element symbol description]

1---register district; 2---counting and initial value heavy cartridges circuit;

3---register group commutation circuit; 4---pulse-generating circuit;

11---register group 1; 12---register group 2;

13---period register; 14---dead band register

21---counter; 22---heavy cartridges circuit;

31---d type flip flop; 32---variable connector;

41---comparator bank; 42---d type flip flop group;

111---register 1; 112---register 3;

113---register 5; 114---register 7;

115---register 9; 116---register 11;

121---register 2; 122---register 4;

123---register 6; 124---register 8;

125---register 10; 126---register 12.

Embodiment

For making object of the present invention, technical scheme and beneficial effect clearer, below will by execution mode, the present invention is described in further detail.

The invention provides a kind of stochastic space voltage vector pulse duration modulation method and modulator based on FPGA of mixing, the structure of its inverter as shown in Figure 1.Modulator provided by the invention can be installed between the controller and isolated drive circuit of frequency conversion speed-adjusting system, also itself and controller can be integrated in a FPGA, as shown in Figure 7.

First enforcement of the present invention need, according to the command voltage vector of controller output, to calculate the time of adjacent two basic voltage vectors, Zero voltage vector effect, and then calculate the moment of impulse hits, and implementation step is as shown in Figure 6, specific as follows:

S1: according to the command voltage vector of controller output, the action time of calculating two adjacent basic voltage vectors and Zero voltage vector, Yi① district is example, and formula is

$\left\{\begin{array}{c}{T}_{\mathrm{SV}1}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\π}}{3}-\mathrm{\θ})\\ T_{\mathrm{SV}2}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\θ}\\ T_{\mathrm{SV}0}=T_s-T_{\mathrm{SV}1}-T_{\mathrm{SV}2}\end{array}\right.---\left(9\right)$

In formula: T _sfor carrier cycle (modulation period, switch periods); T _sV1, T _sV2, T _sV0it is the action time of two adjacent basic voltage vectors and Zero voltage vector; U _ofor the amplitude of command voltage vector; θ is the phase angle of command voltage vector; U _dCfor direct voltage.

S2: be created on the random number R on interval [0,1] according to the probability distribution of setting ₁.

S3: calculate Zero voltage vector with t action time _sV00and T _sV07, formula is

$\left\{\begin{array}{c}{T}_{\mathrm{SV}00}=R_1{T}_{\mathrm{SV}0}\\ T_{\mathrm{SV}07}=(1-R_1)T_{\mathrm{SV}0}\end{array}\right.---\left(10\right)$

S4: be created on interval [K according to the probability distribution of setting ₁, K ₂] on random number R ₂, in the type of probability distribution and step S2, generate random number R ₁probability distribution used is separate;

S5: calculate seven segmentation type of action as shown in Figure 4,

${\stackrel{\→}{U}}_0\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_7\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_0---\left(7\right)$

T action time of every section of basic voltage vectors ₁, T ₂, T ₃, T ₄, T ₅, T ₆, T ₇for

$\left\{\begin{array}{c}{T}_1=R_2{T}_{\mathrm{SV}00}\\ T_2=T_{\mathrm{SV}1}/2\\ T_3=T_{\mathrm{SV}2}/2\\ T_4=T_{\mathrm{SV}07}\\ T_5=T_{\mathrm{SV}2}/2\\ T_6=T_{\mathrm{SV}1}/2\\ T_7=(1-R_2)T_{\mathrm{SV}00}\end{array}\right.---\left(11\right)$

S6: calculated for 6 road impulse hits moment, and then the value of counter register variable, by logical circuit production burst signal.

Further, in described step S4, random number R ₂scope need meet following condition

$1-\frac{1}{2R_1}\≤R_2\≤\frac{1}{2R_1}---\left(16\right)$

Stochastic variable R ₂residing interval is [K ₁, K ₂], wherein

$K_1=\left\{\begin{array}{cc}0& R_1\≤\frac{1}{2}\\ 1-\frac{1}{2R_1}& R_1>\frac{1}{2}\end{array}\right.---\left(17\right)$

$K_2=\left\{\begin{array}{cc}1& R_1\≤\frac{1}{2}\\ \frac{1}{2R_1}& R_1>\frac{1}{2}\end{array}\right.---\left(18\right)$

In the S2 of above-mentioned embodiment and S4 step, random number R ₁and R ₂the value formula that can generate by pseudo random number, in real time produce and realize by software programming; Also can be that pseudo random number table on 0～1 is stored in read-only memory by span, pointer is set in program, read pseudo random number by the movement of pointer.

To random number R ₂, random number need to be transformed to interval [K from 0～1 ₁, K ₂] upper, can adopt linear transformation as follows

R ₂＝K ₁+(K ₂-K ₁)x (22)

In formula: x is the random number on 0～1.

In order to solve the technical problem of electric machine phase current sampling in frequency conversion speed-adjusting system closed-loop control, the phase current sampling method adopting in mixing stochastic space voltage vector pulse duration modulation method of the present invention is: the moment of phase current sampling is set in the mid point of modulation period, i.e. each modulation period place, the moment as shown in square frame in Fig. 5 (b).

If system voltage is higher, consider that the measurement of electric current is subject to that impulse hits disturbs and affects, the current sample moment is avoided the moment of impulse hits, and current sample moment and impulse hits moment have a S interval at least.Requirement according to control system to current sample error, observes the impact of impulse hits on electric current by experiment, and then definite time delay S.

Now, random number R ₂residing interval is [K ₁, K ₂], wherein

$K_1=\max \{1-\frac{1}{2R_1}+\frac{\mathrm{\λ}}{R_1},0\}---\left(20\right)$

$K_2=\min \{\frac{1}{2R_1}-\frac{\mathrm{\λ}}{R_1},1\}---\left(21\right)$

In formula: $\mathrm{\λ}=\frac{S}{T_{\mathrm{SV}0}}.$

In conjunction with Fig. 8, the modulator based on FPGA provided by the invention, it comprises:

A register district (1), it comprises two jumping moment register groups: register group 1 (11) and register group 2 (12), one-period register (13), a dead band register (14).Period register (13) is used for depositing modulation period, and dead band register (14) is used for setting Dead Time.Every group of register group 1 (11) and register group 2 (12) has 6 registers, the moment of depositing every phase upper arm impulse hits in these 12 registers.The moment of underarm impulse hits is determined jointly by register corresponding to upper arm jumping moment and dead band register (14).In every group, have two register control A phases, one of them controls forward position, and another controls rear edge; In every group, have two register control B phases, one of them controls forward position, and another controls rear edge; In every group, have two register control C phases, one of them controls forward position, and another controls rear edge.Two groups are used alternatingly generation control impuls, if use register group 1 (11) a upper modulation period, this cycle is used register group 2 (12), and next cycle is used register group 1 (11).

In conjunction with Fig. 8 and Fig. 9, the register 1 (111) in register group 1 (11) is controlled the forward position of A phase upper arm, and register 3 (112) is controlled the rear edge of A phase upper arm; Register 5 (113) is controlled the forward position of B phase upper arm, and register 7 (114) is controlled the rear edge of B phase upper arm; Register 9 (115) is controlled the forward position of C phase upper arm, and register 11 (116) is controlled the rear edge of C phase upper arm.

Register 2 (121) in register group 2 (12) is controlled the forward position of A phase upper arm, and register 4 (122) is controlled the rear edge of A phase upper arm; Register 6 (123) is controlled the forward position of B phase upper arm, and register 8 (124) is controlled the rear edge of B phase upper arm; Register 10 (125) is controlled the forward position of C phase upper arm, and register 12 (126) is controlled the rear edge of C phase upper arm.

Count and initial value heavy cartridges circuit (2) for one, its Counter (21) has an input and 2 outputs, and input line connects count pulse and subtracts 1 counting according to pulse; An output line is exported current count value, connects an input line of comparand register group (41) in pulse-generating circuit (4); Another output line output spill over, when counter reduces to 0, then subtracts 1 while overflowing, and the pulse of output spill over is controlled heavy cartridges circuit (22) from period register 14 (13) the counting initial value of reloading, and starts the counting in next cycle.The input pin CP of d type flip flop (31) is sent into again in spill over pulse.The currency of counter (21) send the comparator bank (41) of pulse-generating circuit (4).Heavy cartridges circuit (22) has 2 inputs and an output, and an input line connects the spill over of counter (21), and another input connects period register 14 (13), and output line connects counter (21).

Register group commutation circuit (3), it comprises a d type flip flop (31) and variable connector (32).This circuit is accepted the spill over from counter (21), controls two groups of registers alternately by variable connector (32), and send the comparator bank (41) of pulse-generating circuit (4).Variable connector (32) has 3 inputs and an output, and its 2 inputs connect respectively register group 1 (11) and register group 2 (12); Another inputs position control end, meets the output Q of d type flip flop (31); Output line connects the input line of the comparator bank (41) of pulse-generating circuit (4).The output Q of d type flip flop (31) connects the control end of variable connector (32); The anti-phase output Q of d type flip flop (31) meets input D, and the rising edge of a pulse of realizing CP makes the output Q saltus step of d type flip flop (31) and keeps.Pulse-generating circuit (4), comprises a comparator bank (41) and d type flip flop group (42).Its effect is: the currency of counter (21) and the set point in impulse hits moment compared, if identical, impulse hits.D type flip flop group (42) has comprised 6 d type flip flop groups, corresponds respectively to 6 tunnel pulses.6 comparators in comparator bank (41), are comprised, wherein 3 comparators are corresponding to the upper arm of three-phase, each have 3 inputs and an output, these four inputs connect respectively: the currency output line of counter (21), (three-phase is respectively register 1 (111) to the pulse front edge jumping moment register of variable connector (32) output, register 5 (113), register 9 (115) or register 2 (121), register 6 (123), register 10 (125)), (three-phase is respectively register 3 (112) to rear jumping moment register, register 7 (114), register 11 (116) or register 4 (122), register 8 (124), register 12 (126)), wherein 3 comparators are corresponding to the underarm of three-phase, each have 4 inputs and an output, these four inputs connect respectively: the currency output line of counter (21), (three-phase is respectively register 1 (111) to the pulse front edge jumping moment register of variable connector (32) output, register 5 (113), register 9 (115) or register 2 (121), register 6 (123), register 10 (125)), (three-phase is respectively register 3 (112) to rear jumping moment register, register 7 (114), register 11 (116) or register 4 (122), register 8 (124), register 12 (126)), dead band register 13 (14).

When comparing, every phase upper arm directly uses the value of corresponding registers, underarm needs the value of the value of corresponding register and dead band register (14) to be added or to subtract each other afterwards to participate in relatively again, to produce dead band, avoid the time delay of opening and turn-offing of switching tube to cause underarm straight-through.The saltus step of pulse realizes by d type flip flop group (42).

The figure place of above-mentioned related register, comparator can be 16,32 or other, need to select according to concrete row such as the models of modulation period, FPGA.

Modulator approach provided by the invention and circuit can be realized having on the market on numerous FPGA, the FPGA producing as companies such as Altera, Xilinx, Lattice.

Be that 40Hz (being that motor stator voltage angle frequency is 80 π rad/s), pwm switch frequency are 2000Hz in fundamental voltage frequency, modulation ratio is to implement the present invention, phase voltage, current deviation, sampling instant and upper arm control signal figure that Fig. 5 is the embodiment of the present invention under 0.6 condition.As shown in Fig. 5 (b), in the beginning of modulation period, phase current deviation is zero; In the middle moment of modulation period, the deviation of phase current is also zero, carves and carries out current sample at this moment, measures phase current and can reduce measure error.

Figure 10 is the amplitude spectrum of 7 sections of type of action modulator approach phase voltages of symmetrical expression of generally adopting, and Figure 11 is the amplitude spectrum of embodiment of the present invention phase voltage.As shown in figure 10, very large at the peak value of switching frequency integral multiple place collection bunch harmonic wave; As shown in Figure 11 (a) and Figure 11 (b), mixing investigation of random PWM method provided by the invention can greatly reduce the peak value of switching frequency integral multiple place collection bunch harmonic wave.

The feature of method of the present invention and modulator is:

(1) the present invention, ensureing to have proposed mixing method of randomization and the modulator based on FPGA under the prerequisite that fundamental voltage, on-off times etc. are constant, can significantly reduce the large peak value of certainty space vector width pulse modulation method collection bunch harmonic wave generally adopting;

(2) perception is accounted for to the frequency conversion speed-adjusting system of leading load, at the mid point of modulation period, phase current deviation is approximately zero, carves and samples at this moment, has improved control precision and the effect of system;

(3) the present invention can make full use of FPGA circuit customization flexibly feature, and other circuit of governing system and algorithm are integrated in a FPGA;

(4) the executed in parallel characteristic of FPGA has improved and has controlled the speed that software is carried out, and is the mutual fusion of advanced control algorithm and modulation algorithm more, and application in frequency conversion speed-adjusting system provides guarantee.

Application of the present invention, solve the large spike problem of certainty SVPWM collection bunch harmonic wave, can improve Electro Magnetic Compatibility, reliability, the man-machine friendly of system, open up the new SVPWM strategy of a class, make the purposes of space vector pulse width modulation more extensive, also can support better the development of the industries such as China's electric automobile, wind power generation, there is good society and economic benefit.

The above; it is only preferred embodiment of the present invention; not the present invention is done to any pro forma restriction, simple modification, equivalent variations or modification that those skilled in the art utilize the technology contents of above-mentioned prompting to make, all drop in protection scope of the present invention.

Claims (12)

1. the modulator based on FPGA, it is characterized in that adopting a kind of stochastic space voltage vector pulse duration modulation method that mixes, it controls action time and the pulse location of basic voltage vectors by two stochastic variables, concrete control mode is, one of them stochastic variable is controlled the action time of basic voltage vectors by controlling the allocation proportion of two zero vector action times, another stochastic variable is carried out pulse location by the position of controlling the widest pulse of high level, and described two stochastic variables are presented as random number R ₁and R ₂;

The described modulator based on FPGA mainly comprises one-period register, dead band register, two group hopping time registers, counting and initial value heavy cartridges circuit, a register group commutation circuit and a pulse-generating circuit,

Described period register, is used for depositing modulation period;

Described dead band register, is used for setting Dead Time;

Described in two groups, in jumping moment register, all deposit the moment of every phase upper arm impulse hits;

Described counting and initial value heavy cartridges circuit comprise a counter, this counter is accepted count pulse and is subtracted 1 counting according to pulse, when counter reduces to 0, subtract again 1 while overflowing, output spill over pulse, controls from the period register counting initial value of reloading, and starts the counting in next cycle, d type flip flop is sent into again in spill over pulse, and the currency of counter send the comparator bank of pulse-generating circuit;

Described register group commutation circuit comprises a d type flip flop and a variable connector, this d type flip flop receives the spill over pulse from counter, controls two group hopping time registers and alternately access by variable connector the comparator bank of pulse-generating circuit with this;

Described pulse-generating circuit comprises a comparator bank and a d type flip flop group, this comparator bank compares the currency and the set point in impulse hits moment that are received from counter, if identical, realize the saltus step of pulse by the d type flip flop in d type flip flop group, the every phase upper arm direct set point with the impulse hits moment in corresponding jumping moment register relatively time, when every phase underarm comparison, need the value of Dead Time in the set point in impulse hits moment in corresponding jumping moment register and dead band register to be added or to subtract each other afterwards to participate in again relatively, to produce dead band, avoid the time delay of opening and turn-offing of switching tube to cause underarm straight-through, two group hopping time registers are alternately for comparing, if use the first group hopping time register a upper modulation period, this cycle is used the second group hopping time register, the lower cycle will re-use the first group hopping time register, in current finish time modulation period or next zero hour modulation period, two group hopping time register states switch, participate in a group hopping time register relatively in current modulation period and become not relatively state, and prepare for assignment, in current modulation period, the jumping moment register of assignment becomes comparison state, prepare to participate in relatively, two group hopping time registers alternately relatively produce control impuls.

2. the modulator based on FPGA according to claim 1, is characterized in that:

In described mixing stochastic space voltage vector pulse duration modulation method, in the time of voltage vector pulse-width modulation under formula (7) seven segmentation type of action, action time and the pulse position of two basic Zero voltage vectors are subject to random number R ₁and R ₂control, specifically comprise the steps:

${\stackrel{\→}{U}}_0\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_7\→{\stackrel{\→}{U}}_2\→{\stackrel{\→}{U}}_1\→{\stackrel{\→}{U}}_0---\left(7\right)$

S1: according to the command voltage vector of controller output, calculate T action time of two adjacent basic voltage vectors by formula (9) _sV1and T _sV2and T action time of Zero voltage vector _sV0,

$\left\{\begin{array}{c}{T}_{\mathrm{SV}1}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\π}}{3}-\mathrm{\θ})\\ T_{\mathrm{SV}2}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\θ}\\ T_{\mathrm{SV}0}=T_s-T_{\mathrm{SV}1}-T_{\mathrm{SV}2}\end{array}\right.---\left(9\right)$

In formula (9): T _sfor carrier cycle, U _ofor the amplitude of command voltage vector, θ is the phase angle of command voltage vector, U _dCfor direct voltage,

S2: be created on the random number R on interval [0,1] according to the probability distribution of setting ₁,

S3: calculate zero vector by formula (10) with t action time _sV00and T _sV07,

$\left\{\begin{array}{c}{T}_{\mathrm{SV}00}=R_1{T}_{\mathrm{SV}0}\\ T_{\mathrm{SV}07}=(1-R_1)T_{\mathrm{SV}0}\end{array}\right.---\left(10\right)$

S4: be created on interval [K according to the probability distribution of setting ₁, K ₂] on random number R ₂, in the type of probability distribution and S2, generate random number R ₁probability distribution used is separate,

S5: T action time that calculates every section of vector by formula (11) ₁, T ₂, T ₃, T ₄, T ₅, T ₆, T ₇,

$\left\{\begin{array}{c}{T}_1=R_2{T}_{\mathrm{SV}00}\\ T_2=T_{\mathrm{SV}1}/2\\ T_3=T_{\mathrm{SV}2}/2\\ T_4=T_{\mathrm{SV}07}\\ T_5=T_{\mathrm{SV}2}/2\\ T_6=T_{\mathrm{SV}1}/2\\ T_7=(1-R_2)T_{\mathrm{SV}00}\end{array}\right.---\left(11\right)$

S6: calculated for 6 road impulse hits moment, and then the value of counter register variable, by logical circuit production burst signal.

3. the modulator based on FPGA according to claim 2, is characterized in that:

In described mixing stochastic space voltage vector pulse duration modulation method, in described step S2 and S4, random number R ₁and R ₂generating mode be: the formula generating by pseudo random number, is in real time produced and realizes by software programming; Or the pseudo random number table that is 0～1 by span is stored in read-only memory, thereby then pseudo random number is transformed to required scope from 0～1 generates described random number R ₁and R ₂.

4. the modulator based on FPGA according to claim 2, is characterized in that:

In described mixing stochastic space voltage vector pulse duration modulation method, in described step S4, random number R ₂residing interval [K ₁, K ₂] according to random number R ₁determine, be specially:

$K_1=\left\{\begin{array}{cc}0& R_1\≤\frac{1}{2}\\ 1-\frac{1}{{2R}_1}& R_1>\frac{1}{2}\end{array}\right.---\left(17\right)$

$K_2=\left\{\begin{array}{cc}1& R_1\≤\frac{1}{2}\\ \frac{1}{2R_1}& R_1>\frac{1}{2}\end{array}\right.---\left(18\right).$

5. according to the modulator based on FPGA described in claim 1,2,3 or 4, it is characterized in that:

In described mixing stochastic space voltage vector pulse duration modulation method, the moment of phase current sampling is set in each modulation period place.

6. the modulator based on FPGA according to claim 5, is characterized in that:

In described mixing stochastic space voltage vector pulse duration modulation method, in order to improve the precision of current measurement, make moment that the current sample moment avoids impulse hits to avoid the measurement of electric current to be subject to the impact that impulse hits disturbs, concrete mode is, current sample moment and impulse hits moment have a S interval at least, requirement according to control system to current sample error, observes the impact of impulse hits on electric current by experiment, and then definite time delay S.

7. the modulator based on FPGA according to claim 6, is characterized in that:

In described mixing stochastic space voltage vector pulse duration modulation method, random number R ₂residing interval [K ₁, K ₂] need to be in conjunction with described interval S and random number R ₁redefine, be specially:

$K_1=\max \{1-\frac{1}{{2R}_1}+\frac{\mathrm{\λ}}{R_1},0\}---\left(20\right)$

$K_2=\min \{\frac{1}{{2R}_1}-\frac{\mathrm{\λ}}{R_1},1\}---\left(21\right)$

In formula (20) and (21):

8. according to the modulator based on FPGA described in claim 1,2,3,4,6 or 7, it is characterized in that:

In every group hopping time register, there are 6 jumping moment registers,

In every group, have two jumping moment register control A phases, one is the pulse front edge jumping moment register of controlling forward position, and another is the rear jumping moment register on edge after controlling,

In every group, have two jumping moment register control B phases, one is the pulse front edge jumping moment register of controlling forward position, and another is the rear jumping moment register on edge after controlling,

In every group, have two jumping moment register control C phases, one is the pulse front edge jumping moment register of controlling forward position, and another is the rear jumping moment register on edge after controlling;

D type flip flop group comprises 6 d type flip flops, corresponding 6 tunnel pulses respectively;

In comparator bank, comprise 6 comparators, 6 d type flip flops of corresponding d type flip flop group respectively,

The wherein upper arm of 3 corresponding three-phases of comparator, each have 3 inputs and an output, these 3 inputs connect respectively: the rear jumping moment register of the currency output line of counter, the pulse front edge jumping moment register of variable connector output and variable connector output

The wherein underarm of 3 corresponding three-phases of comparator, each have 4 inputs and an output, and these four inputs connect respectively: rear jumping moment register and the dead band register of the currency output line of counter, the pulse front edge jumping moment register of variable connector output, variable connector output.

9. the modulator based on FPGA according to claim 5, is characterized in that:

In every group hopping time register, there are 6 jumping moment registers,

In every group, have two jumping moment register control A phases, one is the pulse front edge jumping moment register of controlling forward position, and another is the rear jumping moment register on edge after controlling,

In every group, have two jumping moment register control B phases, one is the pulse front edge jumping moment register of controlling forward position, and another is the rear jumping moment register on edge after controlling,

In every group, have two jumping moment register control C phases, one is the pulse front edge jumping moment register of controlling forward position, and another is the rear jumping moment register on edge after controlling;

D type flip flop group comprises 6 d type flip flops, corresponding 6 tunnel pulses respectively;

In comparator bank, comprise 6 comparators, 6 d type flip flops of corresponding d type flip flop group respectively,

The wherein upper arm of 3 corresponding three-phases of comparator, each have 3 inputs and an output, these 3 inputs connect respectively: the rear jumping moment register of the currency output line of counter, the pulse front edge jumping moment register of variable connector output and variable connector output

The wherein underarm of 3 corresponding three-phases of comparator, each have 4 inputs and an output, and these four inputs connect respectively: rear jumping moment register and the dead band register of the currency output line of counter, the pulse front edge jumping moment register of variable connector output, variable connector output.

10. according to the modulator based on FPGA described in claim 1,2,3,4,6,7 or 9, it is characterized in that, it is realized by FPGA, and it has used the parallel characteristics of FPGA.

11. modulators based on FPGA according to claim 5, is characterized in that, it is realized by FPGA, and it has used the parallel characteristics of FPGA.

12. modulators based on FPGA according to claim 8, is characterized in that, it is realized by FPGA, and it has used the parallel characteristics of FPGA.