CN103163450A - Navigation and mapping method for testing specific structure of field programmable gate array (FPGA) - Google Patents
Navigation and mapping method for testing specific structure of field programmable gate array (FPGA) Download PDFInfo
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- CN103163450A CN103163450A CN2011104216393A CN201110421639A CN103163450A CN 103163450 A CN103163450 A CN 103163450A CN 2011104216393 A CN2011104216393 A CN 2011104216393A CN 201110421639 A CN201110421639 A CN 201110421639A CN 103163450 A CN103163450 A CN 103163450A
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Abstract
The invention discloses a navigation and mapping method for testing a specific structure of field programmable gate array (FPGA). The navigation and mapping method for the testing specific structure of the FPGA comprises the following steps: structural information of the FPGA is read; integrated result netlist files are read; user constraint files for navigation and mapping are read; and mapping is conducted according to the user constraint files. The navigation and mapping method for the testing specific structure of the FPGA conducts guidance with the aid of the user constraint files and conducts testable navigation and mapping, so that test targets can be effectively determined, besides, the goal that using conditions of each configurable logical block can be controlled is achieved, and meanwhile, test coverage rates of FPGA chips can be greatly improved.
Description
Technical field
The present invention relates to field programmable gate array and supporting electric design automation design field thereof, particularly a kind of navigation map method that ad hoc structure FPGA is tested of being applied to.
Background technology
Field programmable gate array (FPGA) has relied on its this characteristic of configurable reconstruct since emerging, be widely used in every field.The FPGA of today has structurally more obtained expanding widely, similarly be more a SOC (system on a chip) (system on a chip), it can comprise mixed signal I/O (mixed signal IO), Gigahertz receiver (Gigahertz transceivers), and a large amount of configurable logics etc. and be used for the Software tool of Computer Aided Design.Due to the complexity day by day of FPGA structure, scale is increasing, and the kind of internal resource becomes increasingly abundant, and causes the difficulty of FPGA test also more and more higher.
1), the FPGA method of testing will have identical correlativity with terminal applies, also will be independent of terminal applies simultaneously the Shahin of FPGA manufacturer Xilinx company proposes, and the special challenge of FPGA method of testing is:; 2), should have extensibility, and irrelevant with array sizes; 3), reusable and can automation mechanized operation; 4), be easy to measurement and positioning.
Because fpga chip has programmable characteristics, so even fpga chip has defective workmanship, if can determine defective locations, walk around defective place logic in when programming, so this defective is acceptable.Can avoid defective logic and programme, this ability need to realize by the design software instrument.Simultaneously, if want to reach 100% test coverage, must make that in Software tool, logical block is connected placement-and-routing's process with connection be fully controlled could realizing.
Can determine test target directed and targetedly, can control the operating position of each configurable logic block, and must increase test coverage as far as possible.Above-mentioned requirement to the FPGA test must just can be completed by an Autocad instrument.
Present test for FPGA is divided into uses relevant test and uses irrelevant test: use relevant test and refer to, use fairly large circuit design, download on fpga chip, by the situation that realizes of circuit design being tested the hardware deficiency of FPGA.The drawback of this method of testing is, is subject to the restriction of test circuit scale, and test coverage is not high, and test process does not have specific aim to the logical block of tested FPGA; Use irrelevant test and refer to, by some well-regulated test vectors, download in FPGA, test the hardware of FPGA by the Changing Pattern of input and output.Such method has certain specific aim to the test of the logical organization of hardware, can not fully controlled restriction but be subject to eda tool, and place, position that can't location defect.
Characteristics and limitation in conjunction with above-mentioned FPGA method of testing, in order to reach higher test coverage in using irrelevant test process, can test targetedly each logical block in the fpga logic structure, reach when using the FPGA design simultaneously and avoids the purpose that defective logic is programmed, the present invention proposes a kind of navigation map method that ad hoc structure FPGA is tested of being applied to.
Summary of the invention
The technical matters that (one) will solve
In view of this, fundamental purpose of the present invention is to provide a kind of navigation map method that ad hoc structure FPGA is tested of being applied to, so that the operating position of each configurable logic block is controllable.
(2) technical scheme
For achieving the above object, the invention provides a kind of navigation map method that ad hoc structure FPGA is tested of being applied to, the method comprises: read the FPGA structural information; Read the synthesis result net meter file; Read the user's unbound document for navigation map; And according to this user's unbound document, shine upon.
In such scheme, described synthesis result net meter file and described user's unbound document for navigation map are all in conjunction with the FPGA structure and generate according to test request.
In such scheme, described user's unbound document for navigation map comprises: the type of constraints module; The basic logic unit title; Configurable logic block message under basic logic unit; Logical block information under basic logic unit; And basic logic unit additional information.Described basic logic unit is the logic unit that can shine upon in the FPGA structure, comprises look-up table, distributed memory and register.Under described basic logic unit, configurable logic block information comprises: the basic logic unit with identical configurable logic block message will be boxed in same configurable logic block in mapping step; In placement-and-routing's step after mapping step, this configurable logic block is with the positional information that is assigned with.Under described basic logic unit, logical block information comprises: the basic logic unit with same logical units information will be packaged in same logical block in mapping step; In the positional information of this logical block of the vanning stage of mapping step in configurable logic block.Described basic logic unit additional information comprises: to the basic logic unit of specific (special) requirements is arranged in test process, according to a conventional method whether mapping marks.
In such scheme, described step of shining upon according to this user's unbound document specifically comprises: according to the title of basic logic unit in this user's unbound document, find this basic logic unit in described synthesis result net meter file, simultaneously configurable logic block message, affiliated logical block information and additional information under this basic logic unit are loaded in the data structure of this basic logic unit; According to the rule of affiliated identical configurable logic block and affiliated same logical units, travel through all basic logic units in described synthesis result net meter file, the basic logic unit that filters out is packaged as a logical block; According to the principle of affiliated identical configurable logic block, travel through all logical blocks in described synthesis result net meter file, according to affiliated logical block positional information, vanning is a configurable logic block with the logical block that filters out; And the synthesis result net meter file take configurable logic block as unit is passed to placement-and-routing's instrument, complete navigation map.
(3) beneficial effect
The navigation map method that ad hoc structure FPGA is tested of being applied to provided by the invention, by instructing by user's unbound document, FPGA is carried out the navigation map of measurability, can effectively determine test target, and reached the purpose that to control each configurable logic block operating position, can greatly improve the test coverage to fpga chip simultaneously.
Description of drawings
Fig. 1 is the schematic diagram according to the ad hoc structure FPGA of the embodiment of the present invention;
Fig. 2 is the schematic diagram of configurable logic block in ad hoc structure FPGA shown in Figure 1;
Fig. 3 is the schematic diagram of logical block in ad hoc structure FPGA shown in Figure 1;
Fig. 4 is applied to according to the embodiment of the present invention navigation map method flow diagram that ad hoc structure FPGA is tested;
Fig. 5 is according to each phase logic block structure chain schematic diagram of embodiment of the present invention mapping process;
Fig. 6 is according to embodiment of the present invention user unbound document content schematic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention is to provide a kind of navigation map method that ad hoc structure FPGA is tested of being applied to, wherein ad hoc structure FPGA refers to that FPGA structure that the present invention is suitable for is for the island type structure based on look-up table, to distinguish over structure or the tree structure based on MUX.The schematic diagram of this ad hoc structure FPGA as shown in Figure 1, its basic logic resource is configurable logic block (LB), a LB comprises two logical blocks (LC), LC is made of a 4-LUT (look-up table) and a d type flip flop.Wherein the schematic diagram of configurable logic block as shown in Figure 2, the schematic diagram of logical block is as shown in Figure 3.
As Fig. 4, Fig. 5 and shown in Figure 6, the embodiment of the present invention has proposed a kind of navigation map method that ad hoc structure FPGA is tested of being applied to, and specifically comprises the following steps:
Step 1: read the fpga chip structural information.The fpga chip structural information generally includes the structure of number, arrangement mode, the logical block inside of configurable logic block, the connection mode between the logical and wiring channel, and the input and output pin information etc.
Step 2: read the synthesis result net meter file.Synthesis result is usually take basic logic unit as Major Members, and it comprises 1-4 input look-up table, register and distributed memory etc.Usually the synthesis result net meter file is that synthesizer is directly exported.In test process, be convenient to the realization of navigation map, the synthesis result net meter file can be synchronizeed with user's unbound document and generated, to reach the effect of each basic logic unit in the net table being played constraint.
Step 3: read user's unbound document.User's unbound document logical description part as shown in Figure 6, it mainly comprises following a few part: the type of constraints module; The type of constraints module; Configurable logic block message under basic logic unit; Logical block information under basic logic unit; The basic logic unit additional information.
Wherein, under basic logic unit, configurable logic block information comprises: the basic logic unit with identical configurable logic block message will be boxed in same configurable logic block in mapping step; This configurable logic block is with the positional information that is assigned with in ensuing placement-and-routing step.
Under basic logic unit, logical block information comprises: the basic logic unit with same logical units information will be packaged in same logical block in mapping step; In the positional information of this logical block of the vanning stage of mapping step in configurable logic block.
The basic logic unit additional information comprises: to the basic logic unit of specific (special) requirements is arranged in test process, according to a conventional method whether mapping marks.In test-purpose, the basic logic unit that has mark to shine upon not according to usual manner, in packing process, its line is not to map directly in the FPGA hardware configuration, but connects by wiring channel, tests this wiring channel with the method.
Step 4: shine upon according to this user's unbound document.In read step 1-3 All Files, every data all are recorded in the data structure of mapping tool, and mapping step is divided into two stages realizations: packing and vanning.
According to the rule of affiliated identical configurable logic block and affiliated same logical units, travel through all basic logic units in the synthesis result net meter file, the basic logic unit that filters out is packaged as a logical block.
According to the principle of affiliated identical configurable logic block, travel through all logical blocks in the synthesis result net meter file, according to affiliated logical block positional information, vanning is a configurable logic block with the logical block that filters out.
Synthesis result net meter file take configurable logic block as unit is passed to placement-and-routing's instrument, complete navigation map.
For example, user's unbound document as shown in Figure 6, constraints module type i NST is logic module.Wherein name is called lbc2r1_lut0, lbc2r1_ff0, and the basic logic unit of lbc2r1_ff1, their affiliated configurable logic block message lb is x2y1.This illustrates that they will be boxed in same configurable logic block, and simultaneously, in placement-and-routing's stage, this configurable logic block will be by the position of layout at x2y1.Their affiliated logical block information lc shows, lbc2r1_ff0 and lbc2r1_ffl are 0, the lc of lbc2r1_lut0 is 1, and, the additional information packnet of lbc2r1_ff1 is 0, explanation line of this basic logic unit in mapping process does not map directly in the FPGA hardware configuration, but connects by wiring channel.
In mapping process, two basic logic units of at first that lc information is identical lbc2r1_lut0 and lbc2r1_ff0 are packaged into a logical block, and the line of this logical block is realized by wiring channel; Lbc2r1_ffl oneself is packaged as a logical block; Then, constraint according to the lc value, be a configurable logic block with these two logical block vannings, wherein the logical block of lbc2r1_lut0 and lbc2r1_ff0 composition occupies the position of configurable logic block lc0, and the logical block that lbc2r1_ff1 forms occupies the position of configurable logic block lc1.Same method is processed every other basic logic unit in net meter file, finally generates the net meter file take configurable logic block as unit, and the output as the mapping stage offers placement-and-routing's instrument.
The present invention just can predict the result of mapping from initial comprehensive network table, and then the operating position of each configurable logic block can be controlled by instructing by user's unbound document, has improved the measurability of fpga chip and the coverage rate of test.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. one kind is applied to navigation map method that ad hoc structure FPGA is tested, it is characterized in that, the method comprises:
Read the FPGA structural information;
Read the synthesis result net meter file;
Read the user's unbound document for navigation map; And
According to this user's unbound document, shine upon.
2. the navigation map method that ad hoc structure FPGA is tested of being applied to as claimed in claim 1, it is characterized in that, described synthesis result net meter file and described user's unbound document for navigation map are all in conjunction with the FPGA structure and generate according to test request.
3. the navigation map method that ad hoc structure FPGA is tested of being applied to as claimed in claim 1, is characterized in that, described user's unbound document for navigation map comprises:
The type of constraints module;
The basic logic unit title;
Configurable logic block message under basic logic unit;
Logical block information under basic logic unit; And
The basic logic unit additional information.
4. be applied to as claimed in claim 3 navigation map method that ad hoc structure FPGA is tested, it is characterized in that, described basic logic unit is the logic unit that can shine upon in the FPGA structure, comprises look-up table, distributed memory and register.
5. be applied to as claimed in claim 3 navigation map method that ad hoc structure FPGA is tested, it is characterized in that, under described basic logic unit, configurable logic block information comprises:
Basic logic unit with identical configurable logic block message will be boxed in same configurable logic block in mapping step; In placement-and-routing's step after mapping step, this configurable logic block is with the positional information that is assigned with.
6. be applied to as claimed in claim 3 navigation map method that ad hoc structure FPGA is tested, it is characterized in that, under described basic logic unit, logical block information comprises:
Basic logic unit with same logical units information will be packaged in same logical block in mapping step; In the positional information of this logical block of the vanning stage of mapping step in configurable logic block.
7. be applied to as claimed in claim 3 navigation map method that ad hoc structure FPGA is tested, it is characterized in that, described basic logic unit additional information comprises: to the basic logic unit of specific (special) requirements is arranged in test process, according to a conventional method whether mapping marks.
8. the navigation map method that ad hoc structure FPGA is tested of being applied to as described in any one in claim 1-7, is characterized in that, described step of shining upon according to this user's unbound document specifically comprises:
Title according to basic logic unit in this user's unbound document, find this basic logic unit in described synthesis result net meter file, simultaneously configurable logic block message, affiliated logical block information and additional information under this basic logic unit are loaded in the data structure of this basic logic unit;
According to the rule of affiliated identical configurable logic block and affiliated same logical units, travel through all basic logic units in described synthesis result net meter file, the basic logic unit that filters out is packaged as a logical block;
According to the principle of affiliated identical configurable logic block, travel through all logical blocks in described synthesis result net meter file, according to affiliated logical block positional information, vanning is a configurable logic block with the logical block that filters out; And
Synthesis result net meter file take configurable logic block as unit is passed to placement-and-routing's instrument, complete navigation map.
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| CN109444630A (en) * | 2018-11-05 | 2019-03-08 | 西安智多晶微电子有限公司 | FPGA routing cell tests structure and method |
| CN112560379A (en) * | 2020-12-18 | 2021-03-26 | 广东高云半导体科技股份有限公司 | Modeling method and device for FPGA (field programmable Gate array) on-chip distributed storage unit |
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| CN112560379A (en) * | 2020-12-18 | 2021-03-26 | 广东高云半导体科技股份有限公司 | Modeling method and device for FPGA (field programmable Gate array) on-chip distributed storage unit |
| CN114239459A (en) * | 2022-02-23 | 2022-03-25 | 苏州浪潮智能科技有限公司 | Processing method, device, equipment and medium for FPGA prototype design file |
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Application publication date: 20130619 |