CN103151269B - Prepare the method for source and drain accurate SOI multi-gate structure device - Google Patents

Prepare the method for source and drain accurate SOI multi-gate structure device Download PDF

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Publication number
CN103151269B
CN103151269B CN201310103543.1A CN201310103543A CN103151269B CN 103151269 B CN103151269 B CN 103151269B CN 201310103543 A CN201310103543 A CN 201310103543A CN 103151269 B CN103151269 B CN 103151269B
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source
silica
drain
gate structure
silicon
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CN103151269A (en
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黎明
樊捷闻
李佳
许晓燕
黄如
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Peking University
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Peking University
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Priority to US14/764,155 priority patent/US9356124B2/en
Priority to PCT/CN2013/084743 priority patent/WO2014153942A1/en
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Abstract

The present invention discloses a kind of method preparing source and drain accurate SOI multi-gate structure device, comprising: the active area forming Fin strip; Form STI oxidization isolation layer; Form polycrystalline silicon dummy gate structure; Form source and drain extension area structure; Form the accurate soi structure of source and drain; Form high-k/metal gate structure.Scheme of the present invention by realizing with the cmos compatible process of conventional bulk silicon, can be incorporated in technological process easily, and under comparatively short channel length condition, still can keep less leakage current, thus reduces the power consumption of device.

Description

Prepare the method for source and drain accurate SOI multi-gate structure device
Technical field
The present invention relates to a kind of method preparing source and drain accurate SOI multi-gate structure device, belong to very lagre scale integrated circuit (VLSIC) manufacturing technology field.
Background technology
Current semiconductor manufacturing industry develops rapidly under the guidance of Moore's Law, improves constantly performance and the integration density of integrated circuit, needs to reduce power consumption as much as possible simultaneously.Preparation high-performance, the ultrashort ditch device of low-power consumption is the manufacturing focus of future semiconductor.After entering into 22 nm technology node, conventional planar field-effect transistor causes leakage current constantly to increase due to day by day serious short-channel effect, can not meet the development of semiconductor manufacturing.In order to overcome the problems referred to above, multi-gate structure device, due to its outstanding grid-control performance and transport property, improves the drive current density of unit are, thus causes gradually and pay close attention to widely while overcoming short-channel effect.
Although due to the particular geometries of multi-gate structure device itself, make it have outstanding grid-control performance, but after channel dimensions narrows down to a certain degree, still have larger leakage current, this can badly influence the power consumption of device.Use SOI substrate to reduce leakage current, but due to higher cost and the difference with original bulk silicon technological, therefore, be seldom applied in large scale integrated circuit manufacture.
Summary of the invention
The object of the invention is to still there is difficulty compared with gross leak electric current when short ditch is long for multi-gate structure device, provide a kind of method preparing source and drain accurate SOI multi-gate structure device.The program by realizing with the cmos compatible process of conventional bulk silicon, can be incorporated in technological process easily, and under comparatively short channel length condition, still can keep less leakage current, thus reduces the power consumption of device.
For three grid structures (the method for the invention goes for double-gated devices and tri-gate devices) device, the technical scheme that the present invention prepares source and drain accurate SOI multi-gate structure device comprises the steps:
A) active area of Fin strip is formed
This step main purpose is the graphic structure utilizing photoetching to form fine strip shape (Fin strip) on hard mask.
I. at silicon chip surface deposit one deck silica, (thickness is ) and one deck silicon nitride (thickness is ), as hard mask material.
Ii. by the Fin bar graphic structure of lithographic definition fine strip shape.
Iii. by dry etching, by Graphic transitions on hard mask.
Iv. utilize hard mask, by Graphic transitions on silicon chip, and remove photoresist.
B) STI(Shallow Trench Isolation is formed, shallow trench isolation) oxidization isolation layer
This step main purpose forms STI oxidization isolation layer in active area surrounding.
I. deposit one deck is thicker (more than Fin bar height above) silica, as STI material.
Ii.CMP(chemico-mechanical polishing) silica, and stop at silicon nitride surface, and make silicon nitride, silicon oxide surface planarization.
Iii. by wet etching, silicon nitride hard mask is removed.
Iv. by dry etching, return the silica carving sti region, form STI.
V. carry out trap to inject and trap annealing.
Vi. carry out substrate parasitics transistor to suppress to inject and annealing.
C) polycrystalline silicon dummy gate structure is formed
This step main purpose utilizes to sacrifice side wall to reduce the width of groove, then by backfill polysilicon, forms the polycrystalline silicon dummy gate lines of super-narrow line width.
I. dry-oxygen oxidation forms silica, as false gate dielectric layer.
Ii. deposit thicker (more than Fin bar height above) polysilicon, as gate material layer.
Iii. chemical by polysilicon planarization by CMP, stop at certain altitude place, Fin bar top.
Iv. (thickness is deposit one deck silica ), as the hard mask layer of grid line bar.
V. chemical wet etching, forms hard mask lines and grid line bar.
D) source and drain extension area structure is formed
This step main purpose is the source and drain forming multi-gate structure device.
I. deposit one deck is very thin silica, as Offset material.
Ii. carry out the injection of source and drain extension area, and anneal.
Iii. deposit one deck again silica, and carry out dry etching and return quarter, form monox lateral wall.
E) the accurate soi structure of source and drain is formed
I. etch the silicon of source and drain areas, stop at below STI surface.
Ii. deposit one deck silicon nitride, and carry out dry etching and return quarter, form silicon nitride spacer.Silicon nitride in source and drain areas groove between STI just outside monox lateral wall, and must be removed by this side wall completely.
Iii. the silicon again in anisotropic dry etching source and drain areas groove, to certain depth (20-30nm).
Iv. wet oxidation forms silica in source and drain areas groove, as accurate SOI separator.
V. wet etching removes silicon nitride spacer.
Vi. in-situ doped epitaxial monocrystalline silicon, forms highly doped lifting source and drain.
Vii. carry out the injection of source-drain area, and anneal.
F) material that high k(height k represents high-k is formed) metal-gate structures
This step main purpose is the backfill by false grid and the removal of false gate medium and corresponding high-k/metal gate material, forms high-k/metal gate structure.
I. deposit one deck silica is as dielectric layer.
Ii.CMP silica, and stop at polysilicon surface, make silica and flattening surface of polysilicon.
Iii. wet etching removes polycrystalline silicon dummy gate material.
Iv. wet etching removes the false gate medium of silica.
V. atomic layer deposition forms silica transition zone and high-k gate dielectric HfO 2.
Vi. atomic layer deposition forms metal work function regulating course TiN.
Vii. physical vapor deposition forms metal gate material Al.
Viii.CMP metal gate material Al, and stop at silicon oxide surface, make silica and Al surface planarisation.
Ix. chemical wet etching forms contact hole.
X. Metal Contact is formed and alloy.
The present invention has following technique effect:
The program by realizing with the cmos compatible process of conventional bulk silicon, can be incorporated in technological process easily, and under comparatively short channel length condition, still can keep less leakage current, thus reduces the power consumption of device.
Accompanying drawing explanation
Fig. 1 forms the device architecture schematic diagram after Fin bar.
Fig. 2 is the device architecture schematic diagram of silica after CMP for isolation.
Fig. 3 forms the device architecture schematic diagram after isolated area and active area.
Fig. 4 forms the device architecture schematic diagram after false grid.
Fig. 5 forms the device architecture schematic diagram after Offset and side wall.
Fig. 6 be form groove between source and drain areas STI after device architecture schematic diagram.
Fig. 7 forms the device architecture schematic diagram after silicon nitride spacer.
Fig. 8 is the sectional view in Fig. 7 on AA direction.
Fig. 9 is the sectional view in Fig. 7 on BB direction.
Figure 10 is again the device architecture schematic diagram after anisotropic dry etch.
Figure 11 is the sectional view in Figure 10 on AA direction.
Figure 12 is the sectional view in Fig. 1 on BB direction.
Figure 13 is the device architecture schematic diagram of wet oxidation after source and drain areas forms accurate SOI.
Figure 14 is the sectional view in Figure 13 on AA direction.
Figure 15 is the sectional view in Figure 13 on BB direction.
Figure 16 is the device architecture schematic diagram after wet etching removes silicon nitride spacer.
Figure 17 is the sectional view in Figure 16 on AA direction.
Figure 18 is the sectional view in Figure 16 on BB direction.
Figure 19 is the device architecture schematic diagram that epitaxial monocrystalline silicon forms after lifting source and drain.
Figure 20 is the device architecture schematic diagram of dielectric layer silica after CMP.
Figure 21 forms the device architecture schematic diagram after high-k/metal gate.
Figure 22 is material therefor explanation.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail, specifically provides the process program preparing ultrashort channel multi-gate structure device that realizes the present invention's proposition, and for three grid structure devices, but the scope do not limited the present invention in any way.
Preparing Fin bar width according to the following step and be about 10 nanometers, is highly 30 nanometers, and channel length is about N-shaped three grid field effect transistor of 25 nanometers:
1. low-pressure chemical vapor deposition silica on a silicon substrate
2. low-pressure chemical vapor deposition silicon nitride on silica
3. optical lithography definition Fin bar, Fin bar width is 20nm;
4. anisotropic dry etching silicon nitride;
5. anisotropic dry etch silica;
6. anisotropic dry etch silicon substrate, as shown in Figure 1;
7. remove photoresist;
8. low-pressure chemical vapor phase deposition silica on a silicon substrate
9.CMP cmp, by polysilicon planarization, stops on silicon nitride hard mask layer, as shown in Figure 2;
10. hot phosphoric acid solution isotropism wet etching silicon nitride;
11. anisotropic dry etch silica, exposes silicon, as active area, as shown in Figure 3;
12.P trap injects, note B, and Implantation Energy is 100keV, and injecting inclination angle is 0 degree, and implantation dosage is 1e13cm -2
13.P trap injects, note B, and Implantation Energy is 60keV, and injecting inclination angle is 0 degree, and implantation dosage is 1e13cm -2
14.P trap injects, note B, and Implantation Energy is 20keV, and injecting inclination angle is 0 degree, and implantation dosage is 1e13cm -2
15. traps drive into, and activate, RTP(rapid thermal annealing) annealing, 1050 degree, 20 seconds;
16. substrate parasitics transistors suppress to inject, note B, and Implantation Energy is 8keV, and injecting inclination angle is 0 degree, and implantation dosage is 1e13cm -2
17. parasitic transistors suppress to inject activation, laser annealing, 1100 degree, 1 nanosecond;
18.HF solution carries out silicon face process;
19. dry-oxygen oxidations as false gate medium;
20. low-pressure chemical vapor deposition polysilicons as false grid material;
Polysilicon is planarized to Fin bar top by 21.CMP cmp place;
22. low-pressure chemical vapor deposition silica as the hard mask material of grid line bar;
23. optical lithography definition grid line bars, grid line thickness is 25nm, and namely physical gate is long is 25nm;
24. anisotropic dry etchings silica, forms hard mask lines;
25. anisotropic dry etchings polysilicon and silica, forms false grid, as shown in Figure 4;
26. low-pressure chemical vapor deposition silica as Offset material;
27. source and drain extension areas are injected, note As, and Implantation Energy is 5keV, and injecting inclination angle is 20 degree, and implantation dosage is 1e15cm -2, inject at twice;
28. source and drain extension area impurity activations, laser annealing, 1100 degree, 1 nanosecond;
29. low-pressure chemical vapor deposition silica as spacer material;
30. anisotropic dry etch silica, forms side wall, and makes the silicon of source and drain areas out exposed, as shown in Figure 5;
31. anisotropic dry etchings silicon, forms groove, as shown in Figure 6 between source and drain areas STI;
32. low-pressure chemical vapor deposition silicon nitrides as spacer material;
33. anisotropic dry etch silicon nitride, form side wall, and make the silicon of source and drain areas out exposed, as shown in Figure 7, as shown in Figure 8, the sectional view in Fig. 7 on BB direction is as shown in Figure 9 for the sectional view in Fig. 7 on AA direction;
34. anisotropic dry etchings again silicon, as shown in Figure 10, as shown in figure 11, the sectional view in Figure 10 on BB direction is as shown in figure 12 for the sectional view in Figure 10 on AA direction;
35. wet oxidations are formed in the inside grooves of source and drain areas silica, as shown in figure 13, as shown in figure 14, the sectional view in Figure 13 on BB direction is as shown in figure 15 for the sectional view in Figure 13 on AA direction;
36. hot phosphoric acid solution isotropism wet etchings silicon nitride, as shown in figure 16, as shown in figure 17, the sectional view in Figure 16 on BB direction is as shown in figure 18 for the sectional view in Figure 16 on AA direction;
37. in-situ doped epitaxial monocrystalline silicons, form highly doped lifting source and drain, epitaxial thickness is doping content is 1e20cm -3,.The shape of epitaxial monocrystalline silicon lifting source and drain is relevant with the crystal orientation of raceway groove with the crystal face of silicon chip, and the device getting <100> crystal orientation on (100) crystal face is here example, as shown in figure 19;
38. source-drain areas inject, note As, and Implantation Energy is 10keV, and injecting inclination angle is 0 degree, and implantation dosage is 2e15cm -2;
39. source-drain area impurity activations, laser annealing, 1100 degree, 1 nanosecond;
40. low-pressure chemical vapor phase deposition silica as dielectric layer;
41.CMP cmp, by silica planarization, stops on the polysilicon layer, as shown in figure 20;
42.TMAH solution isotropism wet etching polysilicon;
43.HF solution isotropic wet etching silica;
44. by plasma impurity doping techniques, and it is highly doped that the in-situ doped technology of silicon epitaxy or monolayer doping techniques realize channel surface, and dopant dose is 1e15cm -2;
45. atomic layer depositions silica;
46. channel region impurity activations, laser annealing, 1100 degree, 1 nanosecond;
47.HF solution isotropic wet etching silica;
48. atomic layer depositions silica;
49. atomic layer depositions hafnium oxide;
50. atomic layer depositions titanium nitride;
51. physical sputtering deposits aluminium;
CMP cmp, by aluminium planarization, stops on silicon oxide layer, as shown in figure 21;
52. source and drain form contact hole and Metal Contact;
53. alloys;
Above-described embodiment is not intended to limit the present invention, any those skilled in the art, and without departing from the spirit and scope of the present invention, can do various changes and retouching, therefore protection scope of the present invention defined depending on right.

Claims (9)

1. prepare a method for source and drain accurate SOI multi-gate structure device, it is characterized in that, comprise the steps:
1) form the active area of Fin strip, comprising:
1.1) at silicon chip surface deposit one deck silica and one deck silicon nitride, as hard mask material;
1.2) by the Fin bar graphic structure of lithographic definition fine strip shape;
1.3) by dry etching, by Graphic transitions on hard mask;
1.4) utilize hard mask, by Graphic transitions on silicon chip, and remove photoresist;
2) form STI oxidization isolation layer, comprising:
2.1) deposit one deck silica, as STI material;
2.2) CMP silica, and stop at silicon nitride surface, and make silicon nitride, silicon oxide surface planarization;
2.3) by wet etching, silicon nitride hard mask is removed;
2.4) by dry etching, return the silica carving sti region, form STI;
2.5) carry out trap to inject and trap annealing;
2.6) carry out substrate parasitics transistor to suppress to inject and annealing;
3) form polycrystalline silicon dummy gate structure, comprising:
3.1) dry-oxygen oxidation forms silica, as false gate dielectric layer;
3.2) deposit one deck polysilicon, as gate material layer;
3.3) by CMP by polysilicon planarization, stop at certain altitude place, Fin bar top;
3.4) deposit one deck silica, as the hard mask layer of grid line bar;
3.5) chemical wet etching, forms hard mask lines and grid line bar;
4) form source and drain extension area structure, comprising:
4.1) deposit one deck silica, as Offset material;
4.2) carry out the injection of source and drain extension area, and anneal;
4.3) deposit one deck silica again, and carry out dry etching and return quarter, form monox lateral wall;
5) form the accurate soi structure of source and drain, comprising:
5.1) etch the silicon of source and drain areas, stop at below STI surface;
5.2) deposit one deck silicon nitride, and carry out dry etching and return quarter, form silicon nitride spacer; Silicon nitride in source and drain areas groove between STI just outside monox lateral wall, and must be removed by this side wall completely;
5.3) silicon again in anisotropic dry etching source and drain areas groove, to certain depth;
5.4) wet oxidation forms silica in source and drain areas groove, as accurate SOI separator;
5.5) wet etching removes silicon nitride spacer;
5.6) in-situ doped epitaxial monocrystalline silicon, forms highly doped lifting source and drain;
5.7) carry out the injection of source-drain area, and anneal;
6) form high-k/metal gate structure, comprising:
6.1) deposit one deck silica is as dielectric layer;
6.2) CMP silica, and stop at polysilicon surface, make silica and flattening surface of polysilicon;
6.3) wet etching removes polycrystalline silicon dummy gate material;
6.4) wet etching removes the false gate medium of silica;
6.5) atomic layer deposition forms silica transition zone and high-k gate dielectric HfO 2;
6.6) atomic layer deposition forms metal work function regulating course TiN;
6.7) physical vapor deposition forms metal gate material Al;
6.8) CMP metal gate material Al, and stop at silicon oxide surface, make silica and Al surface planarisation;
6.9) chemical wet etching forms contact hole;
6.10) Metal Contact alloy is formed.
2. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 1.1) in, the thickness of silica is the thickness of silicon nitride is
3. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 3.2) in, the thickness of polysilicon is more than Fin bar height above.
4. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 3.4) in, the thickness of silica is
5. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 4.1) in, the thickness of silica is
6. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 4.3) in, the thickness of silica is
7. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 5.2) in, the thickness of silicon nitride is
8. prepare as claimed in claim 1 the method for source and drain accurate SOI multi-gate structure device, it is characterized in that, step 5.3) described in the degree of depth be 20-30nm.
9. prepare the method for source and drain accurate SOI multi-gate structure device as claimed in claim 1, it is characterized in that, step 6.1) in, the thickness of silica is
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160064529A1 (en) * 2013-03-28 2016-03-03 Peking University Method for fabricating multi-gate structure device with source and drain having quasi-soi structure

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700593B (en) * 2013-12-18 2016-02-17 北京大学 Prepare the method for accurate SOI source and drain multi-gate device
CN103681355B (en) 2013-12-18 2016-04-06 北京大学 Prepare the method for accurate SOI source-drain field effect transistor device
CN109841525B (en) * 2017-11-27 2021-12-14 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110473916B (en) * 2019-09-18 2024-04-02 深圳爱仕特科技有限公司 Preparation method of silicon carbide MOSFET device with p+ region self-alignment process
US11211470B2 (en) * 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
WO2024081473A1 (en) * 2022-10-12 2024-04-18 Lam Research Corporation Inhibited oxide deposition for refilling shallow trench isolation

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605514B1 (en) * 2002-07-31 2003-08-12 Advanced Micro Devices, Inc. Planar finFET patterning using amorphous carbon
CN1595624A (en) * 2004-06-18 2005-03-16 北京大学 A method for preparing quasi SOI field effect transistor device
CN1622301A (en) * 2004-12-23 2005-06-01 北京大学 Method for preparing quasi dual gate field effect transistor
CN1622295A (en) * 2004-12-21 2005-06-01 北京大学 Method for preparing field effect transistor
CN1731569A (en) * 2005-08-31 2006-02-08 北京大学 Method for making MOS transistor with source-drain on insulating layer
CN101060136A (en) * 2007-06-05 2007-10-24 北京大学 A double-fin channel wrap gate field-effect transistor and its manufacture method
CN102110648A (en) * 2009-12-24 2011-06-29 中国科学院微电子研究所 Method for preparing bulk silicon gate-all-around metal oxide semiconductor field effect transistors
CN102646599A (en) * 2012-04-09 2012-08-22 北京大学 Preparation method of FinFET (Fin Field Effect Transistor) in large-scale integration circuit
CN102651321A (en) * 2011-02-25 2012-08-29 中国科学院微电子研究所 Manufacturing method for semiconductor devices

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
JP2008124189A (en) * 2006-11-10 2008-05-29 Elpida Memory Inc Semiconductor device and its manufacturing method
US8710566B2 (en) * 2009-03-04 2014-04-29 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
CN101924139B (en) * 2010-06-25 2012-05-30 北京大学 Strain channel field-effect transistor and preparation method thereof
US8389367B2 (en) * 2011-02-25 2013-03-05 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing a semiconductor device
US8778744B2 (en) * 2011-06-24 2014-07-15 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor field effect transistor
US9368603B2 (en) * 2011-09-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Contact for high-k metal gate device
US8815691B2 (en) * 2012-12-21 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a gate all around device
CN103151269B (en) * 2013-03-28 2015-08-12 北京大学 Prepare the method for source and drain accurate SOI multi-gate structure device
US9257327B2 (en) * 2013-04-09 2016-02-09 Samsung Electronics Co., Ltd. Methods of forming a Field Effect Transistor, including forming a region providing enhanced oxidation
CN103681355B (en) * 2013-12-18 2016-04-06 北京大学 Prepare the method for accurate SOI source-drain field effect transistor device
CN103700593B (en) * 2013-12-18 2016-02-17 北京大学 Prepare the method for accurate SOI source and drain multi-gate device
US9263587B1 (en) * 2014-09-04 2016-02-16 Globalfoundries Inc. Fin device with blocking layer in channel region

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605514B1 (en) * 2002-07-31 2003-08-12 Advanced Micro Devices, Inc. Planar finFET patterning using amorphous carbon
CN1595624A (en) * 2004-06-18 2005-03-16 北京大学 A method for preparing quasi SOI field effect transistor device
CN1622295A (en) * 2004-12-21 2005-06-01 北京大学 Method for preparing field effect transistor
CN1622301A (en) * 2004-12-23 2005-06-01 北京大学 Method for preparing quasi dual gate field effect transistor
CN1731569A (en) * 2005-08-31 2006-02-08 北京大学 Method for making MOS transistor with source-drain on insulating layer
CN101060136A (en) * 2007-06-05 2007-10-24 北京大学 A double-fin channel wrap gate field-effect transistor and its manufacture method
CN102110648A (en) * 2009-12-24 2011-06-29 中国科学院微电子研究所 Method for preparing bulk silicon gate-all-around metal oxide semiconductor field effect transistors
CN102651321A (en) * 2011-02-25 2012-08-29 中国科学院微电子研究所 Manufacturing method for semiconductor devices
CN102646599A (en) * 2012-04-09 2012-08-22 北京大学 Preparation method of FinFET (Fin Field Effect Transistor) in large-scale integration circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160064529A1 (en) * 2013-03-28 2016-03-03 Peking University Method for fabricating multi-gate structure device with source and drain having quasi-soi structure
US9356124B2 (en) * 2013-03-28 2016-05-31 Peking University Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure

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