CN103151246B - Based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction - Google Patents
Based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction Download PDFInfo
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Abstract
The invention discloses a kind of based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, mainly the Graphene poor continuity prepared of solution prior art and the problem such as graphene device carrier mobility is low.Implementation step is: after cleaning Si print grow carburization zone and then form 3C-SiC film; Deposit SiO on 3C-SiC film
2, and at SiO
2on make side gate transistor graphical window by lithography; By 3C-SiC and the Cl after photoetching
2reaction, generates carbon film; Carbon film sample wafer is placed in hydrofluoric acid solution and removes SiO
2; SiO will be removed
2after carbon film sample wafer be placed on Cu film, then this entirety is placed in Ar gas, anneals under high temperature, make carbon film be reconstructed into Graphene; Depositing metal Pd layer and Au layer on Graphene print, then etch the Metal Contact of side gate transistor.The Graphene continuity that the present invention makes is good, and its technical process ensure that the mobility of transistor, improves device performance.
Description
Technical field
The invention belongs to microelectronics technology, relate to a kind of method manufacturing electronic device on graphene film semi-conducting material, specifically based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction.
Technical background
Along with people are to high-performance, high reliability, the raising of low power consumption equipment demand, becomes devices on integrated circuits characteristic and more pays close attention to.Graphene, this material be made up of two-dimensional hexagonal carbon lattice, due to the electricity structure characteristic that it is outstanding, after the Lip river husband that to be disappeared by two scientist An Delie Jim of Univ Manchester UK and Ke Siteyanuowo in 2004 finds to obtain, namely by as the candidate materials manufacturing high performance device.
The new method preparing Graphene emerges in an endless stream, but uses and maximum mainly contain following two kinds:
One is chemical vapour deposition technique, it is a kind of effective ways of controlled synthesis Graphene, it is by planar substrates, as metallic film, metal single crystal etc. are placed in the decomposable presoma of high temperature, as in the atmosphere such as methane, ethene, make carbon atom be deposited on substrate surface by high annealing to form Graphene, after finally removing metallic substrates with chemical corrosion method, independently graphene film can be obtained.By selecting the growth of the Parameter adjustable control Graphene such as type, the temperature of growth, the flow of presoma of substrate, as growth rate, thickness, area etc., the maximum shortcoming of the method is that the graphene sheet layer that obtains and substrate interact by force, lose the character of many single-layer graphenes, and the continuity of Graphene not fine.
Two is thermal decomposition SiC methods, and this method is by monocrystal SiC heating to remove Si by making the SiC on surface decompose, and forms Graphene subsequently with residual carbon.But the monocrystal SiC used in SiC thermal decomposition is very expensive, and the Graphene grown out is island distribution, and hole is many, and the number of plies is uneven, and because photoetching process can make the electron mobility of Graphene reduce when making device, thus have impact on device performance.
The preparation method of existing Graphene, as " method of process for preparing graphenes by chemical vapour deposition " patent that application number is 200810113596.0, its technical scheme is: first Kaolinite Preparation of Catalyst, carry out high temperature chemical vapor deposition again, substrate with catalyst is put into anoxic reactor, substrate is made to reach 500-1200 DEG C, pass into carbon containing source of the gas again carry out chemical deposition and obtain Graphene, then Graphene is purified, namely use acid treatment or evaporate under low pressure, high temperature, to remove catalyst.The major defect of the method is: complex process, needs to remove catalyst specially, and energy resource consumption is large, and production cost is high.
Geim seminar in 2005 and Kim seminar find, under room temperature, Graphene has 10 times to the high carrier mobility of commercial silicon chip, its mobility is about 10am/Vs, and it is very little by the impact of temperature and doping effect, show the ballistic transport characteristic of room temperature submicron-scale, can reach 0.3m at 300k, this is Graphene as the most outstanding advantage of nano electron device, makes the room temperature trajectory field effect transistor of electronic engineering field very attractive become possibility.Larger Fermi velocity and low contact resistance then contribute to reducing the devices switch time further, and the operation response characteristic of ultra-high frequency is another significant advantage of graphene-based electronic device.In addition, different from the silicon used in current electronic device and metal material, Graphene is reduced to the even single phenyl ring of nanoscale and keeps good stability and electric property equally, makes exploration single-electron device become possibility.Recently, Geim seminar utilizes the method for electron beam lithography and dry etching that same Graphene is processed into quantum dot, lead-in wire and grid, manipulable graphene-based single electron field effect transistor under obtaining room temperature, solves the operating temperature limitation problem that current single electron field effect brings due to the unsteadiness of nanometer sized materials.Holland scientist then reports first graphene-based superconducting field-effect pipe, finds that Graphene still can transmit certain electric current when charge density is zero, may for low energy consumption, and switching time, fast nanoscale superconductive electronic device brought breakthrough.
IBM declares in research center to work out graphene field effect transistor fastest in the world, and operating frequency reaches 26GHz, and this is the fastest operating frequency of the grapheme transistor measured so far, and grid are long is 150nm.Because crest frequency increases along with the long reduction of grid, they believe that the operating frequency of grapheme transistor is expected to break through THz by within reducing grid further and growing to 50nm.The composition of Graphene and the carbon nano-tube of " honeycomb " lattice of mesh-like be made up of carbon atom similar.But honeycomb lattice is bent to nanotube shape by carbon nano-tube to be difficult to copy, and grapheme transistor is that carbon atom is deposited as film, and drawn out by traditional micro-shadow instrument.IBM has been demonstrated can effectively to be solved by a kind of Graphene technology of stratiform and has made with narrow shape Graphene the noise problem that transistor channels brings.In nearest demonstration, IBM claims that the THz frequency required by millimetre-wave attenuator circuit reaches by graphene film.
IBM represents that the grapheme transistor of grid at top is made by Silicon-On-Insulator wafer, all has very high operating frequency under different grid voltages and length.Result of study shows increasing along with frequency, and the response curve of conventional transistor is followed in the decline of grapheme transistor current gain.And square being inversely proportional to of most higher cutoff frequency and grid length, reach 26GHz for when 150nm grid are long.Next goal in research improves grid dielectric material, to realize the radio circuit being operated in THz frequency range.
At present, the manufacturing process of graphene field effect pipe needs the problems and suggestio considered mainly to concentrate on several aspect: first, material is considered, uses the method preparing Graphene at present, be difficult to deposit static in a dielectric substrate and go out large area Graphene in blocks to manufacture device; The second, device manufacturing method face is considered, because Graphene is a kind of zero band gap material, so in order to utilize other semi-conducting materials similar to have forbidden band to reach the characteristic controlling current delivery, designing a kind of suitable grid structure will be very important to control raceway groove; 3rd, dielectric substrate aspect is considered, substrate scattering can have a strong impact on the mobility of charge carrier, and to being added with the material of electric field, the substrate of high K dielectric is conducive to the generation preventing device breakdown.
Above-mentioned graphene preparation method, the Graphene of generation is point-like, is difficult to the large-scale semiconductor material obtaining other manufacture devices similar.Traditional TG pushes up grid technique, needs deposit medium on substrate, causes the degeneration of graphene-channel mobility; SG side grid technique, namely on the substrate having structuring graphene-channel, on vertical-channel direction, graphene-channel side, structure dissolves grid, to this grid making alive to reach the control to graphene-channel current delivery.In addition, in device manufacturing processes, mobility will be made greatly to degenerate to the etching of material, the impact of substrate scattering effect can make mobil-ity degradation equally, affects device performance.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose a kind of based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, puncture under high voltages to avoid device and reduce substrate scattering effect, optionally growing graphene forms side grid structure and can control channel current, ensure that the electron mobility of Graphene is stablized, improve device performance.
For achieving the above object, preparation method of the present invention comprises the following steps:
(1) standard cleaning is carried out to the Si substrate base of 4-12 inch;
(2) carburization zone is grown:
(2a) the Si substrate base after cleaning is put into CVD system reative cell, reative cell is vacuumized and reaches 10
-7mb
ar rank;
(2b) H is passed into reative cell
2after, make reative cell progressively be warming up to carburizing temperature 1000 DEG C-1150 DEG C, pass into
Flow is the C of 40sccm
3h
8, carbonization 4-8min is carried out to substrate, growth one deck carburization zone;
(3) reative cell is warming up to 1150 DEG C-1350 DEG C of suitable 3C-SiC growth, passes into C
3h
8and SiH
4gas, carries out 3C-SiC thin film heterogeneity epitaxial growth, and growth time is 36-60min, then at H
2progressively be cooled to room temperature under protection, complete the growth of SiC film;
(4) plasma enhanced chemical vapor deposition PECVD method is utilized at the 3C-SiC film surface grown, the SiO that deposit one deck 0.5-1 μm is thick
2mask layer;
(5) at SiO
2layer makes side gate transistor graphical window by lithography:
(5a) according to the side grid of side grid grapheme transistor, source electrode, drain electrode, conducting channel position is made into reticle;
(5b) be the acrylic resin PMMA solution of 3% in mask surface with spin coating one deck concentration, and toast 60 seconds at 180 DEG C, itself and mask are closely linked;
(5c) with electron beam, PMMA layer is exposed, by the Graphic transitions in reticle to SiO
2on mask;
(5d) use buffered hydrofluoric acid to SiO
2mask layer corrodes, and exposes 3C-SiC, forms the window of the side grid of side gate transistor, source electrode, drain electrode and conducting channel figure;
(6) print after windowing is placed in quartz ampoule, is heated to 700-1100 DEG C;
(7) in quartz ampoule, Ar gas and Cl is passed into
2the mist of gas, continues 4-7min, makes Cl
2react with exposed 3C-SiC, generate the side grid with side gate transistor, source electrode, the carbon film of drain electrode and conducting channel figure;
(8) carbon film sample wafer of generation is placed in buffered hydrofluoric acid solution to remove SiO unnecessary outside window
2;
(9) SiO will be removed
2after carbon film sample wafer be placed on Cu film, again they are together placed in Ar gas, anneal 10-30 minute at temperature is 900-1100 DEG C, make carbon film at the side grid of side gate transistor, source electrode, drain electrode and conducting channel position reconstruct continuous graphite alkene, then are removed from the print generating Graphene by Cu film;
(10) the method depositing metal Pd/Au layer of deposited by electron beam evaporation on the print generating Graphene;
(11) photolithographic contact layer:
(11a) according to side grid, source electrode, the drain metal electrode position making reticle of side gate transistor;
(11b) by concentration be 7% acrylic resin PMMA solution be spun on metal level, and with 180 DEG C baking 60 seconds, make itself and metal level close contact;
(11c) with electron beam exposure acrylic resin PMMA, make Graphic transitions in reticle on metal level, then as etching gas, RIE etching is carried out to metal level with oxygen, obtain the print after etching;
(12) print after using acetone soln immersion to etch 10 minutes, to remove residual acrylic resin PMMA, and dries, obtains side grid grapheme transistor.
The present invention compared with prior art tool has the following advantages:
1. the side grid structure grapheme transistor mentioned of the present invention is not owing to having top gate medium, too much scattering source can not be introduced, simultaneously owing to there is no photo-etching technological process, ensure that graphene film also can not and be damaged, and then ensure that the mobility of Graphene, the hysteresis avoiding the medium breakdown phenomenon that caused by gate medium and cause due to dielectric under the grid of top.
2. the present invention is by the distance d between reasonable disposition side grid and raceway groove
ch, and the relatively large unit-area capacitance C' that side grid structure brings
g, can channel resistance be reduced, improve channel conduction, simultaneously because Graphene is a kind of zero band gap material, so most of metal is in contact with it all can form ohmic contact, conveniently can carry out metallic electrode.
3. the present invention anneals on Cu film owing to utilizing, and the carbon film thus generated more easily reconstructs and forms the good Graphene of continuity.
4. 3C-SiC and Cl in the present invention
2generate the reaction of carbon film, can carry out at lower temperature and normal pressure, and reaction rate is fast.Due to 3C-SiC can heteroepitaxial growth on Si disk, thus during growing graphene, cost is low.
5. the present invention adopts selectivity structured growth on substrate to go out Graphene, do not need large area deposition grapheme material, therefore stock utilization is high.
6. the present invention compared with prior art, and its technique is simple, and energy savings, fail safe is high.
Accompanying drawing explanation
Fig. 1 is the device schematic diagram that the present invention prepares Graphene;
Fig. 2 is the flow chart that the present invention makes connecting-type side grid grapheme transistor;
Fig. 3 is the domain schematic diagram that the present invention makes connecting-type side grid grapheme transistor;
Fig. 4 is the flow chart that the present invention makes disconnected type side grid grapheme transistor;
Fig. 5 is the domain schematic diagram that the present invention makes disconnected type side grid grapheme transistor.
Embodiment
The present invention's preparation comprises etching system, electron beam evaporation system, chemical gas-phase precipitation system CVD, the microelectronic technique system that plasma enhanced CVD system PECVD, reactive ion etching RIE etc. are ripe and task equipment.Wherein task equipment as shown in Figure 1, and this equipment forms primarily of quartz ampoule 1 and resistance furnace 2, and this quartz ampoule 1 is provided with air inlet 3 and gas outlet 4, and resistance furnace is 2 is annular hollow structure, and quartz ampoule 1 is inserted in resistance furnace 2.
The present invention provides the following three kinds of embodiments making grapheme transistor.
Embodiment 1, makes connecting-type side grid grapheme transistor.
With reference to Fig. 2 and Fig. 3, the making step of the present embodiment is as follows:
Step 1: remove sample surfaces pollutant, as Fig. 2 (a).
(1.1) surface cleaning process is carried out to the Si substrate base of 4 inches, use NH
4oH+H
2o
2reagent soaks sample 10 minutes, takes out post-drying, to remove sample surfaces organic remains;
(1.2) HCl+H is used
2o
2reagent soaks sample 10 minutes, takes out post-drying, to remove ionic contamination.
Step 2: growth carburization zone.
(2.1) Si substrate base is put into CVD system reative cell, reative cell is vacuumized and reaches 10
-7mbar rank;
(2.2) at H
2when protection, reaction chamber temperature is risen to carburizing temperature 1000 DEG C, then pass into reative cell the C that flow is 40sccm
3h
8, continue 4min, grow one deck carburization zone on a si substrate.
Step 3: grow 3C-SiC film on carburization zone, as Fig. 2 (b).
(3.1) reaction chamber temperature is risen to rapidly 1150 DEG C, pass into the SiH that flow is respectively 15sccm and 35sccm
4and C
3h
8, continue 36min, carry out 3C-SiC thin film heterogeneity epitaxial growth;
(3.2) at H
2progressively reduce temperature under gas shielded to room temperature, complete the growth of 3C-SiC film.
Step 4: the 3C-SiC film surface deposit one deck SiO grown
2mask layer, as Fig. 2 (c).
(4.1) the 3C-SiC film grown is put into PECVD system, internal system pressure is adjusted to 3.0Pa, and radio-frequency power is adjusted to 100W, and temperature is adjusted to 150 DEG C;
(4.2) in PECVD system, the SiH that flow velocity is respectively 30sccm, 60sccm and 200sccm is passed into
4, N
2o and N
2, continue 30min, make SiH
4and N
2o reacts, thus at the thick SiO of 3C-SiC print surface deposition one deck 0.5 μm
2mask layer.
Step 5: at SiO
2layer carves side grid structure window, as Fig. 2 (d).
(5.1) reticle is become according to the side grid G of the side grid grapheme transistor shown in Fig. 3, source S, drain D with conducting channel graphic making;
(5.2) at SiO
2mask layer spin coating concentration is the PMMA solution of 3%, and puts into baking oven toast 60s at 180 DEG C;
(5.3) have the print of PMMA solution to carry out exposure-processed to spin coating, its process conditions are: electron accelerating voltage is 100kV, and exposure intensity is 8000 μ C/cm
2;
(5.4) with buffered hydrofluoric acid to SiO
2mask layer corrodes, by Graphic transitions in reticle to SiO
2on mask layer, expose 3C-SiC, form side grid structure figure.
Step 6: the print forming side grid structure figure is loaded quartz ampoule, and heating exhaust gas.
(6.1) print after windowing is loaded in quartz ampoule 1, quartz ampoule is placed in resistance furnace 2;
(6.2) to quartz ampoule, pass into from air inlet 3 the Ar gas that flow velocity is 80sccm, 10 minutes emptying is carried out to quartz ampoule, air is discharged from gas outlet 4;
(6.3) open resistance furnace mains switch, 700 DEG C are heated to quartz ampoule.
Step 7:3C-SiC and chlorine reaction generate carbon film, as Fig. 2 (e).
Ar gas and the Cl that flow velocity is respectively 95sccm and 5sccm is passed into quartz ampoule
2gas, continues 4min, makes Cl
2the carbon film generating grid grapheme transistor side, side grid, source electrode, drain electrode and conducting channel figure is reacted with exposed 3C-SiC.
Step 8: remove remaining SiO
2.
The print generating carbon film is taken out from quartz ampoule and is placed in the buffered hydrofluoric acid solution that hydrofluoric acid and water proportioning are 1:10, to remove the SiO outside window
2.
Step 9: reconfigured geometry functionalized graphene.
(9.1) SiO will be removed
2after carbon film sample wafer be placed on the Cu film that thickness is 250nm, as Fig. 2 (f);
(9.2) carbon film sample wafer and Cu film entirety are placed in the Ar gas that flow velocity is 25sccm, anneal 10 minutes at temperature is 900 DEG C, carbon film is made to reconstruct continuous print side grid structure figure Graphene, as Fig. 2 (g) in the side grid of side grid grapheme transistor, source electrode, drain electrode and conducting channel position;
(9.3) Cu film is removed from structuring Graphene print, obtain structuring Graphene print.
Step 10: deposited metal, as Fig. 2 (h).
(10.1) etching gate transistor side, side grid, source electrode, the method depositing metal Pd of deposited by electron beam evaporation on the Graphene print of drain electrode and conducting channel structure graph, thickness is 5nm;
(10.2) utilize the method depositing metal Au of electron beam evaporation, thickness is 100nm.
Step 11: photoetching formed Metal Contact, as Fig. 2 (i).
(11.1) spin coating concentration is on the metal layer the PMMA solution of 7%, and puts into baking oven, at 180 DEG C, toast 60s, makes that PMMA is solution cured to be attached on metal;
(11.2) reticle is made according to the metal contact pattern of the side grid of side grid structure grapheme transistor, source electrode, drain electrode;
(11.3) electron beam is first used to have the print of PMMA to expose to spin coating, again under oxygen atmosphere, be that etching gas utilizes RIE method to etch metal contact layer with oxygen, etch side grid, source electrode, the drain metal contacts of side grid structure grapheme transistor, its process conditions are: power is 100W, oxygen flow is 20sccm, and etch period is 60s.
Step 12: the sample using acetone soln immersion to make 10 minutes, takes out post-drying, obtains connecting-type side grid grapheme transistor.
Embodiment 2, makes disconnected type side grid grapheme transistor.
With reference to Fig. 4 and Fig. 5, the performing step of the present embodiment is as follows:
Step one: surface cleaning process is carried out to the Si substrate base of 12 inches, namely first uses NH
4oH+H
2o
2reagent soaks sample 10 minutes, takes out post-drying, to remove sample surfaces organic remains; Re-use HCl+H
2o
2reagent soaks sample 10 minutes, takes out post-drying, to remove ionic contamination, as Fig. 4 (a).
Step 2: growth carburization zone.Si substrate base is put into CVD system reative cell, reative cell is vacuumized and reaches 10
-7mbar rank; Again at H
2when protection, reaction chamber temperature is risen to the carburizing temperature of 1150 DEG C, then pass into reative cell the C that flow is 40sccm
3h
8, continue 8min, grow one deck carburization zone on a si substrate.
Step 3: grow 3C-SiC film on carburization zone.Reaction chamber temperature is risen to rapidly the growth temperature of 1350 DEG C, then pass into the SiH that flow is respectively 25sccm and 55sccm
4and C
3h
8, continue 60min, carry out 3C-SiC thin film heterogeneity epitaxial growth; Then at H
2progressively reduce temperature under protection to room temperature, complete the growth of 3C-SiC film, as Fig. 4 (b).
Step 4: the 3C-SiC film print grown is put into PECVD system, and internal system pressure is adjusted to 3.0Pa, and radio-frequency power is adjusted to 100W, and temperature is adjusted to 150 DEG C; The SiH that flow velocity is respectively 30sccm, 60sccm and 200sccm is passed into again in system
4, N
2o and N
2, continue 100min, make SiH
4and N
2o reacts, thus at the thick SiO2 mask layer of 3C-SiC film surface deposit one deck 1 μm, as Fig. 4 (c).
Step 5: at SiO
2mask layer etches side grid structure graphical window, as Fig. 4 (d).
(5a) reticle is made into according to the side grid G of the side grid grapheme transistor shown in Fig. 5, source S, drain D and conducting channel position;
(5b) at SiO
2mask layer spin coating concentration is the PMMA solution of 3%, and puts into baking oven toast 60s at 180 DEG C;
(5c) have the print of PMMA solution to carry out exposure-processed to spin coating, its process conditions are: electron accelerating voltage is 100kV, and exposure intensity is 9000 μ C/cm
2;
(5d) use buffered hydrofluoric acid solution to SiO
2mask layer corrodes, by Graphic transitions in reticle to SiO
2on mask layer, expose 3C-SiC, form the side grid structure graphical window of the side grid of side grid grapheme transistor, source electrode, drain electrode and conducting channel.
Step 6: the print forming side grid structure graphical window is loaded quartz ampoule, and heating exhaust gas.
(6a) print after windowing is placed in quartz ampoule 1, quartz ampoule is placed in resistance furnace 2;
(6b) to quartz ampoule, pass into from air inlet 3 the Ar gas that flow velocity is 80sccm, to quartz ampoule carry out 10 minutes emptying, air is discharged from gas outlet 4;
(6c) open resistance furnace mains switch, 1100 DEG C are heated to quartz ampoule.
Step 7: 3C-SiC and chlorine reaction generate carbon film
Ar gas that flow velocity is 98sccm is passed into and flow velocity is the Cl of 2sccm to quartz ampoule
2gas, continues 7min, makes Cl
2react with exposed 3C-SiC and generate carbon film, as Fig. 4 (e).
Step 8: remove remaining SiO
2.
The print generating carbon film is taken out from quartz ampoule and is placed in the buffered hydrofluoric acid solution that hydrofluoric acid and water proportioning are 1:10, to remove the SiO outside window
2.
Step 9: reconstruct structuring Graphene.
SiO will be removed
2after carbon film sample wafer be placed on the Cu film that thickness is 300nm, as Fig. 4 (f); Again carbon film sample wafer and Cu film entirety are placed in the Ar gas that flow velocity is 100sccm, anneal 30 minutes at temperature is 1100 DEG C, make carbon film reconstruct continuous print side grid structure figure Graphene in the side grid of side grid grapheme transistor, source electrode, drain electrode and conducting channel position; Finally Cu film is taken away from structuring Graphene print, obtain structuring Graphene print, as Fig. 4 (g).
Step 10: deposited metal, as Fig. 4 (h).
Etching gate transistor side, side grid, source electrode, on the Graphene print of drain electrode and conducting channel structure graph, the method deposition thickness of deposited by electron beam evaporation is the metal Pd of 5nm; The method deposition thickness of recycling electron beam evaporation is the metal A u of 100nm.
Step 11: photoetching formed Metal Contact, as Fig. 4 (i).
First, spin coating concentration is on the metal layer the PMMA solution of 7%, and puts into baking oven, at 180 DEG C, toast 60s;
Secondly, reticle is made according to the metal contact pattern of the side grid of side grid structure grapheme transistor, source electrode, drain electrode;
Then, electron beam is used to expose PMMA.Again under oxygen atmosphere, be that etching gas utilizes RIE method to etch metal contact layer with oxygen, etch side grid, source electrode, the drain metal contacts of side grid structure grapheme transistor, its process conditions are: power is 100W, oxygen flow is 20sccm, and etch period is 60s.
Step 12: the sample using acetone soln immersion to make 10 minutes, takes out post-drying, obtains disconnected type side grid grapheme transistor.
Embodiment 3, makes connecting-type side grid grapheme transistor.
With reference to Fig. 2 and Fig. 3, the performing step of the present embodiment is as follows:
Steps A: remove sample surfaces pollutant, as Fig. 2 (a).
(A1) surface cleaning process is carried out to the Si substrate base of 8 inches, namely first use NH
4oH+H
2o
2reagent soaks sample 10 minutes, takes out post-drying, to remove sample surfaces organic remains;
(A2) HCl+H is used
2o
2reagent soaks sample 10 minutes, takes out post-drying, to remove ionic contamination.
Step B: growth carburization zone.
(B1) Si substrate base is put into CVD system reative cell, reative cell is vacuumized and reaches 10
-7mbar rank;
(B2) at H
2when protection, reaction chamber temperature is risen to the carburizing temperature of 1050 DEG C, then pass into reative cell the C that flow is 40sccm
3h
8, continue 6min, grow one deck carburization zone on a si substrate.
Step C: grow 3C-SiC film on carburization zone, as Fig. 2 (b).
(C1) reaction chamber temperature is risen to rapidly the growth temperature of 1250 DEG C, then pass into the SiH that flow is respectively 20sccm and 45sccm
4and C
3h
8, continue 48min, carry out 3C-SiC thin film heterogeneity epitaxial growth;
(C2) at H
2progressively reduce temperature under protection to room temperature, complete the growth of 3C-SiC film.
Step D: the 3C-SiC film surface deposit one deck SiO grown
2, as Fig. 2 (c).
(D1) the 3C-SiC film print grown is put into PECVD system, internal system pressure is adjusted to 3.0Pa, and radio-frequency power is adjusted to 100W, and temperature is adjusted to 150 DEG C;
(D2) in PECVD system, the SiH that flow velocity is respectively 30sccm, 60sccm and 200sccm is passed into
4, N
2o and N
2, continue 65min, make SiH
4and N
2o reacts, thus at the thick SiO of 3C-SiC film surface deposit one deck 0.8 μm
2mask layer.
Step e: at SiO
2mask layer etches side grid structure graphical window, as Fig. 2 (d).
(E1) reticle is made into according to the side grid G of the side grid grapheme transistor shown in Fig. 3, source S, drain D and conducting channel position;
(E2) at SiO
2mask layer spin coating concentration is the PMMA solution of 3%, and puts into baking oven toast 60s at 180 DEG C;
(E3) have the print of PMMA solution to carry out exposure-processed to spin coating, its process conditions are: electron accelerating voltage is 100kV, and exposure intensity is 8500 μ C/cm
2;
(E4) use buffered hydrofluoric acid solution to SiO
2mask layer corrodes, by Graphic transitions in reticle to SiO
2on mask layer, expose 3C-SiC, form the side grid structure graphical window of the side grid of side grid grapheme transistor, source electrode, drain electrode and conducting channel.
Step F: the print forming side grid structure graphical window is loaded quartz ampoule, and heating exhaust gas.
(F1) print after windowing is placed in quartz ampoule 1, quartz ampoule is placed in resistance furnace 2;
(F2) to quartz ampoule, pass into from air inlet 3 the Ar gas that flow velocity is 80sccm, to quartz ampoule carry out 10 minutes emptying, air is discharged from gas outlet 4;
(F3) open resistance furnace mains switch, 1100 DEG C are heated to quartz ampoule.
Step G:3C-SiC and chlorine reaction generate carbon film, as Fig. 2 (e).
Ar gas and the Cl that flow velocity is respectively 97sccm and 3sccm is passed into quartz ampoule
2gas, continues 5min, makes Cl
2react with exposed 3C-SiC and generate carbon film.
Step H: remove remaining SiO
2.
The print generating carbon film is taken out from quartz ampoule and is placed in the buffered hydrofluoric acid solution that hydrofluoric acid and water proportioning are 1:10, to remove the SiO outside window
2.
Step I: reconstruct structuring Graphene.
SiO will be removed
2after carbon film sample wafer be placed on the Cu film that thickness is 280nm, as Fig. 2 (f), this entirety is placed in the Ar gas that flow velocity is 65sccm again, anneal 20 minutes at temperature is 1000 DEG C, make carbon film reconstruct continuous print side grid structure figure Graphene in the side grid of side grid grapheme transistor, source electrode, drain electrode and conducting channel position; Then Cu film is taken away from structuring Graphene print, obtain structuring Graphene print, as Fig. 2 (g).
Step J: deposited metal, as Fig. 2 (h).
Etching gate transistor side, side grid, source electrode, on the Graphene print of drain electrode and conducting channel structure graph, the method deposition thickness of first deposited by electron beam evaporation is 5nm metal Pd, and the method deposition thickness of recycling electron beam evaporation is the metal A u of 100nm.
Step K: photoetching formed Metal Contact, as Fig. 2 (i).
(K1) spin coating concentration is on the metal layer the PMMA solution of 7%, and puts into baking oven, at 180 DEG C, toast 60s;
(K2) reticle is made according to the metal contact pattern of the side grid of side grid structure grapheme transistor, source electrode, drain electrode;
(K3) electron beam is used to expose PMMA, again under oxygen atmosphere, be that etching gas utilizes RIE method etching sheet metal with oxygen, etch side grid, source electrode, the drain metal contacts of side grid structure grapheme transistor, the process conditions of its etching are: power is 100W, oxygen flow is 20sccm, and etch period is 60s.
Step L: the sample using acetone soln immersion to make 10 minutes, takes out post-drying, obtains connecting-type side grid grapheme transistor.
More than describing is only several specific embodiment of the present invention; do not form any limitation of the invention; obviously for those skilled in the art; after having understood content of the present invention and principle; all may not deviate from the principle of the invention; when structure, carry out the various amendment in form and details and change, but these corrections based on inventive concept and change are still within claims of the present invention.
Claims (8)
1., based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, comprise the following steps:
(1) standard cleaning is carried out to the Si substrate base of 4-12 inch;
(2) carburization zone is grown:
(2a) the Si substrate base after cleaning is put into CVD system reative cell, reative cell is vacuumized and reaches 10
-7mbar rank;
(2b) H is passed into reative cell
2after, make reative cell progressively be warming up to carburizing temperature 1000 DEG C-1150 DEG C, pass into the C that flow is 40sccm
3h
8, carbonization 4-8min is carried out to substrate, growth one deck carburization zone;
(3) reative cell is warming up to 1150 DEG C-1350 DEG C of suitable 3C-SiC growth, passes into C
3h
8and SiH
4gas, carries out 3C-SiC thin film heterogeneity epitaxial growth, and growth time is 36-60min, then at H
2progressively be cooled to room temperature under protection, complete the growth of SiC film;
(4) plasma enhanced chemical vapor deposition PECVD method is utilized at the 3C-SiC film surface grown, the SiO that deposit one deck 0.5-1 μm is thick
2mask layer;
(5) at SiO
2layer makes side gate transistor graphical window by lithography:
(5a) according to the side grid of side grid grapheme transistor, source electrode, drain electrode, conducting channel position is made into reticle;
(5b) be the acrylic resin PMMA solution of 3% in mask surface with spin coating one deck concentration, and toast 60 seconds at 180 DEG C, itself and mask are closely linked;
(5c) with electron beam, PMMA layer is exposed, by the Graphic transitions in reticle to SiO
2on mask;
(5d) use buffered hydrofluoric acid to SiO
2mask layer corrodes, and exposes 3C-SiC, forms the window of the side grid of side gate transistor, source electrode, drain electrode and conducting channel figure;
(6) print after windowing is placed in quartz ampoule, is heated to 700-1100 DEG C;
(7) in quartz ampoule, Ar gas and Cl is passed into
2the mist of gas, continues 4-7min, makes Cl
2react with exposed 3C-SiC, generate the side grid with side gate transistor, source electrode, the carbon film of drain electrode and conducting channel figure;
(8) carbon film sample wafer of generation is placed in buffered hydrofluoric acid solution to remove SiO unnecessary outside window
2;
(9) SiO will be removed
2after carbon film sample wafer be placed on Cu film, again they are together placed in Ar gas, anneal 10-30 minute at temperature is 900-1100 DEG C, make carbon film at the side grid of side gate transistor, source electrode, drain electrode and conducting channel position reconstruct continuous graphite alkene, then are removed from the print generating Graphene by Cu film;
(10) the method depositing metal Pd/Au layer of deposited by electron beam evaporation on the print generating Graphene;
(11) photolithographic contact layer:
(11a) according to side grid, source electrode, the drain metal electrode position making reticle of side gate transistor;
(11b) by concentration be 7% acrylic resin PMMA solution be spun on metal level, and with 180 DEG C baking 60 seconds, make itself and metal level close contact;
(11c) with electron beam exposure acrylic resin PMMA, make Graphic transitions in reticle on metal level, then as etching gas, RIE etching is carried out to metal level with oxygen, obtain the print after etching;
(12) print after using acetone soln immersion to etch 10 minutes, to remove residual acrylic resin PMMA, and dries, obtains side grid grapheme transistor.
2. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, it is characterized in that the SiH passed in described step (3)
4and C
3h
8, its flow is respectively 15-25sccm and 35-55sccm.
3. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, it is characterized in that utilizing PECVD deposit SiO in described step (4)
2, its process conditions are:
SiH
4, N
2o and N
2flow velocity be respectively 30sccm, 60sccm and 200sccm,
Reaction chamber internal pressure is 3.0Pa,
Radio-frequency power is 100W,
Deposition temperature is 150 DEG C,
Deposition time is 30-100min.
4. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, it is characterized in that PMMA layer is exposed with electron beam described in step (5c), its process conditions are: electron accelerating voltage 100kV, and exposure intensity is 8000-9000 μ C/cm
2.
5. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, it is characterized in that the Ar gas that described step (7) passes into and Cl
2gas, flow velocity is respectively 95-98sccm and 2-5sccm, Ar gas and Cl
2the overall flow rate of gas is 100sccm.
6. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, pass into Ar gas when it is characterized in that described step (9) is annealed, its flow velocity is 25-100sccm; Use Cu film to cover, its thickness is 250-300nm.
7. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, it is characterized in that the electron beam evaporation depositing metal contact Pd/Au layer in described step (10), its metal Pd layer thickness is 5nm, metal A u layer thickness is 100nm.
8. according to claim 1 based on the annealing of Cu film and the side grid grapheme transistor preparation method of chlorine reaction, it is characterized in that in described step (11c), utilizing RIE method to etch metal contact layer, its process conditions are: power is 100W, oxygen flow is 20sccm, and etch period is 60s.
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