CN103150440A - Simulation method of module-level circuit netlist - Google Patents
Simulation method of module-level circuit netlist Download PDFInfo
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- CN103150440A CN103150440A CN2013100812423A CN201310081242A CN103150440A CN 103150440 A CN103150440 A CN 103150440A CN 2013100812423 A CN2013100812423 A CN 2013100812423A CN 201310081242 A CN201310081242 A CN 201310081242A CN 103150440 A CN103150440 A CN 103150440A
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Abstract
The invention provides a simulation method of a module-level circuit netlist, which comprises an RTL (Real Time Logistics) simulation flow and a netlist simulation flow, wherein delay information used by the netlist simulation flow is obtained by conducting separate realization and delay information extraction on all modules of a chip to be verified; an sdf (Spatial Data File) of a netlist simulation module used by the netlist simulation flow is generated by separately extracting the delay information of each module from an actual circuit layout; and the step of building a netlist simulation platform is to replace an RTL module requiring netlist simulation with the netlist simulation module based on an RTL simulation platform, reserve other RTL modules, and add the delay information to a connection line of each netlist simulation module in the netlist simulation platform. With the adoption of the simulation method, the simulation netlist quantity each time can be reduced; the simulation speed is high; multiple persons can take charge of debugging by modules when a netlist environment is built; the building speed is high; modification can be made directly based on an RTL simulation environment; the modification is convenient; and the workload is small.
Description
Technical field
The present invention relates to a kind of module level circuit meshwork list emulation mode.
Background technology
Along with digital IC scale strengthens, chip area is also increasing, and the circuit elementary cell of digital circuit physical level net table emulation bottom during due to simulation object (such as phase inverter, with door or door etc.), added again the delayed data from the side circuit domain to calculate, the simulation calculating amount is quite huge, common RTL emulation a few minutes just can the complete case of emulation, often needs just can complete in several days in the emulation of net table.So the emulation of net table usually becomes the sizable part of spended time in whole chip checking process, and net table simulated environment build also more complicated, expensive time perhaps.How to reduce the time that the emulation of whole chip net table expends, again very huge meaning.
As shown in Figure 1, current chip is realized normally whole the realization, and whole chip extracts a sdf, all reads in whole chip net table at every turn and carry out emulation when the emulation of net table, and is consuming time huge.As shown in Figure 2, be the chip realization flow schematic diagram of current techniques.It comprises following process: at first read in all RTL codes of design of chip, comprehensively produce the integral net table of chip, then extract the whole sdf file that produces chip, the net table of its generation and sdf file are all for the emulation of netting table.Can find out from this flow process, the emulation of chip net table is all that integral body is carried out, and imitative after chip integral net table, simulation time is very long; And the debugging of chip integral net table environment, task is not suitable for task division.
Net table emulation relatively, RTL emulation (being exactly procedure simulation) is because simulation object is abstract, and not calculating time-delay in side circuit, simulation velocity is a lot of soon, but also because do not comprise the working condition that time-delay in side circuit can not reflect real final chip.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of module level circuit meshwork list emulation mode, reduces the net table quantity of each emulation, and simulation velocity is high; Can be responsible for debugging by many people sub-module when building net table environment, the speed of building is fast; And can directly revise based on the RTL simulated environment, it is convenient to revise, and workload is little.
The present invention is achieved in that a kind of module level circuit meshwork list emulation mode, and it comprises RTL simulation flow and net table simulation flow; Described RTL simulation flow comprises to be built RTL emulation platform step and based on the RTL simulation process of this RTL emulation platform, guarantees the correctness of RTL design by the RTL simulation process; Described net table simulation flow comprises to be built net table emulation platform step and based on the net table simulation process of this net table emulation platform, guarantees the correctness of final chip circuit by the grade simulated step of net table; Wherein, described net table simulation flow delayed data used is all modules of chip to be verified to be carried out independent realization and delayed data extract and get, and the sdf file of the net table emulation module that described net table simulation flow is used is the delayed data of each module of extraction and producing separately in the side circuit domain; And the described net table emulation platform step of building is on the basis of described RTL emulation platform, needs to be netted the RTL module of showing emulation to replace with net table emulation module, and keep other RTL modules, and delayed data is added on the line of each the net table emulation module in net table emulation platform.
Further, described all modules of chip to be verified carry out need arranging in independent implementation procedure the module interface attribute for revising, to keep interface optimised the deleting not between each module.
Further, the described RTL of building emulation platform step comprises:
Step 11, design excitation generation unit, and will encourage generation unit to be connected to the load module of chip;
Step 12, put into all modules of chip to be verified, connect all modules in verification platform, this module is the RTL module;
Step 13, design result are collected inspection unit, are connected to the output module as a result of chip to be verified, are used for collecting simulation result and check the emulation correctness;
The described net table emulation platform step of building comprises:
Step 21, on the basis of RTL emulation platform, the RTL module of needs being netted table emulation replaces with the net table emulation module of this module;
Step 22, connect an input time delay model come transmission delay behavior between analog module before described net table emulation module, to satisfy the sequential demand of net table emulation;
Step 23, be ready to the sdf file of net table emulation module, for being used for to net table reactionary slogan, anti-communist poster sequential when the emulation.
Further, the net table emulation module that the RTL module of needs being netted table emulation in described step 21 replaces with this module is to realize by being converted of design tool, this design tool is Design_Compiler and two instruments of Prime_Time in the eda tool of the EDA synopsys of company, and two instruments of this Design_Compiler and Prime_Time realize that respectively RTL is to the conversion of net table and the extraction of sdf file.
The present invention has following advantage: the present invention combines the characteristics of two kinds of emulation, all chip modules are carried out independent realization and delayed data extraction, module to the needs checking replaces with the net table, other circuit still use RTL, can reduce like this net table quantity of each emulation, significantly improve simulation velocity, reach simultaneously the effect of checking actual chips operation circuit; Can directly revise based on the RTL simulated environment, it is convenient to revise, and workload is little; And can be responsible for debugging by many people sub-module when building net table environment, accelerate the speed of building.
Description of drawings
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the structured flowchart of net table emulation platform of the prior art.
Fig. 2 is the process flow diagram of chip implementation procedure of the prior art.
Fig. 3 is the structured flowchart of the RTL emulation platform in the present invention.
Fig. 4 is the structured flowchart of the net table emulation platform in the present invention.
Fig. 5 is the process flow diagram of the chip implementation procedure in the present invention.
Embodiment
Module level circuit meshwork list emulation mode of the present invention comprises RTL simulation flow and net table simulation flow; Described RTL simulation flow comprises to be built RTL emulation platform step and based on the RTL simulation process of this RTL emulation platform, guarantees the correctness of RTL design by the RTL simulation process; Described net table simulation flow comprises to be built net table emulation platform step and based on the net table simulation process of this net table emulation platform, guarantees the correctness of final chip circuit by the grade simulated step of net table; Wherein, described net table simulation flow delayed data used is all modules of chip to be verified to be carried out independent realization and delayed data extract and get, and the sdf file of the net table emulation module that described net table simulation flow is used is the delayed data of each module of extraction and producing separately in the side circuit domain; And the described net table emulation platform step of building is on the basis of described RTL emulation platform, needs to be netted the RTL module of showing emulation to replace with net table emulation module, and keep other RTL modules, and delayed data is added on the line of each the net table emulation module in net table emulation platform.Wherein, in the process of a secondary net table emulation, can emulation single or a plurality of RTL modules.
As extremely shown in Figure 5 in Fig. 3, in specific embodiment, of the present invention being achieved as follows:
As shown in Figure 3, the described RTL of building emulation platform step can comprise:
Step 11, design excitation generation unit, and will encourage generation unit to be connected to the load module of chip; The load module of the chip that shows in Fig. 3 is modules A;
Step 12, put into all modules of chip to be verified, Fig. 3 comprises modules A, module B and module C, connects all modules in verification platform, makes each module become the RTL module;
Step 13, design result are collected inspection unit, are connected to the output module as a result of chip to be verified, and the load module of the chip that shows in Fig. 3 is module C; Be used for collecting simulation result and check the emulation correctness;
As shown in Figure 4, the described net table emulation platform step of building can comprise:
Step 21, on the basis of RTL emulation platform, the RTL module of needs being netted table emulation replaces with the net table emulation module of this module; Fig. 4 is shown as module B for netting the RTL module of table emulation, is therefore module B net table with its net table emulation module that replaces with this module; Keep simultaneously other RTL modules, namely modules A and module C are the RTL module; The net table emulation module that the RTL module of needs being netted table emulation in this step replaces with this module is to realize by being converted of design tool, this design tool is Design_Compiler and two instruments of Prime_Time in the eda tool of the EDA synopsys of company, and two instruments of this Design_Compiler and Prime_Time realize that respectively RTL is to the conversion of net table and the extraction of sdf file.
Step 22, come transmission delay behavior between analog module at the front connection one input time delay model of described net table emulation module (being module B net table), to satisfy the sequential demand of net table emulation;
Step 23, be ready to the sdf file (being the sdf file of module B net table) of net table emulation module, for being used for to net table reactionary slogan, anti-communist poster sequential when the emulation of net table.
It should be noted that in addition, Fig. 4 is the platform structure situation when netting table emulation as an example of module B example, if net the words of table emulation as example take modules A or module C, to connect an input time delay model before modules A or module C, and make its corresponding sdf file for modules A or module C when the emulation of net table.And in the process of a secondary net table emulation, can emulation single or a plurality of RTL modules, therefore when the emulation of net table, can give different personnel with different modules and be responsible for debugging, compare an original people and debug whole net table simulation and verification platform, the present invention can many people concurrent working, has greatly accelerated verifying speed, and has reduced risk.
From the foregoing, net table emulation platform can be revised a little based on the RTL emulation platform and get final product, but in order to obtain delayed data and the sdf file for net table simulation flow, its chip realization flow is also wanted corresponding adjustment.
As shown in Figure 5, the chip realization flow is:
1. each module realizes separately; Realize respectively as modules A, module B and module C; And the module interface attribute need be set for revising in implementation procedure, to keep interface optimised the deleting not between module;
2. after module realizes separately, each module is read in separately the RTL code of this module, more comprehensively produce the net table of this module, be used for net table simulation process, as reading in respectively the RTL code of modules A, module B and module C, more comprehensively produce the net table of this modules A, module B and module C;
3. each module is extracted separately the sdf file, be used for the independent net table emulation of module; Sdf file as difference abstraction module A, module B and module C.
In sum, the present invention combines the characteristics of two kinds of emulation, all chip modules are carried out independent realization and delayed data extraction, module to the needs checking replaces with the net table, other circuit still use RTL, can reduce like this net table quantity of each emulation, significantly improve simulation velocity, reach simultaneously the effect of checking actual chips operation circuit; Can directly revise based on the RTL simulated environment, it is convenient to revise, and workload is little; And can be responsible for debugging by many people sub-module when building net table environment, accelerate the speed of building.
Although more than described the specific embodiment of the present invention; but being familiar with those skilled in the art is to be understood that; our described specific embodiment is illustrative; rather than for the restriction to scope of the present invention; those of ordinary skill in the art are in modification and the variation of the equivalence of doing according to spirit of the present invention, all should be encompassed in the scope that claim of the present invention protects.
Claims (4)
1. a module level circuit meshwork list emulation mode, is characterized in that: comprise RTL simulation flow and net table simulation flow;
Described RTL simulation flow comprises to be built RTL emulation platform step and based on the RTL simulation process of this RTL emulation platform, guarantees the correctness of RTL design by the RTL simulation process;
Described net table simulation flow comprises to be built net table emulation platform step and based on the net table simulation process of this net table emulation platform, guarantees the correctness of final chip circuit by the grade simulated step of net table;
Wherein, described net table simulation flow delayed data used is all modules of chip to be verified to be carried out independent realization and delayed data extract and get, and the sdf file of the net table emulation module that described net table simulation flow is used is the delayed data of each module of extraction and producing separately in the side circuit domain; And the described net table emulation platform step of building is on the basis of described RTL emulation platform, needs to be netted the RTL module of showing emulation to replace with net table emulation module, and keep other RTL modules, and delayed data is added on the line of each the net table emulation module in net table emulation platform.
2. a kind of module level circuit meshwork list emulation mode according to claim 1 is characterized in that:
Described all modules of chip to be verified carry out need arranging in independent implementation procedure the module interface attribute for revising, to keep interface optimised the deleting not between each module.
3. a kind of module level circuit meshwork list emulation mode according to claim 1 and 2 is characterized in that:
The described RTL of building emulation platform step comprises:
Step 11, design excitation generation unit, and will encourage generation unit to be connected to the load module of chip;
Step 12, put into all modules of chip to be verified, connect all modules in verification platform, this module is the RTL module;
Step 13, design result are collected inspection unit, are connected to the output module as a result of chip to be verified, are used for collecting simulation result and check the emulation correctness;
The described net table emulation platform step of building comprises:
Step 21, on the basis of RTL emulation platform, the RTL module of needs being netted table emulation replaces with the net table emulation module of this module;
Step 22, connect an input time delay model come transmission delay behavior between analog module before described net table emulation module, to satisfy the sequential demand of net table emulation;
Step 23, be ready to the sdf file of net table emulation module, for being used for to net table reactionary slogan, anti-communist poster sequential when the emulation.
4. a kind of module level circuit meshwork list emulation mode according to claim 1 is characterized in that:
The net table emulation module that the RTL module of needs being netted table emulation in described step 21 replaces with this module is to realize by being converted of design tool, this design tool is Design_Compiler and two instruments of Prime_Time in the eda tool of the EDA synopsys of company, and two instruments of this Design_Compiler and Prime_Time realize that respectively RTL is to the conversion of net table and the extraction of sdf file.
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Cited By (12)
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| CN104699473A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Timing constraint file generation method and device and RTL (Register Transfer Level) simulation equipment |
| CN104899076A (en) * | 2015-06-18 | 2015-09-09 | 中国科学院自动化研究所 | Super-large-scale integrated circuit gate-level net list simulation acceleration method |
| CN105512418A (en) * | 2015-12-18 | 2016-04-20 | 山东海量信息技术研究院 | Method for realizing block level verification through multiplexing system level model verification environment |
| CN106502897A (en) * | 2016-10-24 | 2017-03-15 | 北京润科通用技术有限公司 | Test model generation method and device |
| CN106529043A (en) * | 2016-11-14 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Method for carrying out sub-module comprehensive design on circuit on basis of computer software |
| CN109361378A (en) * | 2018-09-25 | 2019-02-19 | 福州瑞芯微电子股份有限公司 | The verification platform and verification method of SOC chip asynchronous clock |
| CN110750946A (en) * | 2018-07-19 | 2020-02-04 | 澜至电子科技（成都）有限公司 | Integrated circuit netlist simulation acceleration method and system thereof |
| CN111427794A (en) * | 2020-04-03 | 2020-07-17 | 天津飞腾信息技术有限公司 | Method, system and medium for accelerating simulation of storage component netlist |
| CN112069754A (en) * | 2020-09-08 | 2020-12-11 | 海光信息技术股份有限公司 | Chip design method, system, device and storage medium |
| CN112100952A (en) * | 2020-09-14 | 2020-12-18 | 海光信息技术股份有限公司 | Post-simulation method and device for integrated circuit, electronic equipment and storage medium |
| CN114626324A (en) * | 2022-02-24 | 2022-06-14 | 深圳市紫光同创电子有限公司 | Post-simulation verification method and device for FPGA circuit, electronic equipment and storage medium |
| CN115983170A (en) * | 2023-03-17 | 2023-04-18 | 中国人民解放军国防科技大学 | Advanced and backward simulation method, device and equipment for very large scale integrated circuit |
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Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104699473A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Timing constraint file generation method and device and RTL (Register Transfer Level) simulation equipment |
| CN104899076A (en) * | 2015-06-18 | 2015-09-09 | 中国科学院自动化研究所 | Super-large-scale integrated circuit gate-level net list simulation acceleration method |
| CN104899076B (en) * | 2015-06-18 | 2018-04-27 | 北京思朗科技有限责任公司 | A kind of accelerated method of super large-scale integration gate level netlist emulation |
| CN105512418A (en) * | 2015-12-18 | 2016-04-20 | 山东海量信息技术研究院 | Method for realizing block level verification through multiplexing system level model verification environment |
| CN106502897A (en) * | 2016-10-24 | 2017-03-15 | 北京润科通用技术有限公司 | Test model generation method and device |
| CN106502897B (en) * | 2016-10-24 | 2019-03-12 | 北京润科通用技术有限公司 | Test model generation method and device |
| CN106529043A (en) * | 2016-11-14 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Method for carrying out sub-module comprehensive design on circuit on basis of computer software |
| CN110750946B (en) * | 2018-07-19 | 2023-08-18 | 澜至电子科技（成都）有限公司 | Simulation acceleration method and system for integrated circuit netlist |
| CN110750946A (en) * | 2018-07-19 | 2020-02-04 | 澜至电子科技（成都）有限公司 | Integrated circuit netlist simulation acceleration method and system thereof |
| CN109361378A (en) * | 2018-09-25 | 2019-02-19 | 福州瑞芯微电子股份有限公司 | The verification platform and verification method of SOC chip asynchronous clock |
| CN109361378B (en) * | 2018-09-25 | 2022-05-24 | 瑞芯微电子股份有限公司 | Verification platform and verification method for asynchronous clock of SOC (System on chip) |
| CN111427794A (en) * | 2020-04-03 | 2020-07-17 | 天津飞腾信息技术有限公司 | Method, system and medium for accelerating simulation of storage component netlist |
| CN111427794B (en) * | 2020-04-03 | 2023-05-16 | 飞腾信息技术有限公司 | Method, system and medium for accelerating simulation of memory component netlist |
| CN112069754A (en) * | 2020-09-08 | 2020-12-11 | 海光信息技术股份有限公司 | Chip design method, system, device and storage medium |
| CN112069754B (en) * | 2020-09-08 | 2021-08-24 | 海光信息技术股份有限公司 | Chip design method, system, device and storage medium |
| CN112100952B (en) * | 2020-09-14 | 2021-06-22 | 海光信息技术股份有限公司 | Post-simulation method and device for integrated circuit, electronic equipment and storage medium |
| CN112100952A (en) * | 2020-09-14 | 2020-12-18 | 海光信息技术股份有限公司 | Post-simulation method and device for integrated circuit, electronic equipment and storage medium |
| CN114626324A (en) * | 2022-02-24 | 2022-06-14 | 深圳市紫光同创电子有限公司 | Post-simulation verification method and device for FPGA circuit, electronic equipment and storage medium |
| CN114626324B (en) * | 2022-02-24 | 2023-12-12 | 深圳市紫光同创电子有限公司 | FPGA circuit post-simulation verification method and device, electronic equipment and storage medium |
| CN115983170A (en) * | 2023-03-17 | 2023-04-18 | 中国人民解放军国防科技大学 | Advanced and backward simulation method, device and equipment for very large scale integrated circuit |
| CN115983170B (en) * | 2023-03-17 | 2023-06-16 | 中国人民解放军国防科技大学 | Advanced simulation method, device and equipment for very large scale integrated circuit |
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