CN103123657A - Method for automatically appending redundant hole for chip physical layout - Google Patents
Method for automatically appending redundant hole for chip physical layout Download PDFInfo
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- CN103123657A CN103123657A CN2011103710916A CN201110371091A CN103123657A CN 103123657 A CN103123657 A CN 103123657A CN 2011103710916 A CN2011103710916 A CN 2011103710916A CN 201110371091 A CN201110371091 A CN 201110371091A CN 103123657 A CN103123657 A CN 103123657A
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Abstract
The invention discloses a method for automatically appending a redundant hole for a chip physical layout. The method includes the following steps that step one, an area where an upper metal layer is in single-hole connection with a lower metal layer just is found out in the chip physical layout; step two, the size of space around a single through hole is calculated, whether the redundant hole can be appended around the single hole or not is judged, and the position where the redundant hole is appended is determined; step three, a redundant through hole is inserted into the position where the redundant hole can be appended; and step four, a metal layer is covered on the inserted redundant through hole, and the inserted redundant through hole is enabled to be connected with the upper metal layer and the lower metal layer. According to the method, on the premise that design rules are followed, the redundant hole is appended on the position where only the single-hole connection exists in the chip physical layout to strengthen the connection on the position, the failure probability in the manufacturing process caused due to weak through hole connection can be reduced, and therefore the yield and reliability of chips are improved.
Description
Technical field
The present invention relates to a kind of optimization method of semi-conductor chip physical layout, be specifically related to a kind of method of the chip physical layout being appended automatically the redundancy hole.
Background technology
It is one of major reason that causes chip failure that through hole lost efficacy.Especially 0.13 micron and following process node, the size of through hole is more and more less, and the probability that through hole lost efficacy is also increasing.
Lost efficacy for fear of through hole, method commonly used is increase redundancy hole.But, the present industry powerful instrument in redundancy hole that automatically domain increased without comparison also, just part has realized this function, and more or less all exists following defective:
1) need extra software;
2) can only be for digital domain;
3) can only realize in the self routing stage;
4) can't do optimization to former layout data.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method of the chip physical layout being appended automatically the redundancy hole, and it can reduce the probability of through hole Joint failure.
For solving the problems of the technologies described above, the present invention is to comprise the following steps to the technical solution that the chip physical layout appends the method in redundancy hole automatically:
The first step is found out the zone of only having single hole to be connected between upper metal layers and lower metal layer in the chip physical layout;
Second step calculates the space size around single through hole, and judgement is whether to append the redundancy hole around single hole, determines to append the position in redundancy hole;
The 3rd step is in the position insertion redundant via that can append the redundancy hole;
In the 4th step, covering metal layer on the redundant via of inserting makes the redundant via of inserting connect upper metal layers and lower metal layer.
The described metal level that described the 4th step covers on the redundant via of inserting is upper metal layers and lower metal layer.
The technique effect that the present invention can reach is:
The present invention is observing under the prerequisite of design rule, by to only having place that single hole connects to append the redundancy hole with the connection at strong this place in the chip physical layout, can reduce because through hole connects the weak probability that causes inefficacy in manufacture process, thereby improve yield and the reliability of chip.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 to Fig. 4 is the present invention appends each step in the method in redundancy hole automatically to the chip physical layout schematic diagram.
Description of reference numerals in figure:
10 is upper metal layers, and 20 is lower metal layer,
1,2,3 is single through hole region,
11,21,22 is the zone that can insert redundant via.
Embodiment
The present invention appends the method in redundancy hole automatically to the chip physical layout, comprise the following steps:
The first step is found out the connecting through hole that only has single hole in the chip physical layout;
In domain as shown in Figure 1, upper metal layers 10 and the zone that lower metal layer 20 is connected have three join domains 1, the 2, the 3rd, connect by single through hole;
Second step calculates the space size around single through hole, and judgement is whether to append the redundancy hole around single hole, determines to append the position in redundancy hole;
According to minimum design rule, require between two through holes spacing must not (process node be different less than the size of regulation, the spacing of through hole varies in size), and the spacing between the metal that covers on through hole and metal on every side also must not be less than the size of regulation, therefore, if want to append around a certain single through hole redundancy hole, need to confirm that the surrounding space of this single through hole is enough large, the spacing between the redundancy hole of being appended to guarantee and this single through hole is not less than given size;
As shown in Figure 2, through calculating, there is a zone, place 11 can append the redundancy hole around join domain 1, has a zone, place 21,22 can append the redundancy hole around join domain 2, do not have enough spaces to append the redundancy hole around join domain 3;
The 3rd step is in the position insertion redundant via that can append the redundancy hole;
As shown in Figure 3, insert redundant via at 11,21,22 places, zone respectively;
The 4th step covered upper metal layers 10 and lower metal layer 20 on the redundant via of inserting, make the redundant via of inserting connect upper metal layers 10 and lower metal layer 20, as shown in Figure 4.
The present invention carries out after the chip physical layout design is completed, to only having single hole but still having the connection of sufficient space automatically to append the redundancy hole.
Claims (2)
1. a method of the chip physical layout being appended automatically the redundancy hole, is characterized in that, comprises the following steps:
The first step is found out the zone of only having single hole to be connected between upper metal layers and lower metal layer in the chip physical layout;
Second step calculates the space size around single through hole, and judgement is whether to append the redundancy hole around single hole, determines to append the position in redundancy hole;
The 3rd step is in the position insertion redundant via that can append the redundancy hole;
In the 4th step, covering metal layer on the redundant via of inserting makes the redundant via of inserting connect upper metal layers and lower metal layer.
2. method of the chip physical layout being appended automatically the redundancy hole according to claim 1 is characterized in that: the described metal level that described the 4th step covers on the redundant via of inserting is upper metal layers and lower metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103710916A CN103123657A (en) | 2011-11-21 | 2011-11-21 | Method for automatically appending redundant hole for chip physical layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103710916A CN103123657A (en) | 2011-11-21 | 2011-11-21 | Method for automatically appending redundant hole for chip physical layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103123657A true CN103123657A (en) | 2013-05-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103710916A Pending CN103123657A (en) | 2011-11-21 | 2011-11-21 | Method for automatically appending redundant hole for chip physical layout |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112466815A (en) * | 2020-11-24 | 2021-03-09 | 上海华力集成电路制造有限公司 | Redundant through hole adding method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226930A (en) * | 2007-01-15 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure with layer or structure identification mark and manufacturing method and application thereof |
| CN101430500A (en) * | 2007-11-06 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | OPC correcting method for forming auxiliary through hole |
| CN101789032A (en) * | 2009-07-23 | 2010-07-28 | 芯原微电子(上海)有限公司 | Design method and structure thereof of physical layout of CUP weld pad zone |
| US20110140728A1 (en) * | 2007-06-22 | 2011-06-16 | Randy Yach | Method and apparatus for monitoring via's in a semiconductor fab |
-
2011
- 2011-11-21 CN CN2011103710916A patent/CN103123657A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226930A (en) * | 2007-01-15 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure with layer or structure identification mark and manufacturing method and application thereof |
| US20110140728A1 (en) * | 2007-06-22 | 2011-06-16 | Randy Yach | Method and apparatus for monitoring via's in a semiconductor fab |
| CN101430500A (en) * | 2007-11-06 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | OPC correcting method for forming auxiliary through hole |
| CN101789032A (en) * | 2009-07-23 | 2010-07-28 | 芯原微电子(上海)有限公司 | Design method and structure thereof of physical layout of CUP weld pad zone |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112466815A (en) * | 2020-11-24 | 2021-03-09 | 上海华力集成电路制造有限公司 | Redundant through hole adding method |
| CN112466815B (en) * | 2020-11-24 | 2023-08-15 | 上海华力集成电路制造有限公司 | Redundant through hole adding method |
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Application publication date: 20130529 |