CN103117954B - Method for acceleratedly processing PLOAM information of optical network unit (PLO) terminal of XG-PON1 system - Google Patents
Method for acceleratedly processing PLOAM information of optical network unit (PLO) terminal of XG-PON1 system Download PDFInfo
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Abstract
The invention relates to a method for acceleratedly processing PLOAM information of an optical network unit (ONU) terminal of an XG-PON1 system. Computer processing unit (CPU) software process and hardware process are combined in the process of processing the PLOAM information by an ONU, and MIC verification and MIC generation are partly achieved through a hardware processing portion. The ONU finishes MIC verification of received down PLOAM information by utilizing hardware, and MIC verification byte generation of up PLOAM information sent by the ONU is also finished by the hardware. The down PLOAM information refers to the PLOAM information sent by an optical line terminal (OLT) in the XG-PON1 system to the ONU, and the up PLOAM information is the PLOAM information sent by the ONU in the XG-PON1 system to the OLT. According to the method for acceleratedly processing the PLOAM information of the optical ONU terminal of the XG-PON1 system, part of functions of software are replaced by a hardware circuit, interactive speed of software data and hardware data is quickened, processing performance of the PLOAM information by the ONU is improved, processing time of the PLOAM information is reduced, and stability of the XG-PON1 system is improved.
Description
Technical field
The present invention relates to XG-PON1(10 gigabit passive optical network) access technology, be XG-PON1 system ONU(optical network unit specifically) method accelerated of the PLOAM message (physical layer operations management maintenance message) of holding process.
Background technology
XG-PON1 is as Next Generation Access technology, there is higher speed and splitting ratio, from the smooth evolution of gigabit passive optical network (GPON) technology, to advantages such as full-service operation ability supports, achieve low cost, at a distance high-peed connection, be considered to the new trend of broadband access at present.XG-PON1 connecting system is made up of local side optical line terminal equipment OLT and far-end ONU equipment.
G.987.3, the Systematical control of XG-PON1, operation and management have three passages to the XG-PON1 agreement organizing ITU-T to formulate according to International Telecommunication Union telecommunication standards: embedded operation management maintenance (embedded OAM), physical layer operations management maintenance (PLOAM), manage and control interface (OMCI).Wherein PLOAM passage is message based, one group of message of constant transmissions in descending 125us Frame and uplink burst special domain, the advantage of PLOAM channel is, compare embedded OAM management channels and function more flexibly can be provided, and speed is more than OMCI passage, XG-PON1 system ONU is defined as maximum 750 microseconds to the processing response time of PLOAM message in G.987.3 agreement.The process of the PLOAM message of current XG-PON1 system ONU end is all processed by software, uses software process PLOAM message to there is the defect that the response time does not reach the requirement that agreement specifies, be mainly manifested in following three aspects in ONU equipment:
1, the speed of the exchanges data of software and hardware is slower, because the data volume of PLOAM message is little, general employing buffer queue is deposited, and CPU is the buffer memory adopting the mode of indirect addressing to access PLOAM message, and the exchanges data between software and hardware can be caused like this to take the more time.
2, some do not need PLOAM message to be processed to be sent to software process, consume the process resource of software and hardware exchanges data time and CPU.
3, the MIC verify calculation of PLOAM message can expend the time and resource that in ONU, CPU is many, has influence on ONU to the process of PLOAM message and response speed.
The processing time of ONU to PLOAM message does not reach protocol requirement, ONU will be caused can not to complete basic registering functional or registering functional instability, cause the serious problems that whole XG-PON1 systematic function reduces in the test of the XG-PON1 system of reality.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide the method that the PLOAM Message Processing of XG-PON1 system ONU end is accelerated, hardware circuit is utilized to carry out the partial function of alternative software, and accelerate the speed of software and hardware data interaction, improve the handling property of ONU to PLOAM message, reduce the processing time of PLOAM message, improve the stability of XG-PON1 system.
For reaching above object, the technical scheme that the present invention takes is:
The method of the PLOAM Message Processing acceleration of XG-PON1 system ONU end, it is characterized in that: in ONU is to the process of PLOAM Message Processing, adopt the process of CPU software and hardware handles to combine, described hardware handles refers to: realize MIC School Affairs MIC by hardware handles part and generate
ONU adopts hardware to complete MIC verification to the downstream PLOAM message received, the up PLOAM message sent for ONU also adopts hardware to generate to complete MIC check byte, wherein: downstream PLOAM message refers to that in XG-PON1 system, OLT sends to the PLOAM message of ONU, up PLOAM message refers to that in XG-PON1 system, ONU sends to the PLOAM message of OLT
The data format of descending and up PLOAM message meets the definition of G.987.3CLAUSE11.2 chapters and sections, comprise No. ID of ONU, No. ID, PLOAM type of message, sequence number, message content, MIC check byte.
On the basis of technique scheme, described hardware handles also comprises: the login state for downstream PLOAM message foundation ONU carries out hardware filtering, and filtering ONU does not need downstream PLOAM message to be processed in this condition.
On the basis of technique scheme, described hardware handles part is provided with descending PLOAM buffer memory and up PLOAM buffer memory, and CPU adopts immediated addressing access to the read-write of PLOAM buffer memory, and PLOAM buffer memory adopts fifo fifo to realize.
On the basis of technique scheme, described hardware handles part is PLOAM Message Processing accelerating circuit, specifically comprises downlink data treatment circuit and upstream data treatment circuit; Described PLOAM Message Processing accelerating circuit completes downstream PLOAM message handling process and up PLOAM Message Processing flow process;
Described downlink data treatment circuit comprise interrupt producing circuit and the descending MIC checking circuit connected successively, descending PLOAM filtering circuit, descending PLOAM write enable generative circuit, descending PLOAM buffer circuit, descending PLOAM read enable generative circuit;
Described upstream data treatment circuit comprises that the up PLOAM connected successively writes enable generative circuit, up PLOAM buffer circuit, up PLOAM read enable generative circuit, up MIC generative circuit.
On the basis of technique scheme, the process of hardware handles part, produce following signal:
Descending PLOAM data: be parallel data signal are the downlink datas that ONU receives;
Descending PLOAM data enable: the effective index signal of descending PLOAM data, for the parallel data signal of indicating downlink PLOAM time high is effective, for time low, the parallel data of indicating downlink PLOAM is invalid;
Descending FIFO remaining space: the remaining space of indicating downlink PLOAM buffer memory, being occupied full of indicating downlink PLOAM buffer memory when being 0, for complete 1 time indicating downlink PLOAM buffer memory also there is no store data;
Descending FIFO takes up room: taking up room of indicating downlink PLOAM buffer memory, represents in buffer memory do not have data when being 0, for complete 1 is that instruction buffer memory is occupied full;
Descending FIFO writes enable: writing enable generative circuit by descending PLOAM and produce, writing descending FIFO buffer memory, for writing time high, for being failure to actuate time low for controlling descending PLOAM data;
Descending FIFO reads enable: reading enable generative circuit by descending PLOAM and produce, reading, for reading time high, for being failure to actuate time low for controlling descending PLOAM data from descending FIFO buffer memory;
CPU reads enable: the read control signal of cpu bus, for reading time high, for being failure to actuate time low;
CPU reads address: the address bus of CPU, effective when CPU read signal is high;
The data/address bus of CPU read data: CPU is the descending PLOAM data that CPU reads from descending FIFO;
Interrupt instruction: produced by interruption generative circuit, when descending FIFO buffer memory takes up room the length being greater than or equal to a downstream PLOAM message, produce and interrupt instruction;
Up FIFO remaining space: the remaining space indicating up PLOAM buffer memory, indicates being occupied full of up PLOAM buffer memory when being 0, for complete 1 time indicate up PLOAM buffer memory also there is no store data;
Up FIFO takes up room: indicate taking up room of up PLOAM buffer memory, represents in buffer memory do not have data when being 0, for complete 1 is that instruction buffer memory is occupied full;
Up FIFO writes enable: writing enable generative circuit by up PLOAM and produce, writing up FIFO buffer memory, for writing time high, for being failure to actuate time low for controlling up PLOAM data;
Up FIFO reads enable: reading enable generative circuit by up PLOAM and produce, reading, for reading time high, for being failure to actuate time low for controlling up PLOAM data from up FIFO buffer memory;
CPU writes enable: the write control signal of cpu bus, for writing time high, for being failure to actuate time low;
The address bus of CPU write address: CPU, effective when CPU write signal is high;
CPU writes data: the data/address bus of CPU, for CPU writes the up PLOAM data of up FIFO, effective when write signal is high;
Up PLOAM sends enable: the up PLOAM that the instruction according to OLT generates sends index signal, for sending up PLOAM message time high, for not sending time low;
Up PLOAM data: be parallel data signal are the up PLOAM message that ONU is sent to;
Up PLOAM data enable: indicate the effective index signal of up PLOAM data, for indicating the parallel data signal of up PLOAM effective time high, for indicating the parallel data of up PLOAM invalid time low.
On the basis of technique scheme, the step of downstream PLOAM message handling process is:
When ONU receives the downstream PLOAM message or broadcast PLOAM message that belong to this ONU, first MIC verification is carried out to downstream PLOAM message, the MIC data of 8 bytes calculated and 8 byte datas extracted from downstream PLOAM message are compared, if consistent, this downstream PLOAM message is sent to subsequent treatment module, if comparison is inconsistent, this downstream PLOAM message is abandoned, correct descending PLOAM data are verified for MIC, the cache residual space judging descending FIFO is needed whether enough to deposit this downstream PLOAM message, Rule of judgment is the length whether remaining space of descending FIFO is more than or equal to a frame downstream PLOAM message, if be less than the length of a frame PLOAM message, show that FIFO buffer memory can not deposit this PLOAM message, this downstream PLOAM message does discard processing, if be more than or equal to the length of a frame PLOAM message, show that descending FIFO buffer memory can deposit this PLOAM message, just can this PLOAM message be written in descending FIFO, after writing data in descending FIFO, the buffer memory according to descending FIFO takes up room instruction, when descending FIFO buffer memory takes up room the length being more than or equal to a frame PLOAM message, interruption index signal is set to high notice CPU and can reads downstream PLOAM message, after CPU receives interruption instruction, perform interrupt handling routine, first read the state of descending PLOAM buffer memory, the number of the downstream PLOAM message that acquisition can be read, then according to the number that can read PLOAM message, perform read operation, from downstream PLOAM message buffer memory, read PLOAM data, after read operation completes, clear operation is performed to the interrupt signal of downstream PLOAM message, interruption index signal is set to low.
On the basis of technique scheme, the step of up PLOAM Message Processing flow process is:
After CPU generates up PLOAM message, first the remaining space state of up FIFO buffer memory is read, if the remaining space of up FIFO buffer memory can not fill the complete PLOAM data of next frame, continue to wait for, until the remaining space of up FIFO buffer memory is more than or equal to the length of a frame PLOAM message, if the remaining space of up FIFO buffer memory is more than or equal to the length of a frame PLOAM message, this PLOAM message is written in up FIFO buffer memory, when up PLOAM transmission enable signal is effective, first judge that the buffer memory of up FIFO takes up room and whether be more than or equal to the length of a frame PLOAM message, if buffer memory takes up room be more than or equal to the length of a frame PLOAM message, show in up FIFO buffer memory, to store the complete up PLOAM message of a frame, this up PLOAM message is read, be sent to MIC and verify generation module, the data of PLOAM message after last 8 bytes of removing and the cipher key calculation of PLOAM message is utilized to go out the MIC check byte of 8 bytes, replace last 8 bytes in PLOAM message, then the PLOAM message after replacement is sent, if buffer memory takes up room be less than the length of a frame PLOAM message, the PLOAM message data showing not have a frame complete in up FIFO buffer memory or at all just do not have data, hardware circuit generates a frame null message and is sent to MIC verification generation module, the data of null message of last 8 bytes of removing and the cipher key calculation of PLOAM message is utilized to go out the MIC check byte of 8 bytes, replace last 8 bytes in data in null message, then the null message after replacement is sent.
The method of the PLOAM Message Processing acceleration of XG-PON1 system ONU end of the present invention, hardware circuit is utilized to carry out the partial function of alternative software, and accelerate the speed of software and hardware data interaction, improve the handling property of ONU to PLOAM message, reduce the processing time of PLOAM message, improve the stability of XG-PON1 system.
Accompanying drawing explanation
The present invention has following accompanying drawing:
Fig. 1 is that XG-PON1 system ONU end PLOAM Message Processing of the present invention accelerates block diagram,
Fig. 2 is the process accelerated process figure of ONU end downstream PLOAM message,
Fig. 3 is the process accelerated process figure of the up PLOAM message of ONU end.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The basic procedure of ONU to PLOAM Message Processing is: ONU equipment extracts PLOAM message from downstream data flow, then message integrity check (MIC) verification is carried out to PLOAM message, the PLOAM message of check errors is dropped, the PLOAM message deposit that verification is passed through is to descending PLOAM buffer memory, produce interrupt notification CPU to read, CPU reads the data in descending PLOAM buffer memory, and processes downstream PLOAM message, generates up PLOAM message and is written in up PLOAM buffer memory.When needs send up PLOAM message, sense data from up PLOAM buffer memory, and carry out MIC generate obtain MIC check byte, then sense data and MIC check byte together will be sent in upstream data from up PLOAM buffer memory.
As shown in Figure 1, the method of the PLOAM Message Processing acceleration of XG-PON1 system ONU end of the present invention, what adopt in ONU is to the process of PLOAM Message Processing is that the process of CPU software and hardware handles combine, in Fig. 1, the dotted line left side is CPU software processing part, is hardware handles part on the right of dotted line.
Described hardware handles refers to: achieve MIC School Affairs MIC by hardware handles part and generate, namely the function that substituted for software is generated by the MIC School Affairs MIC in hardware handles part, ONU adopts hardware to complete MIC verification to the downstream PLOAM message received, the up PLOAM message sent for ONU also adopts hardware to generate to complete MIC check byte, MIC School Affairs MIC generates and refers to the AES-CMAC algorithm that G.987.3CLAUSE15.6 ITU-T defines, wherein: downstream PLOAM message refers to that in XG-PON1 system, OLT sends to the PLOAM message of ONU, downstream PLOAM message includes but not limited to that classes of messages model is 0x01, 0x03, 0x04, 0x05, 0x06, 0x09, 0x0A, 0x0D, 9 message such as 0x12, up PLOAM message refers to that in XG-PON1 system, ONU sends to the PLOAM message of OLT, and up PLOAM message includes but not limited to that classes of messages model is 5 message such as 0x01,0x02,0x05,0x09,0x10, the data format of descending and up PLOAM message meets the definition of G.987.3CLAUSE11.2 chapters and sections, comprise No. ID of ONU, No. ID, PLOAM type of message, sequence number, message content, MIC check byte.
On the basis of technique scheme, described hardware handles also comprises: the login state for downstream PLOAM message foundation ONU carries out hardware filtering, and filtering ONU does not need downstream PLOAM message to be processed in this condition.
On the basis of technique scheme, described hardware handles part is provided with descending PLOAM buffer memory and up PLOAM buffer memory, CPU (refers to descending PLOAM buffer memory and up PLOAM buffer memory to PLOAM buffer memory, namely PLOAM message reception buffer memory and send buffer memory) read-write adopt immediated addressing access, to improve the exchanges data speed of CPU and ONU hardware circuit, PLOAM buffer memory adopts fifo fifo to realize.
On the basis of technique scheme, described hardware handles part is PLOAM Message Processing accelerating circuit, specifically comprises: downlink data treatment circuit and upstream data treatment circuit.
Described downlink data treatment circuit comprise interrupt producing circuit and the descending MIC checking circuit connected successively, descending PLOAM filtering circuit, descending PLOAM write enable generative circuit, descending PLOAM buffer circuit, descending PLOAM read enable generative circuit;
Described upstream data treatment circuit comprises that the up PLOAM connected successively writes enable generative circuit, up PLOAM buffer circuit, up PLOAM read enable generative circuit, up MIC generative circuit.
The realizing circuit that the PLOAM Message Processing that the present invention proposes to realize XG-PON1ONU is accelerated, as shown in Figure 1, comprising:
1, for the descending MIC checking circuit of downstream PLOAM message, MIC calculating is carried out to downstream PLOAM message, compare with the MIC byte in downstream PLOAM message.
2, for the descending PLOAM filtering circuit of downstream PLOAM message, the login state of downstream PLOAM message according to ONU is filtered.
3, descending PLOAM writes enable generative circuit, and the write control circuit of descending PLOAM buffer circuit, writes downstream PLOAM message in buffer memory.
4, the interruption for downstream PLOAM message produces circuit, completes the Generation and control of interrupt signal.
5, downstream PLOAM message buffer circuit, completes the storage to downstream PLOAM message.
6, descending PLOAM reads enable generative circuit, reads control circuit for CPU to the direct addressin of downstream PLOAM message.
7, up PLOAM writes enable generative circuit, for the write control circuit of CPU to the direct addressin of up PLOAM message.
8, up PLOAM buffer circuit, completes the storage to up PLOAM message.
9, up PLOAM reads enable generative circuit, up PLOAM buffer circuit read control circuit, up PLOAM message is read from buffer memory.
10, for the up MIC generative circuit of up PLOAM message, the generation completing the MIC byte of up PLOAM message calculates.
On the basis of technique scheme, as shown in Figure 1, hardware handles part process, following signal is produced:
Descending PLOAM data: be parallel data signal are the downlink datas that ONU receives;
Descending PLOAM data enable: the effective index signal of descending PLOAM data, for the parallel data signal of indicating downlink PLOAM time high is effective, for time low, the parallel data of indicating downlink PLOAM is invalid;
Descending FIFO remaining space: the remaining space of indicating downlink PLOAM buffer memory, being occupied full of indicating downlink PLOAM buffer memory when being 0, for complete 1 time indicating downlink PLOAM buffer memory also there is no store data;
Descending FIFO takes up room: taking up room of indicating downlink PLOAM buffer memory, represents in buffer memory do not have data when being 0, for complete 1 is that instruction buffer memory is occupied full;
Descending FIFO writes enable: writing enable generative circuit by descending PLOAM and produce, writing descending FIFO buffer memory, for writing time high, for being failure to actuate time low for controlling descending PLOAM data;
Descending FIFO reads enable: reading enable generative circuit by descending PLOAM and produce, reading, for reading time high, for being failure to actuate time low for controlling descending PLOAM data from descending FIFO buffer memory;
CPU reads enable: the read control signal of cpu bus, for reading time high, for being failure to actuate time low;
CPU reads address: the address bus of CPU, effective when CPU read signal is high;
The data/address bus of CPU read data: CPU is the descending PLOAM data that CPU reads from descending FIFO;
Interrupt instruction: produced by interruption generative circuit, when descending FIFO buffer memory takes up room the length being greater than or equal to a downstream PLOAM message, produce and interrupt instruction;
Up FIFO remaining space: the remaining space indicating up PLOAM buffer memory, indicates being occupied full of up PLOAM buffer memory when being 0, for complete 1 time indicate up PLOAM buffer memory also there is no store data;
Up FIFO takes up room: indicate taking up room of up PLOAM buffer memory, represents in buffer memory do not have data when being 0, for complete 1 is that instruction buffer memory is occupied full;
Up FIFO writes enable: writing enable generative circuit by up PLOAM and produce, writing up FIFO buffer memory, for writing time high, for being failure to actuate time low for controlling up PLOAM data;
Up FIFO reads enable: reading enable generative circuit by up PLOAM and produce, reading, for reading time high, for being failure to actuate time low for controlling up PLOAM data from up FIFO buffer memory;
CPU writes enable: the write control signal of cpu bus, for writing time high, for being failure to actuate time low;
The address bus of CPU write address: CPU, effective when CPU write signal is high;
CPU writes data: the data/address bus of CPU, for CPU writes the up PLOAM data of up FIFO, effective when write signal is high;
Up PLOAM sends enable: the up PLOAM that the instruction according to OLT generates sends index signal, for sending up PLOAM message time high, for not sending time low;
Up PLOAM data: be parallel data signal are the up PLOAM message that ONU is sent to;
Up PLOAM data enable: indicate the effective index signal of up PLOAM data, for indicating the parallel data signal of up PLOAM effective time high, for indicating the parallel data of up PLOAM invalid time low.
On the basis of technique scheme, descending MIC checking circuit completes and verifies the MIC of downstream PLOAM message,
When descending PLOAM data enable signal is effective, judge whether this PLOAM message is the downlink unicast PLOAM message or the multicast PLOAM message that belong to this ONU,
Extract last 8 bytes of this PLOAM message, these 8 bytes are MIC check byte that this PLOAM message carries, and utilize the correct MIC check byte of this PLOAM message of cipher key calculation of this PLOAM message data after removing last 8 bytes and PLOAM message, then the correct MIC check byte calculated and the MIC check byte extracted from PLOAM message is utilized to compare
If consistent, MIC verification is correct, and PLOAM message continues to transmit downwards, if inconsistent, MIC check errors, this PLOAM message does discard processing, and descending PLOAM data enable signal corresponding to these descending PLOAM data is set low, and allows this PLOAM message invalid.
On the basis of technique scheme, descending PLOAM filtering circuit completes the filtering function of the PLOAM message after to MIC verification correctly, and this function has been come by filtering list item, is below the embodiment of a filtering list item.
According to No. ID, the type of message of descending PLOAM, configure this number message at the filtering function of ONU under various login state.Specifically:
When the descending PLOAM data enable signal sent into is effective, extract No. ID, the type of message of downstream PLOAM message, the login state current according to ONU and this number message filtering configuration in this condition, determine that this downstream PLOAM message abandons or continues to transmit rearward; If cross filtering to be configured to 1, this PLOAM message continues to transmit rearward; If filtering is configured to 0, abandon this downstream PLOAM message, PLOAM data enable signal corresponding for these descending PLOAM data is set to low, make this downstream PLOAM message invalid.
Filtering list item is configured according to the login state of ONU, and hardware filtering act of disposition comprises and abandoning or normal process, and the login state of ONU defines the definition met G.987.3CLAUSE12.2.1.
On the basis of technique scheme, descending PLOAM writes the generation that enable generative circuit completes descending PLOAM buffer memory write enable signal, is written to by downstream PLOAM message in descending PLOAM buffer memory,
When the descending PLOAM data enable signal sent into is effective, by the remaining space of descending FIFO, judge whether cache residual space is more than or equal to the length of a PLOAM message,
If remaining space is more than or equal to the length of a PLOAM message, produce write enable signal, be that high downstream PLOAM message data are written in buffer memory by descending for correspondence PLOAM data enable signal, if remaining space is less than the length of a PLOAM message, just this downstream PLOAM message is abandoned.
On the basis of technique scheme, descending PLOAM buffer circuit completes the memory function of descending PLOAM data, and stored by downstream PLOAM message, data read by waiting for CPU from buffer memory.
Such as: descending PLOAM buffer circuit adopts first-in first-out fifo circuit to realize, such as adopt a two-port FIFO, for write port, comprise write data, write enable and write clock, FIFO write enable for high time input data are written in FIFO, for reading port, comprise sense data, read enable and readout clock, FIFO read enable for high time give sense data by the data in FIFO.
On the basis of technique scheme, descending PLOAM reads the generation that enable generative circuit completes descending PLOAM cache read enable signal, is read by downstream PLOAM message from descending PLOAM buffer memory,
When CPU read signal is high, and when CPU reads the address that address equals as the definition of FIFO read port, enable signal will be read and set high, sense data from FIFO, enable signal will be read after running through data and set low.
On the basis of technique scheme, interrupt producing generation and the removing that circuit completes interrupt signal, and interrupt signal be sent to CPU,
When judge descending PLOAM buffer memory take up room the length being more than or equal to a PLOAM message time, interruption index signal is set to height, interrupts the removing of index signal and completed by CPU.
On the basis of technique scheme, up PLOAM writes the generation that enable generative circuit completes PLOAM buffer memory write enable signal, up PLOAM message is written in up PLOAM buffer memory,
When CPU write signal is high, and when CPU write address equals the address of FIFO write port definition, set high by write enable signal, write enable signal is sent to the write port of up PLOAM buffer memory FIFO, after write operation completes, is set low by write enable signal.
On the basis of technique scheme, up PLOAM buffer circuit completes the memory function of up PLOAM data, up PLOAM message stores is got up, and waits for that data read by hardware circuit from buffer memory.
Such as: up PLOAM buffer circuit adopts fifo circuit to realize, such as adopt a two-port FIFO, for write port, comprise write data, write enable and write clock, FIFO write enable for high time input data are written in FIFO, for reading port, comprise sense data, read enable and readout clock, FIFO read enable for high time give sense data by the data in FIFO.
On the basis of technique scheme, up PLOAM reads the generation that enable generative circuit completes up PLOAM cache read enable signal, up PLOAM message is read from up PLOAM buffer memory,
When up PLOAM transmission enable signal is high, judge whether up FIFO space hold is more than or equal to the length of a PLOAM message,
If be more than or equal to the length of a PLOAM message, be set up row FIFO and read enable signal for high, from up PLOAM buffer memory after sense data, up PLOAM data enable signal is set high, indicates these up PLOAM data effective, if judge that up FIFO space hold is less than the length of a PLOAM message, the PLOAM message of a bar null message is generated by hardware circuit, sent by this null message, and up PLOAM data enable signal is set to height, instruction null message data are effective.
On the basis of technique scheme, up MIC generative circuit completes calculating and the replacement of up PLOAM message MIC check byte,
When up PLOAM data enable signal is effective, utilize the up MIC check byte of the PLOAM message data of last 8 bytes of this removal and this PLOAM message of cipher key calculation of PLOAM message, then the MIC check byte calculated is utilized to replace last 8 bytes in up PLOAM message, then the up PLOAM data after byte being replaced and up PLOAM data enable signal are sent, for the transmission of up PLOAM data.
On the basis of technique scheme, described PLOAM Message Processing accelerating circuit completes downstream PLOAM message handling process and up PLOAM Message Processing flow process.
As shown in Figure 2, the step of downstream PLOAM message handling process is:
When ONU receives the downstream PLOAM message or broadcast PLOAM message that belong to this ONU, first MIC verification is carried out to downstream PLOAM message, the MIC data of 8 bytes calculated and 8 byte datas extracted from downstream PLOAM message are compared, if consistent, this downstream PLOAM message is sent to subsequent treatment module, if comparison is inconsistent, this downstream PLOAM message is abandoned, correct descending PLOAM data are verified for MIC, the cache residual space judging descending FIFO is needed whether enough to deposit this downstream PLOAM message, Rule of judgment is the length whether remaining space of descending FIFO is more than or equal to a frame downstream PLOAM message, if be less than the length of a frame PLOAM message, show that FIFO buffer memory can not deposit this PLOAM message, this downstream PLOAM message does discard processing, if be more than or equal to the length of a frame PLOAM message, show that descending FIFO buffer memory can deposit this PLOAM message, just can this PLOAM message be written in descending FIFO, after writing data in descending FIFO, the buffer memory according to descending FIFO takes up room instruction, when descending FIFO buffer memory takes up room the length being more than or equal to a frame PLOAM message, interruption index signal is set to high notice CPU and can reads downstream PLOAM message, after CPU receives interruption instruction, perform interrupt handling routine, first read the state of descending PLOAM buffer memory, the number of the downstream PLOAM message that acquisition can be read, then according to the number that can read PLOAM message, perform read operation, from downstream PLOAM message buffer memory, read PLOAM data, after read operation completes, clear operation is performed to the interrupt signal of downstream PLOAM message, interruption index signal is set to low,
As shown in Figure 3, the step of up PLOAM Message Processing flow process is:
After CPU generates up PLOAM message, first the remaining space state of up FIFO buffer memory is read, if the remaining space of up FIFO buffer memory can not fill the complete PLOAM data of next frame, continue to wait for, until the remaining space of up FIFO buffer memory is more than or equal to the length of a frame PLOAM message, if the remaining space of up FIFO buffer memory is more than or equal to the length of a frame PLOAM message, this PLOAM message is written in up FIFO buffer memory, when up PLOAM transmission enable signal is effective, first judge that the buffer memory of up FIFO takes up room and whether be more than or equal to the length of a frame PLOAM message, if buffer memory takes up room be more than or equal to the length of a frame PLOAM message, show in up FIFO buffer memory, to store the complete up PLOAM message of a frame, this up PLOAM message is read, be sent to MIC and verify generation module, the data of PLOAM message of last 8 bytes of removing and the cipher key calculation of PLOAM message is utilized to go out the MIC check byte of 8 bytes, replace last 8 bytes in PLOAM message, then the PLOAM message after replacement is sent, if buffer memory takes up room be less than the length of a frame PLOAM message, the PLOAM message data showing not have a frame complete in up FIFO buffer memory or at all just do not have data, hardware circuit generates a frame null message and is sent to MIC verification generation module, the data of null message of last 8 bytes of removing and the cipher key calculation of PLOAM message is utilized to go out the MIC check byte of 8 bytes, replace last 8 bytes in data in null message, then the null message after replacement is sent.
The PLOAM Message Processing scheme of the XG-PON1 system ONU that the present invention proposes, has the following advantages:
MIC School Affairs due to PLOAM message generates and adopts hardware implementing, decreases the time that software generates the up MIC verification of downstream PLOAM message MIC School Affairs.In advance downstream PLOAM message is filtered, decrease the workload of software.The write of CPU to the reading of downstream PLOAM message and up PLOAM message all adopts the mode of direct addressin, saves the passing time of PLOAM message between hardware and CPU, greatly reduces ONU like this to the PLOAM Message Processing response time.Invention increases the stability of system, improve the performance of XG-PON1 system.
The content be not described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (7)
- The method of the PLOAM Message Processing acceleration of 1.XG-PON1 system ONU end, it is characterized in that: in optical network unit ONU physical layer operations administered and maintained in the process of PLOAM Message Processing and adopt the process of CPU software and hardware handles to combine, described hardware handles refers to: realize message integrity check MIC School Affairs message integrity check MIC by hardware handles part and generateOptical network unit ONU adopts hardware to verify to complete message integrity check MIC to the down physical layer Operations,Administration And Maintenance PLOAM message received, the upstream physical layer Operations,Administration And Maintenance PLOAM message sent for optical network unit ONU also adopts hardware to generate to complete message integrity check MIC check byte, wherein: down physical layer Operations,Administration And Maintenance PLOAM message refers to that in 10 gigabit passive optical network XG-PON1 systems, optical line terminal OLT sends to the physical layer operations of optical network unit ONU to administer and maintain PLOAM message, upstream physical layer Operations,Administration And Maintenance PLOAM message refers to that in 10 gigabit passive optical network XG-PON1 systems, optical network unit ONU sends to the physical layer operations of optical line terminal OLT to administer and maintain PLOAM message,Descending and data format that is upstream physical layer Operations,Administration And Maintenance PLOAM message meets the definition of G.987.3CLAUSE 11.2 chapters and sections, comprises No. ID of optical network unit ONU, physical layer operations administers and maintains No. ID, PLOAM type of message, sequence number, message content, message integrity check MIC check byte.
- 2. the method for the PLOAM Message Processing acceleration of XG-PON1 system ONU end as claimed in claim 1, it is characterized in that, described hardware handles also comprises: the login state for downstream PLOAM message foundation ONU carries out hardware filtering, and filtering ONU does not need downstream PLOAM message to be processed in this condition.
- 3. the method for the PLOAM Message Processing acceleration of XG-PON1 system ONU end as claimed in claim 1, it is characterized in that: described hardware handles part is provided with descending PLOAM buffer memory and up PLOAM buffer memory, CPU adopts immediated addressing access to the read-write of PLOAM buffer memory, and PLOAM buffer memory adopts fifo fifo to realize.
- 4. the method for the PLOAM Message Processing acceleration of XG-PON1 system ONU end as claimed in claim 1, is characterized in that: described hardware handles part is PLOAM Message Processing accelerating circuit, specifically comprises downlink data treatment circuit and upstream data treatment circuit; Described PLOAM Message Processing accelerating circuit completes downstream PLOAM message handling process and up PLOAM Message Processing flow process;Described downlink data treatment circuit comprise interrupt producing circuit and the descending MIC checking circuit connected successively, descending PLOAM filtering circuit, descending PLOAM write enable generative circuit, descending PLOAM buffer circuit, descending PLOAM read enable generative circuit;Described upstream data treatment circuit comprises that the up PLOAM connected successively writes enable generative circuit, up PLOAM buffer circuit, up PLOAM read enable generative circuit, up MIC generative circuit.
- 5. the method accelerated of the PLOAM Message Processing of XG-PON1 system ONU end as claimed in claim 4, is characterized in that, the process of hardware handles part, produces following signal:Descending PLOAM data: be parallel data signal are the downlink datas that ONU receives;Descending PLOAM data enable: the effective index signal of descending PLOAM data, for the parallel data signal of indicating downlink PLOAM time high is effective, for time low, the parallel data of indicating downlink PLOAM is invalid;Descending FIFO remaining space: the remaining space of indicating downlink PLOAM buffer memory, being occupied full of indicating downlink PLOAM buffer memory when being 0, for complete 1 time indicating downlink PLOAM buffer memory also there is no store data;Descending FIFO takes up room: taking up room of indicating downlink PLOAM buffer memory, represents in buffer memory do not have data when being 0, for complete 1 is that instruction buffer memory is occupied full;Descending FIFO writes enable: writing enable generative circuit by descending PLOAM and produce, writing descending FIFO buffer memory, for writing time high, for being failure to actuate time low for controlling descending PLOAM data;Descending FIFO reads enable: reading enable generative circuit by descending PLOAM and produce, reading, for reading time high, for being failure to actuate time low for controlling descending PLOAM data from descending FIFO buffer memory;CPU reads enable: the read control signal of cpu bus, for reading time high, for being failure to actuate time low;CPU reads address: the address bus of CPU, effective when CPU read signal is high;The data/address bus of CPU read data: CPU is the descending PLOAM data that CPU reads from descending FIFO;Interrupt instruction: produced by interruption generative circuit, when descending FIFO buffer memory takes up room the length being greater than or equal to a downstream PLOAM message, produce and interrupt instruction;Up FIFO remaining space: the remaining space indicating up PLOAM buffer memory, indicates being occupied full of up PLOAM buffer memory when being 0, for complete 1 time indicate up PLOAM buffer memory also there is no store data;Up FIFO takes up room: indicate taking up room of up PLOAM buffer memory, represents in buffer memory do not have data when being 0, for complete 1 is that instruction buffer memory is occupied full;Up FIFO writes enable: writing enable generative circuit by up PLOAM and produce, writing up FIFO buffer memory, for writing time high, for being failure to actuate time low for controlling up PLOAM data;Up FIFO reads enable: reading enable generative circuit by up PLOAM and produce, reading, for reading time high, for being failure to actuate time low for controlling up PLOAM data from up FIFO buffer memory;CPU writes enable: the write control signal of cpu bus, for writing time high, for being failure to actuate time low;The address bus of CPU write address: CPU, effective when CPU write signal is high;CPU writes data: the data/address bus of CPU, for CPU writes the up PLOAM data of up FIFO, effective when write signal is high;Up PLOAM sends enable: the up PLOAM that the instruction according to OLT generates sends index signal, for sending up PLOAM message time high, for not sending time low;Up PLOAM data: be parallel data signal are the up PLOAM message that ONU is sent to;Up PLOAM data enable: indicate the effective index signal of up PLOAM data, for indicating the parallel data signal of up PLOAM effective time high, for indicating the parallel data of up PLOAM invalid time low.
- 6. the method for the PLOAM Message Processing acceleration of XG-PON1 system ONU end as claimed in claim 5, it is characterized in that, the step of downstream PLOAM message handling process is:When ONU receives the downstream PLOAM message or broadcast PLOAM message that belong to this ONU, first MIC verification is carried out to downstream PLOAM message, the MIC data of 8 bytes calculated and 8 byte datas extracted from downstream PLOAM message are compared, if consistent, this downstream PLOAM message is sent to subsequent treatment module, if comparison is inconsistent, this downstream PLOAM message is abandoned, correct descending PLOAM data are verified for MIC, the cache residual space judging descending FIFO is needed whether enough to deposit this downstream PLOAM message, Rule of judgment is the length whether remaining space of descending FIFO is more than or equal to a frame downstream PLOAM message, if be less than the length of a frame PLOAM message, show that FIFO buffer memory can not deposit this PLOAM message, this downstream PLOAM message does discard processing, if be more than or equal to the length of a frame PLOAM message, show that descending FIFO buffer memory can deposit this PLOAM message, just can this PLOAM message be written in descending FIFO, after writing data in descending FIFO, the buffer memory according to descending FIFO takes up room instruction, when descending FIFO buffer memory takes up room the length being more than or equal to a frame PLOAM message, interruption index signal is set to high notice CPU and can reads downstream PLOAM message, after CPU receives interruption instruction, perform interrupt handling routine, first read the state of descending PLOAM buffer memory, the number of the downstream PLOAM message that acquisition can be read, then according to the number that can read PLOAM message, perform read operation, from downstream PLOAM message buffer memory, read PLOAM data, after read operation completes, clear operation is performed to the interrupt signal of downstream PLOAM message, interruption index signal is set to low.
- 7. the method for the PLOAM Message Processing acceleration of XG-PON1 system ONU end as claimed in claim 5, it is characterized in that, the step of up PLOAM Message Processing flow process is:After CPU generates up PLOAM message, first the remaining space state of up FIFO buffer memory is read, if the remaining space of up FIFO buffer memory can not fill the complete PLOAM data of next frame, continue to wait for, until the remaining space of up FIFO buffer memory is more than or equal to the length of a frame PLOAM message, if the remaining space of up FIFO buffer memory is more than or equal to the length of a frame PLOAM message, this PLOAM message is written in up FIFO buffer memory, when up PLOAM transmission enable signal is effective, first judge that the buffer memory of up FIFO takes up room and whether be more than or equal to the length of a frame PLOAM message, if buffer memory takes up room be more than or equal to the length of a frame PLOAM message, show in up FIFO buffer memory, to store the complete up PLOAM message of a frame, this up PLOAM message is read, be sent to MIC and verify generation module, the data of PLOAM message after last 8 bytes of removing and the cipher key calculation of PLOAM message is utilized to go out the MIC check byte of 8 bytes, replace last 8 bytes in PLOAM message, then the PLOAM message after replacement is sent, if buffer memory takes up room be less than the length of a frame PLOAM message, the PLOAM message data showing not have a frame complete in up FIFO buffer memory or at all just do not have data, hardware circuit generates a frame null message and is sent to MIC verification generation module, the data of null message of last 8 bytes of removing and the cipher key calculation of PLOAM message is utilized to go out the MIC check byte of 8 bytes, replace last 8 bytes in data in null message, then the null message after replacement is sent.
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