CN103117215A - Forming method of metallic gate electrode layer - Google Patents
Forming method of metallic gate electrode layer Download PDFInfo
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- CN103117215A CN103117215A CN2011103661021A CN201110366102A CN103117215A CN 103117215 A CN103117215 A CN 103117215A CN 2011103661021 A CN2011103661021 A CN 2011103661021A CN 201110366102 A CN201110366102 A CN 201110366102A CN 103117215 A CN103117215 A CN 103117215A
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Abstract
A forming method of a metallic gate electrode layer comprises the steps: providing a substrate, wherein a polycrystalline silicon pseudo gate electrode layer and side walls on both sides of the polycrystalline silicon pseudo gate electrode layer are arranged on the surface of the substrate; forming an etch barrier layer on the surface of the substrate, wherein the etch barrier layer is used for covering the polycrystalline silicon pseudo gate electrode layer and the side walls; forming an interlayer dielectric layer on the surface of the etch barrier layer; flattening the interlayer dielectric layer and the etch barrier layer until the polycrystalline silicon pseudo gate electrode layer is exposed; removing the polycrystalline silicon pseudo gate electrode layer, forming an opening, and forming protrusions on the side wall of the top of the opening; forming protective layers on the surfaces of the interlayer dielectric layer and the etch barrier layer, and filling the opening with the protective layers; flattening the protective layers, the interlayer dielectric layer, the etch barrier layer and the side walls with a certain thickness until the protrusions are removed; and removing the protective layers. The metallic gate electrode layer which is formed through the forming method of the metallic gate electrode layer is high in quality.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of metal gate electrode layer.
Background technology
Along with integrated, the microminiaturized development of semiconductor device, the employing material is that the problems such as electrical leakage quantity increase and gate electrode layer loss have appearred in the MOS device of the gate dielectric layer of silicon dioxide and the gate electrode layer that material is polysilicon; For solving the above problems, (be called for short high-K metal gate, HKMG) technique becomes the focus of present research for the dielectric layer of hafnium and the gate electrode layer of metal material.
The formation technique of high-K metal gate can be divided into two kinds of " front grid " technique, " rear grid " techniques.Rear grid technique be owing to can avoid metal gate electrode layer through high annealing, and premium properties that can retainer member is the comparatively main method that forms at present metal gate, and the rear grid technique of the formation technique of high-K metal gate is specially:
At first, provide substrate, described substrate surface has the polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides;
Secondly, form at described substrate surface the etching barrier layer that covers described polysilicon dummy gate layer and side wall;
Afterwards, at described etching barrier layer surface formation interlayer dielectric layer;
Adopt the described interlayer dielectric layer of flatening process planarization and etching barrier layer until expose described polysilicon dummy gate layer;
Remove described polysilicon dummy gate layer, form opening;
Form the high K dielectric layer in described open bottom, fill the metal gate electrode layer of described opening in the surface formation of described high K dielectric layer.
In being the U.S. patent documents of US2010/0081262 A1, publication number can also find the formation technique of more HKMG.
Yet the device that makes according to existing technique is in described high K dielectric layer surface forms the processing step of the metal gate electrode layer of filling described opening, but easily form the space in metal gate electrode layer, cause performance of semiconductor device to reduce, power consumption increases, and reliability reduces.
Summary of the invention
The present invention is utilizing during prior art makes the process of high-K metal gate in order to solve, interstitial problem in metal gate electrode layer.
For addressing the above problem, the embodiment of the present invention provides a kind of method of removing space in metal gate electrode layer, comprising: substrate is provided, and described substrate surface has the polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer that covers described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer; The described interlayer dielectric layer of planarization and etching barrier layer are until expose described polysilicon dummy gate layer; Remove described polysilicon dummy gate layer, form opening, and form projection at the sidewall of described open top; At described interlayer dielectric layer and etching barrier layer surface formation protective layer, described protective layer is filled full described opening; The described protective layer of planarization segment thickness, described interlayer dielectric layer, etching barrier layer and side wall are until remove projection; Remove described protective layer.
Optionally, described protective layer material is photoresist.
Optionally, when described protective layer material was photoresist, the formation technique of described protective layer was: thickness is 400 dusts～1500 dusts, and the speed of spin coating is 300-4000 rev/min, and the temperature of spin coating is 15-100 ℃.
Optionally, the technique of planarization removal projection is the second CMP (Chemical Mechanical Polishing) process.
Optionally, the parameter of CMP (Chemical Mechanical Polishing) process is: the lapping liquid of employing is that silica or cerium oxide are main component, wherein, the particle size of silica lapping liquid is 1～100nm, the particle size of cerium oxide abrasive liquid is 10～20nm, and the lapping liquid of described the second chemico-mechanical polishing is selected than being 0.5～2 the planarization speed of silica and silicon nitride.
Optionally, the technique of the described interlayer dielectric layer of planarization and etching barrier layer is the first CMP (Chemical Mechanical Polishing) process.
Optionally, the parameter of the first CMP (Chemical Mechanical Polishing) process is: the lapping liquid of employing is that silica or cerium oxide are main component, wherein, the particle size of silica lapping liquid is 1～100nm, the particle size of cerium oxide abrasive liquid is 10～20nm, and the lapping liquid of described the first chemico-mechanical polishing selects ratio greater than 1 to the planarization speed of silica and silicon nitride.
Optionally, the technique of the described protective layer of removal is dry method ashing method or wet method ashing method.
Optionally, also comprise: form gate dielectric layer in the bottom of described opening and be positioned at the gate dielectric layer surface and fill the completely metal level of described opening.
Optionally, described gate dielectric layer material is silica or high K medium, and high K medium comprises zirconia, hafnium oxide etc.
Optionally, metal level is single coating or multiple-level stack structure.
Optionally, when described metal level was single coating, described metal layer material was aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, titanium tungsten, nickel platinum, titanium nitride, nitrogenize thallium or tantalum nitride.
Optionally, when described metal level was the multiple-level stack structure, described metal level comprised: be positioned at the function metal level on described gate dielectric layer surface, be positioned at the aluminum metal layer of described function layer on surface of metal.
Optionally, described function metal layer material is titanium nitride, nitrogenize thallium or tantalum nitride.
Compared with prior art, the present invention has the following advantages:
The polysilicon projection that adopts surface with chemical polishing technology for the second time to remove to be formed on described open top madial wall makes follow-uply can not form the space when forming described metal gate electrode layer in described opening; The present embodiment is also before removing the polysilicon projection; adopt protective layer to fill full described opening; avoid in the technique of this chemico-mechanical polishing for the second time with removal oxidation polysilicon projection; the extra madial wall at opening forms other projections or residue again, improves the quality of the described metal level gate electrode layer of follow-up filling.
Further, described protective layer material is photoresist, effectively when protective opening, removes easy and can not damage the interface of opening.
Description of drawings
Fig. 1 to Fig. 4 is the cross-sectional view that existing technique forms high-K metal gate;
Fig. 5 is the process flow diagram that one embodiment of the invention forms metal gate;
Fig. 6 to Figure 12 is the cross-sectional view of the formation procedure of one embodiment of the invention metal gate electrode layer.
Embodiment
The inventor finds, in the formation technique of existing high-K metal gate, in described high-K gate dielectric layer surface forms the processing step of the metal gate electrode layer of filling described opening, easily form the space in metal gate electrode layer, cause performance of semiconductor device to reduce, power consumption increases, and reliability reduces.
The inventor finds after further research, and high-K metal gate technique comprises the steps:
Please refer to Fig. 1, substrate 100 is provided, described substrate 100 surfaces have polysilicon dummy gate layer 101 and are positioned at the side wall 102 of polysilicon dummy gate layer 101 both sides; Described substrate 100 surfaces are formed with the etching barrier layer 103 that covers described polysilicon dummy gate layer 101 and side wall 102, and described etching barrier layer 103 is silicon nitride; Described etching barrier layer 103 surfaces are formed with interlayer dielectric layer 104, and described interlayer dielectric layer is silica;
Please refer to Fig. 2, adopt the described interlayer dielectric layer 104 of flatening process planarization and etching barrier layer 103 until expose described polysilicon dummy gate layer 101, described flatening process is CMP (Chemical Mechanical Polishing) process;
Please refer to Fig. 3, remove described polysilicon dummy gate layer 101, form opening 105; Described removal technique is dry etching or wet etching, because the top of described opening 105 is the handing-over interface of described polysilicon dummy gate layer 101, side wall 102 and etching barrier layer 103; When adopting dry etching or wet etching to remove described polysilicon dummy gate layer 101, easily form polysilicon at described interface location and pile up, the sidewall at the top of described opening 105 can form through snperoxiaized polysilicon projection 106;
Please refer to Fig. 4, at described opening 105 bottoms formation high K dielectric layers 107, fill the metal gate electrode layer 108 of described openings 105 in described high K dielectric layer 106 surface formation; Need to prove, when forming the metal gate electrode layer 108 of filling described opening 105, described metal gate electrode layer 108 is interior space 109 can occur usually.
The inventor furthers investigate discovery, described in metal gate electrode layer interstitial reason be: existing technique is after removing described polysilicon dummy gate layer and forming opening, and the madial wall at the top of described opening can form oxidation polysilicon projection 106; Thereby the top that makes opening becomes narrow, when the following adopted metal deposition process forms the metal gate electrode layer of filling described opening, very fast at the position fill rate with projection, make do not fill fully in opening and have the projection the position sealed, thereby in the inner space that forms of metal gate electrode layer, cause performance of semiconductor device to reduce, power consumption increases, and reliability reduces.
For this reason, the present inventor provides a kind of formation method of metal gate electrode layer, please refer to Fig. 5, comprises the steps:
Step S101 provides substrate, and described substrate surface has the polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer that covers described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer;
Step S102, the described interlayer dielectric layer of planarization and etching barrier layer are until expose described polysilicon dummy gate layer;
Step S103 removes described polysilicon dummy gate layer, forms opening, and forms projection at the madial wall of described open top;
Step S104, at described interlayer dielectric layer and etching barrier layer surface formation protective layer, described protective layer is filled full described opening;
Step S105, the described protective layer of planarization segment thickness, described interlayer dielectric layer, etching barrier layer and side wall are until remove projection;
Step S106 removes described protective layer;
Step S107 forms gate dielectric layer in the bottom of described opening and is positioned at the gate dielectric layer surface and fills the completely metal gate electrode layer of described opening.
Embodiments of the invention adopt flatening process to remove the projection of the sidewall that is formed on described open top; avoid being formed with the space in the metal level that subsequent technique is filled; further; the present invention first forms the protective layer of filling full described opening; described protective layer can avoid removing in planarization that in crowing technique, the extra sidewall at opening forms projection; the semiconductor device metal layer inside of adopting that the embodiment of the present invention forms does not have the space; the device performance that forms improves; power consumption reduces, and reliability improves.
Below in conjunction with specific embodiment, the formation method of the metal gate electrode layer of the embodiment of the present invention is done specific descriptions.
Please refer to Fig. 6, substrate 200 is provided, described substrate 200 surfaces have polysilicon dummy gate layer 201 and are positioned at the side wall 202 of polysilicon dummy gate layer 201 both sides; Described substrate 200 surfaces are formed with the etching barrier layer 203 that covers described polysilicon dummy gate layer 201 and side wall 202; Described etching barrier layer 203 surfaces are formed with interlayer dielectric layer 204.
Described substrate 200 effects are for follow-up formation semiconductor device provides workbench, and described substrate 200 materials are the III-V compounds of group such as silicon (SOI) substrate, silicon nitride substrate and GaAs on N-shaped silicon substrate, p-type silicon substrate, insulating barrier etc.
The material of described etching barrier layer 203 is silicon nitride, described interlayer dielectric layer 204 be silicon oxide layer.
The concrete formation technique of described substrate 200, polysilicon dummy gate layer 201, side wall 202, etching barrier layer 203, interlayer dielectric layer 204 please refer to prior art, here repeats no more.
Please refer to Fig. 7, the described interlayer dielectric layer 204 of planarization and etching barrier layer 203 are until expose described polysilicon dummy gate layer 201.
The technique of described planarization is the first CMP (Chemical Mechanical Polishing) process, particularly, described the first CMP (Chemical Mechanical Polishing) process parameter is: the lapping liquid that chemico-mechanical polishing is adopted is take silica or cerium oxide as main component, and described lapping liquid is selected than greater than 1 the planarization speed of silica and silicon nitride.
Need to prove, the particle size of described silica lapping liquid is 1～100nm, adopts the advantage of silica lapping liquid to be: abrasive grains good dispersion, active, the rear cleaning process of chemical property are easy to advantage.
It should be noted that, the particle size of described cerium oxide abrasive liquid is 10～20nm, adopts the advantage of cerium oxide abrasive liquid to be: have advantages of that polishing speed is high, the clearance of material is high, less to the damage on polished surface.
Also need to prove, in the present embodiment, the material of interlayer dielectric layer 204 is that silica, etching barrier layer 203 is silicon nitride, the lapping liquid of selecting the first chemico-mechanical polishing to the selection of silica and silicon nitride than can guarantee that greater than 1 technological parameter the silicon nitride etch barrier layer 203 higher than the polysilicon dummy gate layer is removed together with silica interlayer dielectric layer 204.
Please refer to Fig. 8, remove described polysilicon dummy gate layer 201, form opening 205, and form projection 206 at the madial wall at described opening 205 tops.
The described technique of removing projection 206 is dry etching or wet etching.
In one embodiment, described dry etching method adopts the reactive ion etching method, and the gas of employing can be selected the mixture of chlorine, helium, hydrogen bromide or helium and oxygen.Adopt the advantage of dry etching to be, anisotropy, selectivity is good and etching efficient is high.
In another embodiment, described wet etching is selected tetramethyl ammonium hydroxide solution, and mass percent concentration is 2～4%, and temperature is 50 ℃～90 ℃, and etch rate is 100～3000 A/mins of clocks, and the speed ratio of etch polysilicon and silica was greater than 100: 1; The advantage that adopts wet etching be easy and simple to handle, low for equipment requirements, be easy to produce in enormous quantities.
The oxide that described protruding 206 materials are polysilicons, particularly, the reason of described protruding 206 formation is: described opening 205 tops are the interface location of described polysilicon dummy gate layer 201, side wall 202 and etching barrier layer 203, when adopting dry etching or wet etching to remove described polysilicon dummy gate layer 101, easily forming polysilicon at described interface location piles up, remaining polysilicon is exposed in air or can be oxidized, and the madial wall at opening 205 tops forms oxidized polysilicon projection 206.
Please refer to Fig. 9, at described interlayer dielectric layer 204 and etching barrier layer 203 surface formation protective layers 207, described protective layer 207 is filled full described openings 205.
Described protective layer 204 is used for removing in subsequent planarization processing step protective opening 205 madial walls of projection 206, avoids forming extra residual packing at the sidewall of opening 205, makes the open top size decreases.
The material photoresist of described protective layer 207; particularly; the concrete technology parameter that applies photoresist is: thickness is 400 dusts～1500 dusts, and the speed of spin coating is 300-4000 rev/min, and the temperature of spin coating is 15-100 ℃; photoresist has advantages of as follows as protective layer: be easy to film forming; be easy to remove, easy to use, corrosion stability is good; adhesiveness is high, can fully fill described opening 205 plays a protective role, and can not cause the infringement at opening interface.
Please refer to Figure 10, the described protective layer 207 of planarization segment thickness, described interlayer dielectric layer 204, etching barrier layer 203 and side wall 202 are until remove projection 206.
The technique that projection 206 is removed in described planarization is the second CMP (Chemical Mechanical Polishing) process, particularly, the technological parameter of described the second chemico-mechanical polishing is: the lapping liquid that chemico-mechanical polishing is adopted is take silica or cerium oxide as main component, particularly, silica lapping liquid particle size is 1～100nm, the particle size of cerium oxide abrasive liquid is 10～20nm, and the lapping liquid of described the second chemico-mechanical polishing is selected than being 0.5～2 the planarization speed of silica and silicon nitride.Adopt the second above-mentioned CMP (Chemical Mechanical Polishing) process parameter, in conjunction with the protective layer of photoresist, can effectively remove projection and can additionally not form other residue at opening sidewalls.
In the present embodiment, adopt surface with chemical polishing technology for the second time to remove the polysilicon projection 206 that is formed on described opening 205 inside top walls, with the inner spaces that form of the metal gate dielectric layer as shown in figure 12 209 of avoiding filling at subsequent technique.Further; in the present embodiment; the previous photoresist protective layer 207 of filling full described opening 205 that forms can be avoided in the technique of this chemico-mechanical polishing for the second time with removal oxidation polysilicon projection 206, and the extra madial wall at opening forms projection 206 again.
Please refer to Figure 11, remove described protective layer 207;
The effect of described removal protective layer 207 techniques is to form the opening 205 that top width increases, and the filling of the metal gate electrode layer as shown in figure 12 209 after making can not form space 109 as shown in Figure 4.
In one embodiment, when the material of protective layer 207 is photoresist, described removal technique is dry method ashing method or wet method ashing method, particularly, the gas that described dry method ashing method adopts can be, the advantage that one or more in inert gas, air, nitrogen, oxygen, fluorocarbon gases and hydrocarbon gas, dry method remove photoresist be simple to operate, the efficient of removing photoresist is high, surface clean is bright and clean; Particularly, the solvent that removes photoresist of described wet method ashing method can be the mixed liquor of sulfuric acid and hydrogen peroxide, and the advantage that wet method is removed photoresist is that cost is low, output is high.
In another embodiment, when protective layer 207 materials were silicon dioxide, described removal technique was coagulation desiliconization method, comprised magnesia mixture desiliconization, the desiliconization of aluminium salt, molysite desiliconization and lime desiliconization.
Please refer to Figure 12, form gate dielectric layer 208 in the bottom of described opening 205 and be positioned at gate dielectric layer 208 surfaces and fill the completely metal gate electrode layer 209 of described opening 205.
Described gate dielectric layer 208 is the appearance that prevents leaky for the effect of high-K gate dielectric layer.
The material of described high-K gate dielectric layer 208 is hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc, and the formation technique of described high-K gate dielectric layer 208 can be chemical vapour deposition technique or physical vapour deposition (PVD).
Described metal gate electrode layer 209 can be single coating or multiple-level stack structure.
In one embodiment, when described metal gate electrode layer 209 was single coating, described metal layer material was aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, titanium tungsten, nickel platinum, titanium nitride, nitrogenize thallium or tantalum nitride.
In another embodiment, when described metal gate electrode layer 209 is the multiple-level stack structure, described metal level comprises: the function metal level that is positioned at described gate dielectric layer 208 surfaces, be positioned at the aluminum metal layer of described function layer on surface of metal, particularly, the effect of described function metal level is to gather in opening 205 sidewall surfaces in the forming process of aluminum metal layer after preventing to cause opening to narrow down, and the material of described function metal level is titanium nitride, nitrogenize thallium or tantalum nitride.
The formation technique of described metal gate electrode layer 209 is chemical vapour deposition (CVD) or physical vapour deposition (PVD), particularly, the formation step of described metal level 209 is: form described high-K gate dielectric layer in opening 205 bottom depositions, on the high-K gate dielectric layer surface and opening 205 madial walls form described function metal level, form aluminum metal layer at described function layer on surface of metal at last.
The advantage of embodiments of the invention is to adopt surface with chemical polishing technology removal for the second time to be formed on the polysilicon projection 206 of described opening 205 inside top walls, makes the follow-up space 109 that can not form when the described metal gate electrode layer 209 of the interior formation of described opening 205 as shown in Figure 4; The present embodiment is also before removing polysilicon projection 206; adopt protective layer 207 to fill full described opening 205; avoid in the technique of this chemico-mechanical polishing for the second time with removal oxidation polysilicon projection 206; the extra madial wall at opening forms other projections or residue again, improves the quality of the described metal level gate electrode layer 209 of follow-up filling.
Further, described protective layer 207 materials are photoresist, effectively when protective opening, remove easy and can not damage the interface of opening 205.
Though the embodiment of the present invention as mentioned above, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (14)
1. the formation method of a metal gate electrode layer, is characterized in that, comprising:
Substrate is provided, and described substrate surface has the polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer that covers described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer;
The described interlayer dielectric layer of planarization and etching barrier layer are until expose described polysilicon dummy gate layer;
Remove described polysilicon dummy gate layer, form opening, and form projection at the sidewall of described open top;
At described interlayer dielectric layer and etching barrier layer surface formation protective layer, described protective layer is filled full described opening;
The described protective layer of planarization segment thickness, described interlayer dielectric layer, etching barrier layer and side wall are until remove projection;
Remove described protective layer.
2. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, described protective layer material is photoresist.
3. the formation method of metal gate electrode layer as claimed in claim 1; it is characterized in that, when described protective layer material was photoresist, the formation technique of described protective layer was: thickness is 400 dusts～1500 dusts; the speed of spin coating is 300-4000 rev/min, and the temperature of spin coating is 15-100 ℃.
4. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, the technique that projection is removed in planarization is the second CMP (Chemical Mechanical Polishing) process.
5. the formation method of metal gate electrode layer as claimed in claim 4, it is characterized in that, the parameter of CMP (Chemical Mechanical Polishing) process is: the lapping liquid of employing is that silica or cerium oxide are main component, wherein, the particle size of silica lapping liquid is 1～100nm, the particle size of cerium oxide abrasive liquid is 10～20nm, and the lapping liquid of described the second chemico-mechanical polishing is selected than being 0.5～2 the planarization speed of silica and silicon nitride.
6. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, the technique of the described interlayer dielectric layer of planarization and etching barrier layer is the first CMP (Chemical Mechanical Polishing) process.
7. the formation method of metal gate electrode layer as claimed in claim 6, it is characterized in that, the technological parameter of the first chemico-mechanical polishing is: the lapping liquid that chemico-mechanical polishing is adopted is take silica or cerium oxide as main component, wherein, the particle size of silica lapping liquid is 1～100nm, the particle size of cerium oxide abrasive liquid is 10～20nm, and the lapping liquid of described the first chemico-mechanical polishing selects ratio greater than 1 to the planarization speed of silica and silicon nitride.
8. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, the technique of removing described protective layer is dry method ashing method or wet method ashing method.
9. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, also comprises: form gate dielectric layer in the bottom of described opening and be positioned at the gate dielectric layer surface and fill the completely metal level of described opening.
10. the formation method of metal gate electrode layer as claimed in claim 9, is characterized in that, described gate dielectric layer material is silica or high K medium, and high K medium comprises zirconia, hafnium oxide etc.
11. the formation method of metal gate electrode layer as claimed in claim 9 is characterized in that, metal level is single coating or multiple-level stack structure.
12. the formation method of metal gate electrode layer as claimed in claim 11, it is characterized in that, when described metal level was single coating, described metal layer material was aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, titanium tungsten, nickel platinum, titanium nitride, nitrogenize thallium or tantalum nitride.
13. the formation method of metal gate electrode layer as claimed in claim 11, it is characterized in that, when described metal level was the multiple-level stack structure, described metal level comprised: be positioned at the function metal level on described gate dielectric layer surface, be positioned at the aluminum metal layer of described function layer on surface of metal.
14. the formation method of metal gate electrode layer as claimed in claim 13 is characterized in that, described function metal layer material is titanium nitride, nitrogenize thallium or tantalum nitride.
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| CN104681421A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Method for improving wet-process etching efficiency |
| CN109686782A (en) * | 2018-12-18 | 2019-04-26 | 吉林华微电子股份有限公司 | Semiconductor devices and preparation method thereof |
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| CN104112657A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | MOS device manufacturing method |
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| CN104681421A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Method for improving wet-process etching efficiency |
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| CN109686782A (en) * | 2018-12-18 | 2019-04-26 | 吉林华微电子股份有限公司 | Semiconductor devices and preparation method thereof |
| CN109686782B (en) * | 2018-12-18 | 2021-11-12 | 吉林华微电子股份有限公司 | Semiconductor device and method for manufacturing the same |
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