CN103116566A - Dual-core communication device by means of mail receive-and-send box - Google Patents
Dual-core communication device by means of mail receive-and-send box Download PDFInfo
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- CN103116566A CN103116566A CN2013100179286A CN201310017928A CN103116566A CN 103116566 A CN103116566 A CN 103116566A CN 2013100179286 A CN2013100179286 A CN 2013100179286A CN 201310017928 A CN201310017928 A CN 201310017928A CN 103116566 A CN103116566 A CN 103116566A
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Abstract
The invention discloses a dual-core communication device by means of a mail receive-and-send box. The dual-core communication device by means of the mail receive-and-send box comprises a processor module, a bus module, a mail receive-and-send module and an interrupt processing module. In operation mode, the processor module is used for receiving and sending instructions and data and processing the instructions and the data, the bus module is used for transmitting the data and the instructions among the modules, the mail receive-and-send box module is used for temporally storing mails sent by the processor module in order to facilitate instruction and data exchange between different processors, and the interruption processing module is used for waking up a certain processor and enabling the processor to enter a dual-core communication mode and to read mails in the mail receive-and-send box module. The device achieves and optimizes a dual-core communication function, guarantees that data do not mixed with other foreign data, and guarantees high efficiency and effectiveness of communication.
Description
Technical field
The invention belongs to microelectronics technology, relate to a kind of double-core SOC technology, particularly relate to the SOC chip that a kind of internal processor can be communicated by letter mutually.
Background technology
Fast development along with integrated circuit technique, with panel computer, smart mobile phone is that the electronic consumer products of representative is universal fast, ultra-large SOC (system on a chip) (System on Chip based on deep-submicron, SOC) technology has become one of gordian technique that 21 century attracts most attention, and the user requires more and more higher to the properties of this series products.Many past must be at the upper complex task of processing of power PC (Personal Computer), such as Email, web page browsing, shooting take pictures, the application function such as media play can carry out on mobile terminal.At present, high-performance SoC product emerges in an endless stream on market, and the double-core product is also the acts that are unequal to more, and what great majority were taked is to share fixed memory unit to carry out communication, coordinates to complete various operations.
Summary of the invention
Technical matters: the objective of the invention is to be the deficiency for existing double-core communication chip, propose a kind of communication that can carry out between double-core, and the mail transmission/reception case that utilizes that has higher efficient when double-core is communicated by letter is realized the device of communicating by letter between double-core.
Technical scheme: the mail transmission/reception case that utilizes of the present invention is realized the device of communicating by letter between double-core, comprises processor module, bus module, mail transmission/reception tank module and interruption processing module;
Processor module is used for receiving and sending instruction and data and instruction and data are processed in mode of operation;
Bus module is used for the data command transmission between modules;
The mail transmission/reception tank module is used for temporary storage from the mail that processor module sends out, and is convenient to the director data exchange between different processor;
Interruption processing module is responsible for waking up certain processor, makes it enter the double-core communication pattern and reads mail in the mail transmission/reception tank module.
In the present invention, the mail transmission/reception tank module comprises two independent mail transmission/reception casees, and mail from any one processor module is accepted and stored to each mail transmission/reception case, and each processor module carries out mail by bus module to the mail transmission/reception case and reads; Mail in the mail transmission/reception case is divided into mail head and Mail Contents, and the mail head sends the action type of data representative for processor module, and Mail Contents is the content of operation of current operation.
In the present invention, processor module comprises two processors that can work independently, processor is controlled the work of other modules, and each processor has a corresponding mail transmission/reception case with it, and processor can form data encoding in mail and send to the mail transmission/reception case.
In the present invention, bus module is the coupling arrangement of all modules, and it follows advanced microcontroller bus architecture bus specification.
In the present invention, interruption processing module comprises a vectorial interrupt handler, the vector interrupt handler is controlled the purpose processor by the mode that sends soft interruption to certain processor, simultaneously to mail transmission/reception case reading command or the data of correspondence, thereby complete two data command interactive communications between processor.
Beneficial effect: prior art of the present invention is compared, and has the following advantages:
What current double-core communication mainly utilized is the part of a certain fixed size in internal memory to be split to regard the interaction area of double-core information, two processors are by reading or deposit certain instruction or certain data in this section public domain, and process function by some software interruption and this part instruction or data are read in the another one processor go.This part space is fixed size, the fixed position, and can only deposit the data of specific format, can not accomplish to apply in a flexible way, and loss or the entanglement of former data might be caused because of sneaking into of other data in this part space, thereby cause the entanglement of system.
Core concept of the present invention is that the data that processor will need to communicate by letter are encoded, send in the mail transmission/reception case with the mail form and go, when the needs double-core is communicated by letter, the work at present processor sends look-at-me by vectorial interrupt handler to the another one processor, the another one processor is entered interrupt processing function, read mail and decoding obtains the raw data line operate of going forward side by side to the mail transmission/reception case, thereby realize and optimized the function that double-core is communicated by letter.What receive due to processor is not original data, but the mail of encoding and forming by processor, and instruction has special register, namely the mail transmission/reception case, can guarantee data not by other external data obfuscations, guarantee high efficiency and the validity of communication.
Description of drawings
Fig. 1 is SoC general frame structural drawing;
Fig. 2 is the schematic diagram of MailBox;
Fig. 3 is the schematic diagram that the double-core communication data flows to;
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
The present invention program is for the double-core communication issue of existing on-chip system chip, the proposition of creativity a kind of mail transmission/reception case that utilizes realize the device of communicating by letter between double-core.With reference to figure 1, the present invention is divided into processor module with acp chip, bus module, mail transmission/reception tank module and interruption processing module.
With reference to figure 2, the below further illustrates with regard to MailBox.
The fifo registers that comprises 32bit * 8 in each Mail Box can be preserved 8 envelope Mail.Each Mail is by a Mail Head(mail head) and a Mail Body(Mail Contents) form.The mail head is action type, for example redirect, and computing is interrupted processing etc.; Mail Contents is content of operation, the address of redirect for example, interrupt vector entry address, content of computing etc.The data that the communication source processor will need to communicate by letter form respectively mail head and Mail Contents and send in MailBox by coding, wait for reading of another one processor.
With reference to figure 3, communication mechanism is further illustrated.
When processor 1 needs processor 2 to participate in data processing and instruction execution:
The first step, processor 1 is encoded external module by the machine code (being operational order) that the bus module transmission comes, form an envelope mail, sends in mail transmission/reception case # 2;
Second step, the software forced interruption register in 1 pair of interruption processing module of processor writes certain value, triggers the soft interruption of VIC module;
The 3rd step; In processor 2, control processor 2 enters and interrupts processing function the VIC module with soft interrupting input;
In the 4th step, processor 2 is processed function by outage the mail in mail transmission/reception case # 2 is read out, and decoding obtains action type and content of operation, carries out this operation.
The above is only better embodiment of the present invention; protection scope of the present invention is not limited with above-mentioned embodiment; as long as the equivalence that those of ordinary skills do according to disclosed content is modified or changed, all should include in the protection domain of putting down in writing in claims.
Claims (5)
1. one kind is utilized the mail transmission/reception case to realize the device of communicating by letter between double-core, it is characterized in that, this device comprises processor module, bus module, mail transmission/reception tank module and interruption processing module;
Described processor module is used for receiving and sending instruction and data and described instruction and data are processed in mode of operation;
Described bus module is used for the data command transmission between modules;
Described mail transmission/reception tank module is used for temporary storage from the mail that processor module sends out, and is convenient to the director data exchange between different processor;
Described interruption processing module is responsible for waking up certain processor, makes it enter the double-core communication pattern and reads mail in the mail transmission/reception tank module.
2. the mail transmission/reception case that utilizes according to claim 1 is realized the device of communicating by letter between double-core, it is characterized in that, described mail transmission/reception tank module comprises two independent mail transmission/reception casees, mail from any one processor module is accepted and stored to each mail transmission/reception case, and each processor module carries out mail by bus module to the mail transmission/reception case and reads; Mail in the mail transmission/reception case is divided into mail head and Mail Contents, and described mail head sends the action type of data representative for processor module, and described Mail Contents is the content of operation of current operation.
3. the mail transmission/reception case that utilizes according to claim 1 is realized the device of communicating by letter between double-core, it is characterized in that, described processor module comprises two processors that can work independently, described processor is controlled the work of other modules, each processor has a corresponding mail transmission/reception case with it, and processor can form data encoding in mail and send to the mail transmission/reception case.
4. the mail transmission/reception case that utilizes according to claim 1 is realized the device of communicating by letter between double-core, it is characterized in that, described bus module is the coupling arrangement of all modules, and it follows advanced microcontroller bus architecture bus specification.
5. the mail transmission/reception case that utilizes according to claim 1 is realized the device of communicating by letter between double-core, it is characterized in that, described interruption processing module comprises a vectorial interrupt handler, described vectorial interrupt handler is controlled the purpose processor by the mode that sends soft interruption to certain processor, simultaneously to mail transmission/reception case reading command or the data of correspondence, thereby complete two data command interactive communications between processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100179286A CN103116566A (en) | 2013-01-17 | 2013-01-17 | Dual-core communication device by means of mail receive-and-send box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100179286A CN103116566A (en) | 2013-01-17 | 2013-01-17 | Dual-core communication device by means of mail receive-and-send box |
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| CN103116566A true CN103116566A (en) | 2013-05-22 |
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| CN2013100179286A Pending CN103116566A (en) | 2013-01-17 | 2013-01-17 | Dual-core communication device by means of mail receive-and-send box |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103440183A (en) * | 2013-09-02 | 2013-12-11 | 北京深思数盾科技有限公司 | Information safety protection device based on dual-core dual-head |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1964285A (en) * | 2006-12-13 | 2007-05-16 | 杭州华为三康技术有限公司 | A master control device with double CPU and realization method |
| US7529987B2 (en) * | 2003-06-05 | 2009-05-05 | Nxp B.V. | Integrity control for data stored in a non-volatile memory |
| EP1805626B1 (en) * | 2004-10-05 | 2009-07-22 | Sony Computer Entertainment Inc. | External data interface in a computer architecture for broadband networks |
| CN101788973A (en) * | 2010-01-12 | 2010-07-28 | 深圳市同洲电子股份有限公司 | Method for communication between dual processors |
-
2013
- 2013-01-17 CN CN2013100179286A patent/CN103116566A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7529987B2 (en) * | 2003-06-05 | 2009-05-05 | Nxp B.V. | Integrity control for data stored in a non-volatile memory |
| EP1805626B1 (en) * | 2004-10-05 | 2009-07-22 | Sony Computer Entertainment Inc. | External data interface in a computer architecture for broadband networks |
| CN1964285A (en) * | 2006-12-13 | 2007-05-16 | 杭州华为三康技术有限公司 | A master control device with double CPU and realization method |
| CN101788973A (en) * | 2010-01-12 | 2010-07-28 | 深圳市同洲电子股份有限公司 | Method for communication between dual processors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103440183A (en) * | 2013-09-02 | 2013-12-11 | 北京深思数盾科技有限公司 | Information safety protection device based on dual-core dual-head |
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Application publication date: 20130522 |