CN103107134B - Array base plate and manufacture method thereof and liquid crystal display device - Google Patents
Array base plate and manufacture method thereof and liquid crystal display device Download PDFInfo
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- CN103107134B CN103107134B CN201310031370.7A CN201310031370A CN103107134B CN 103107134 B CN103107134 B CN 103107134B CN 201310031370 A CN201310031370 A CN 201310031370A CN 103107134 B CN103107134 B CN 103107134B
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 88
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 239000010409 thin film Substances 0.000 claims abstract description 44
- 239000000203 mixture Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000009413 insulation Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 137
- 239000000758 substrate Substances 0.000 claims description 89
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 30
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 24
- 230000014759 maintenance of location Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
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- 238000000576 coating method Methods 0.000 claims description 12
- 239000011787 zinc oxide Substances 0.000 claims description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 229910003437 indium oxide Inorganic materials 0.000 claims description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 6
- 229910001887 tin oxide Inorganic materials 0.000 claims description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
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- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses an array base plate and a manufacture method of the array base plate and a liquid crystal display device. The manufacturing method comprises the steps of providing a base plate, forming a first conductive thin film on the base plate, and forming patterns including pixel electrodes through a composition technology; further forming a metal thin film, forming patterns including public electrode wires, gate electrode wires, data wires, source electrodes and leakage electrodes through the composition technology; further forming a semiconductor layer thin film, and forming the patterns including the semiconductor layer through the composition technology; further forming a gate insulation layer film, and forming patterns including a gate insulation layer and through holes through the composition technology; forming a second conductive thin film on the base plate forming the mentioned patterns, and forming the patterns including gate electrodes and public electrodes. The data wires, the gate electrode wires, the source electrodes and the leakage electrodes of thin film transistor (TFT) are formed simultaneously on the same layer of the base plate, and a semiconductor layer is formed between the source electrodes and the leakage electrodes. The process is good in controllability, and processing property is stable.
Description
Technical Field
The invention relates to a liquid crystal display technology, in particular to an array substrate, a manufacturing method thereof and a liquid crystal display device.
Background
A Thin Film Transistor Liquid Crystal Display (TFT-LCD) is an ideal Display device because it has the advantages of small size, low power consumption, no radiation, etc. In recent years, the application range of TFT-LCD in the display field is gradually expanding, and the related technology is also rapidly developing.
In the prior art, the advanced Super dimension field switching (ads) TFT-LCD is mainly completed by five patterning processes, wherein a gray-tone mask plate is used to form the TFT channel of the thin film transistor. However, in practical applications, it is found that the controllability of the TFT channel pattern formed by using the gray-tone mask is poor, and the process performance is unstable.
Disclosure of Invention
The invention aims to provide an array substrate, a manufacturing method thereof and a liquid crystal display device, and aims to solve the problems that in the process of manufacturing a TFT-LCD array substrate in the prior art, a gray-tone mask plate is adopted to form a TFT channel pattern, controllability is poor, and process performance is unstable.
The purpose of the invention is realized by the following technical scheme:
the embodiment of the invention provides a manufacturing method of an array substrate, which comprises the following steps:
step 1, providing a substrate, forming a first conductive film on the substrate, and forming a pattern comprising a pixel electrode through a composition process;
step 2, forming a metal film on the substrate on which the patterns are formed, and forming the patterns comprising a common electrode line, a grid electrode line, a data line, a source electrode and a drain electrode through a composition process;
step 3, forming a semiconductor layer film on the substrate on which the pattern is formed, and forming the pattern comprising the semiconductor layer through a composition process;
step 4, forming a grid insulation layer film on the substrate on which the patterns are formed, and forming the patterns comprising the grid insulation layer and the via holes through a composition process; the positions of the via holes correspond to the positions of the grid electrode wires and the common electrode wires, and the via holes expose parts of the grid electrode wires and the common electrode wires;
step 5, forming a second conductive film on the substrate on which the patterns are formed, and forming the patterns comprising the gate electrode and the common electrode through a composition process; the gate electrode can be connected with the gate electrode line through part of the via holes, and the common electrode is connected with the common electrode line through part of the via holes.
Preferably, the step 1 includes:
step 11, forming the first conductive film on the substrate;
step 12, coating photoresist on the first conductive film;
step 13, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retaining area and a photoresist complete stripping area, wherein the photoresist complete retaining area corresponds to the pattern of the pixel electrode;
step 14, etching the first conductive film in the photoresist complete stripping area to form a pattern including the pixel electrode;
and 15, stripping the photoresist in the photoresist complete reserved area.
Preferably, the step 2 includes:
step 21, forming the metal film;
step 22, coating photoresist on the metal film;
step 23, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retention area and a photoresist complete stripping area, wherein the photoresist complete retention area corresponds to the patterns of the common electrode line, the gate electrode line, the data line, the source electrode and the drain electrode;
step 24, etching the metal film in the photoresist complete stripping area to form a pattern comprising the common electrode line, the grid electrode line, the data line, the source electrode and the drain electrode;
and 25, stripping the photoresist in the photoresist complete reserved area.
Preferably, the step 3 includes:
step 31, forming the semiconductor layer film;
step 32, coating photoresist on the semiconductor layer film;
step 33, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retention area and a photoresist complete stripping area, wherein the photoresist complete retention area corresponds to the pattern of the semiconductor layer;
step 34, etching the semiconductor layer film in the photoresist complete stripping area to form a pattern comprising the semiconductor layer;
and step 35, stripping the photoresist in the photoresist complete reserved area.
Preferably, the semiconductor layer film is an amorphous silicon film and a doped amorphous silicon film; the forming of the semiconductor layer film is specifically as follows: the amorphous silicon thin film is formed first, and then the doped amorphous silicon thin film is formed.
Preferably, the semiconductor layer thin film is an oxide thin film, and the oxide thin film is any one of an indium oxide thin film, a zinc oxide thin film, a tin oxide thin film, and an indium gallium zinc oxide thin film.
Preferably, the step 4 includes:
step 41, forming the gate insulation layer film;
step 42, coating photoresist on the gate insulation layer film;
43, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retaining area and a photoresist complete stripping area, wherein the photoresist complete retaining area corresponds to the patterns of the grid insulation layer and the via hole;
step 44, etching the gate insulating layer film in the photoresist complete stripping area to form a pattern comprising the gate insulating layer and a via hole;
and step 45, stripping the photoresist in the photoresist complete reserved area.
Preferably, the step 5 includes:
step 51, forming the second conductive film;
step 52, coating photoresist on the second conductive film;
step 53, exposing and developing the photoresist by using a mask plate to form photoresist patterns comprising a photoresist complete retention area and a photoresist complete stripping area, wherein the photoresist complete retention area corresponds to the patterns of the gate electrode and the common electrode;
step 54, etching the second conductive film in the photoresist complete stripping area to form a pattern including the gate electrode and the common electrode;
and step 55, stripping the photoresist in the photoresist complete reserved area.
The embodiment of the invention has the following beneficial effects: a data line, a grid electrode line, a source electrode and a drain electrode of the TFT are synchronously formed on the same layer of the substrate, and a semiconductor layer is formed between the source electrode and the drain electrode, so that the process has good controllability and stable process performance; and a gray tone mask plate is not needed, so that the process steps are reduced, and the cost is saved.
The embodiment of the invention provides an array substrate, which is manufactured by adopting the manufacturing method of the array substrate.
Preferably, the display device further comprises a common electrode line formed on the substrate, and the common electrode line and the gate electrode line, the data line, the source electrode and the drain electrode are arranged in the same layer and are formed synchronously.
Preferably, the organic light emitting device further comprises a common electrode formed on the gate insulating layer; the common electrode is connected with the common electrode line through a via hole penetrating through the gate insulating layer.
Preferably, the common electrode and the gate electrode are disposed in the same layer and formed simultaneously.
Preferably, the semiconductor layer comprises an amorphous silicon semiconductor layer and a doped amorphous silicon semiconductor layer, and the amorphous silicon semiconductor layer is located below the doped amorphous silicon semiconductor layer.
Preferably, the semiconductor layer includes an oxide layer, and the oxide layer is any one of an indium oxide layer, a zinc oxide layer, a tin oxide layer, or an indium gallium zinc oxide layer.
An embodiment of the invention provides a liquid crystal display device, which includes the array substrate.
The embodiment of the invention has the following beneficial effects: the array substrate is provided with the data lines, the grid electrode lines, the source electrodes and the drain electrodes of the TFTs which are arranged on the same layer and are synchronously formed, and a semiconductor layer is formed between the source electrodes and the drain electrodes; and a gray tone mask plate is not needed, so that the process steps are reduced, and the process manufacturing time and cost are saved.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
FIGS. 2-6 are step-by-step flow diagrams of steps of a method according to an embodiment of the invention;
fig. 7 is a schematic partial top view of an array substrate according to a second embodiment of the invention;
fig. 8 is an expanded cross-sectional view (the BB 'portion is omitted) of the array substrate according to the second embodiment of the invention, taken along the cross-section AA' in fig. 7;
fig. 9A to 9D are partial schematic views illustrating step-by-step fabrication of an array substrate according to a fourth embodiment of the invention.
Detailed Description
The following describes in detail the implementation of the embodiments of the present invention with reference to the drawings.
An embodiment of the present invention provides a method for manufacturing an array substrate, as shown in fig. 1, the method includes the following steps:
step S101, providing a substrate, depositing a first conductive film on the substrate, and forming a pattern including a pixel electrode through a patterning process.
In step S101, the substrate may be an inorganic material-based substrate such as a glass substrate or a quartz substrate, or may be an organic material-based substrate;
the material of the first conductive film may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like.
Step S102, forming a metal thin film on the substrate on which the pattern is formed, and forming a pattern including a common electrode line, a gate electrode line, a data line, a source electrode, and a drain electrode by a patterning process.
Step S103, forming a semiconductor layer thin film on the substrate on which the above pattern is formed, and forming a pattern including a semiconductor layer through a patterning process.
Step S104, forming a grid insulation layer film on the substrate with the pattern, and forming a pattern comprising a grid insulation layer and a via hole through a composition process; the via hole is formed on the gate insulating layer at a position corresponding to the gate electrode line and the common electrode line, and part of the gate electrode line and the common electrode line are exposed out of the via hole.
Step S105, forming a second conductive film on the substrate on which the pattern is formed, and forming a pattern including a gate electrode and a common electrode through a patterning process; the gate electrode and the common electrode are respectively connected with the gate electrode line and the common electrode line through the via hole. Preferably, as shown in fig. 2, step S101: depositing a first conductive film on a substrate, and forming a pattern of a pixel electrode through a composition process, wherein the method specifically comprises the following steps:
in step S1011, a first conductive film is deposited on the substrate.
In step S1012, a photoresist is coated on the first conductive film.
Step S1013, exposing and developing the photoresist by using a mask plate to form a photoresist pattern including a photoresist complete retention region and a photoresist complete stripping region, where the photoresist complete retention region corresponds to a pattern of the pixel electrode.
Step 1014, etching the first conductive film in the photoresist complete stripping area to form a pattern including a pixel electrode.
Step S1015, the photoresist in the photoresist complete remaining region is stripped.
Preferably, as shown in fig. 3, step S102: depositing a metal film on the substrate on which the pattern is formed, and forming the pattern comprising a gate electrode line, a data line, a source electrode and a drain electrode by a composition process, wherein the pattern comprises:
step S1021, depositing a metal film on the substrate formed in step S101.
In step S1022, a photoresist is coated on the metal film.
And step S1023, exposing and developing the photoresist by using a mask plate to form photoresist patterns comprising a photoresist complete reserved area and a photoresist complete stripping area, wherein the photoresist complete reserved area corresponds to the patterns of a public electrode wire, a grid electrode wire, a data wire, a source electrode and a drain electrode.
Step S1024, the metal film in the photoresist complete stripping area is etched to form a pattern including a common electrode line, a gate electrode line, a data line, a source electrode and a drain electrode.
In step S1025, the photoresist in the photoresist complete remaining region is stripped.
Preferably, as shown in fig. 4, step S103: depositing a semiconductor layer film on the substrate on which the pattern is formed, and forming the pattern including the semiconductor layer by a patterning process, including:
and a step S1031 of depositing a semiconductor layer film on the substrate formed in the step S102.
Step S1032 is to coat a photoresist on the semiconductor layer film.
Step S1033, exposing and developing the photoresist by using a mask to form a photoresist pattern including a photoresist complete remaining region and a photoresist complete stripping region, where the photoresist complete remaining region corresponds to the pattern of the semiconductor layer.
Step S1034, the semiconductor layer film in the photoresist complete stripping region is etched to form a pattern including a semiconductor layer.
In step S1035, the photoresist in the photoresist complete remaining area is stripped.
Preferably, the semiconductor layer film is an amorphous silicon film or a doped amorphous silicon film, wherein the amorphous silicon film is deposited first, and then the doped amorphous silicon film is deposited.
Of course, the semiconductor thin film may be an oxide thin film, and the oxide thin film may be any of material thin films that can be used as an oxide thin film, such as an indium oxide thin film, a zinc oxide thin film, a tin oxide thin film, or an indium gallium zinc oxide thin film.
Preferably, as shown in fig. 5, step S104: depositing a gate insulating layer film on the substrate on which the pattern is formed, and forming a pattern including a gate insulating layer and a via hole by a patterning process, including:
in step S1041, a gate insulating layer film is deposited on the substrate formed in step S103.
In step S1042, a photoresist is coated on the gate insulating film.
Step S1043, exposing and developing the photoresist by using a mask plate to form a photoresist pattern including a photoresist complete remaining region and a photoresist complete stripping region, where the photoresist complete remaining region corresponds to the pattern of the gate insulating layer and the via hole.
Step S1044 is that the grid electrode insulating layer film in the photoresist complete stripping area is etched to form a pattern comprising a grid electrode insulating layer and a via hole;
step S1045, stripping the photoresist in the photoresist complete remaining region.
Preferably, as shown in fig. 6, step S105: depositing a second conductive film on the substrate on which the pattern is formed, and forming a pattern including a gate electrode and a common electrode by a patterning process, including:
step S1051, depositing a second conductive film on the substrate formed in step S104.
In step S1052, a photoresist is coated on the second conductive film.
And step S1053, exposing and developing the photoresist by using a mask plate to form photoresist patterns comprising a photoresist complete reserved area and a photoresist complete stripping area, wherein the photoresist complete reserved area corresponds to the patterns of the gate electrode and the common electrode.
Step S1054, the second conductive film in the photoresist complete strip region is etched to form a pattern including a gate electrode and a common electrode.
Step S1055, the photoresist in the photoresist complete remaining region is stripped.
Preferably, the first conductive film and the second conductive film are transparent conductive films.
Further, it is preferable that wet etching is used in steps S101, S102, and S105, and dry etching is used in steps S103 and S104.
The embodiment of the invention has the following beneficial effects: the data lines, the grid electrode lines, the source electrodes and the drain electrodes of the TFTs are synchronously formed on the same layer of the substrate, and the semiconductor layer is formed between the source electrodes and the drain electrodes; and a gray tone mask plate is not needed, so that the process steps are reduced, and the process manufacturing time and cost are saved.
In a second embodiment of the present invention, as shown in fig. 7, which is a partial schematic view of a top view of an array substrate, for clearly illustrating various components of the array substrate, overlapping portions between components are also shown by solid lines. The array substrate comprises a substrate 1, wherein gate electrode lines 2, data lines 3 and pixel units (pixel units are not numbered in FIG. 7) which are criss-cross are formed on the substrate 1, each pixel unit comprises a thin film field effect transistor (TFT) switch 5 and a pixel electrode 6, the TFT switch 5 comprises a gate electrode 51, a source electrode 52, a drain electrode 53 and a semiconductor layer 54;
the pixel electrode 6, the gate electrode line 2, the data line 3, the source electrode 52 and the drain electrode 53 are formed on the substrate 1; the source electrode 52 is connected to the data line 3; a partial region of the drain electrode 53 is formed over the pixel electrode 6, the region being connected to the pixel electrode 6; the semiconductor layer 54 is formed between the source electrode 52 and the drain electrode 53, and is connected to the source electrode 52 and the drain electrode 53; a gate insulating layer 7 is formed over the semiconductor layer 54 (the gate insulating layer 7 is not shown in fig. 7), the gate insulating layer 7 covering the substrate 1; the gate electrode 51 is formed on the gate insulating layer 7, and the gate electrode 51 is connected to the gate electrode line 2 through a via 10 penetrating the gate insulating layer 7.
To more clearly illustrate the above structure, the cross section is taken at AA 'shown in fig. 7, so as to obtain an expanded cross-sectional schematic view (the cross section at BB' shown in fig. 7 is omitted) as shown in fig. 8, wherein the gate insulating layer 7 is included, and the gate insulating layer 7 covers the substrate 1.
Preferably, the display device further comprises a common electrode line 8, wherein the common electrode line 8 is formed on the substrate 1, and is arranged in the same layer as and formed synchronously with the gate electrode line 2, the data line 3, the source electrode 52 and the drain electrode 53.
Preferably, the organic light emitting diode further comprises a common electrode 9, wherein the common electrode 9 is formed on the gate insulating layer 7; the common electrode 9 is connected to the common electrode line 8 through a via 10 penetrating the gate insulating layer 7.
Preferably, the common electrode 9 is disposed in the same layer as and formed in synchronization with the gate electrode 51.
Further, it is preferable that the semiconductor layer 54 includes an amorphous silicon semiconductor layer and a doped amorphous silicon semiconductor layer (the amorphous silicon semiconductor layer and the doped amorphous silicon semiconductor layer are not labeled in fig. 7 and 8), the amorphous silicon semiconductor layer being located below the doped amorphous silicon semiconductor layer; or,
preferably, the semiconductor layer 54 includes an oxide layer, and the oxide layer is any one of materials that can be used as an oxide layer, such as an indium oxide layer, a zinc oxide layer, a tin oxide layer, or an indium gallium zinc oxide layer.
The third embodiment of the invention provides a liquid crystal display device, which comprises the array substrate.
The embodiment of the invention has the following beneficial effects: the array substrate is provided with the data lines, the grid electrode lines, the source electrodes and the drain electrodes of the TFTs which are arranged on the same layer and are synchronously formed, and a semiconductor layer is formed between the source electrodes and the drain electrodes; and a gray tone mask plate is not needed, so that the process steps are reduced, and the process manufacturing time and cost are saved.
In the fourth embodiment of the present invention, a manufacturing process of the array substrate of the present invention is described in detail as shown in fig. 9A to 9D, where the substrate is not shown. The method comprises the following steps:
step one, a first conductive film is deposited on the substrate, and a pattern of the pixel electrode 6 as shown in fig. 9A is formed through a patterning process.
Step two, depositing a metal film on the substrate on which the above-mentioned pattern is formed, and forming a pattern including the common electrode line 8, the gate electrode line 2, the data line 3, the source electrode 52 and the drain electrode 53 as shown in fig. 9B through a patterning process. The patterns of the common electrode line 8, the gate electrode line 2, the data line 3, the source electrode 52 and the drain electrode 53 are completed in synchronization.
Note that the data line 3 and the source electrode 52 are integrally formed in synchronization, and the source electrode 52 is a portion shown within a dotted line.
Step three, depositing a semiconductor layer film on the substrate on which the above pattern is formed, and forming a pattern including the semiconductor layer 54 as shown in fig. 9C by a patterning process. Wherein, the semiconductor layer film in the third step is a doped amorphous silicon film and an amorphous silicon film; therefore, the doped amorphous silicon thin film needs to be deposited first, and then the amorphous silicon thin film needs to be deposited.
Note that when the semiconductor layer film is an oxide film, only one deposition is required.
Step four, depositing a gate insulating layer film on the substrate on which the pattern is formed, and forming a pattern including the gate insulating layer 7 (not shown in fig. 9C, refer to a partial sectional view of the array substrate shown in fig. 8) and the via hole 10 as shown in fig. 9D through a patterning process; the via hole 10 is formed on the gate insulating layer 7 at a position corresponding to the gate electrode line 2 and the common electrode line 8, and the via hole 10 exposes a portion of the gate electrode line 2 and the common electrode line 8.
Step five, depositing a second conductive film on the substrate on which the pattern is formed, and forming a pattern including the gate electrode 51 and the common electrode 9 through a patterning process (as shown in a partial top view of the array substrate shown in fig. 7); wherein, the gate electrode 51 and the common electrode 9 are connected with the gate electrode line 2 and the common electrode line 8 through the via 10, respectively. In the manufacturing process, the insulating layer deposition and etching are carried out only once, so that the thickness of the insulating layer between the common electrode and the pixel electrode can be controlled, and the process performance is stable; and a gray tone mask plate is not needed, so that the process steps are reduced, and the process manufacturing time and cost are saved.
It should be noted that the formation of the thin film in the above embodiments is described by taking deposition as an example, but the method of the present invention is not limited thereto. The formation of the thin film involved in the above respective embodiments may include: deposition, coating, sputtering, printing, and the like; the related patterning process comprises the following steps: coating photoresist, sputtering, evaporation, exposure and development, etching, ashing, removing the photoresist and the like.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
step 1, providing a substrate, forming a first conductive film on the substrate, and forming a pattern comprising a pixel electrode through a composition process;
step 2, forming a metal film on the substrate on which the patterns are formed, and synchronously forming the patterns comprising a common electrode line, a grid electrode line, a data line, a source electrode and a drain electrode on the same layer by a composition process;
step 3, forming a semiconductor layer film on the substrate on which the pattern is formed, and forming the pattern comprising the semiconductor layer through a composition process;
step 4, forming a gate insulation layer film on the substrate with the patterns, and forming a gate insulation layer pattern comprising a via hole through a composition process; the positions of the via holes correspond to the positions of the grid electrode wires and the common electrode wires, and the via holes expose parts of the grid electrode wires and the common electrode wires;
step 5, forming a second conductive film on the substrate on which the patterns are formed, and forming the patterns comprising the gate electrode and the common electrode through a composition process; the gate electrode is connected with the gate electrode line by penetrating through the via hole, and the common electrode is connected with the common electrode line by penetrating through the via hole.
2. The method for manufacturing the array substrate according to claim 1, wherein the step 1 comprises:
step 11, forming the first conductive film on the substrate;
step 12, coating photoresist on the first conductive film;
step 13, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retaining area and a photoresist complete stripping area, wherein the photoresist complete retaining area corresponds to the pattern of the pixel electrode;
step 14, etching the first conductive film in the photoresist complete stripping area to form a pattern including the pixel electrode;
and 15, stripping the photoresist in the photoresist complete reserved area.
3. The method for manufacturing the array substrate according to claim 1, wherein the step 2 comprises:
step 21, forming the metal film;
step 22, coating photoresist on the metal film;
step 23, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retention area and a photoresist complete stripping area, wherein the photoresist complete retention area corresponds to the patterns of the common electrode line, the gate electrode line, the data line, the source electrode and the drain electrode;
step 24, etching the metal film in the photoresist complete stripping area to form a pattern comprising the common electrode line, the grid electrode line, the data line, the source electrode and the drain electrode;
and 25, stripping the photoresist in the photoresist complete reserved area.
4. The method for manufacturing the array substrate according to claim 1, wherein the step 3 comprises:
step 31, forming the semiconductor layer film;
step 32, coating photoresist on the semiconductor layer film;
step 33, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retention area and a photoresist complete stripping area, wherein the photoresist complete retention area corresponds to the pattern of the semiconductor layer;
step 34, etching the semiconductor layer film in the photoresist complete stripping area to form a pattern comprising the semiconductor layer;
and step 35, stripping the photoresist in the photoresist complete reserved area.
5. The method of manufacturing an array substrate of claim 4, wherein the semiconductor layer thin film is an amorphous silicon thin film and a doped amorphous silicon thin film;
the forming of the semiconductor layer film is specifically as follows: the amorphous silicon thin film is formed first, and then the doped amorphous silicon thin film is formed.
6. The method of manufacturing an array substrate according to claim 4, wherein the semiconductor layer thin film is an oxide thin film, and the oxide thin film is any one of an indium oxide thin film, a zinc oxide thin film, a tin oxide thin film, or an indium gallium zinc oxide thin film.
7. The method for manufacturing the array substrate according to claim 1, wherein the step 4 comprises:
step 41, forming the gate insulation layer film;
step 42, coating photoresist on the gate insulation layer film;
43, exposing and developing the photoresist by using a mask plate to form a photoresist pattern comprising a photoresist complete retaining area and a photoresist complete stripping area, wherein the photoresist complete retaining area corresponds to the patterns of the grid insulation layer and the via hole;
step 44, etching the gate insulating layer film in the photoresist complete stripping area to form a pattern comprising the gate insulating layer and a via hole;
and step 45, stripping the photoresist in the photoresist complete reserved area.
8. The method for manufacturing the array substrate according to claim 1, wherein the step 5 comprises:
step 51, forming the second conductive film;
step 52, coating photoresist on the second conductive film;
step 53, exposing and developing the photoresist by using a mask plate to form photoresist patterns comprising a photoresist complete retention area and a photoresist complete stripping area, wherein the photoresist complete retention area corresponds to the patterns of the gate electrode and the common electrode;
step 54, etching the second conductive film in the photoresist complete stripping area to form a pattern including the gate electrode and the common electrode;
and step 55, stripping the photoresist in the photoresist complete reserved area.
9. An array substrate, comprising: the array substrate is manufactured by the method of any one of claims 1 to 8.
10. The array substrate of claim 9, further comprising a common electrode line formed on the substrate in the same layer as the gate electrode line, the data line, the source electrode, and the drain electrode and formed simultaneously.
11. The array substrate of claim 10, further comprising a common electrode formed on the gate insulating layer; the common electrode is connected with the common electrode line through a via hole penetrating through the gate insulating layer.
12. The array substrate of claim 11, wherein the common electrode and the gate electrode are disposed in the same layer and are formed simultaneously.
13. The array substrate of claim 9, wherein the semiconductor layer comprises an amorphous silicon semiconductor layer and a doped amorphous silicon semiconductor layer, and the amorphous silicon semiconductor layer is located below the doped amorphous silicon semiconductor layer.
14. The array substrate of claim 9, wherein the semiconductor layer comprises an oxide layer, and the oxide layer is any one of an indium oxide layer, a zinc oxide layer, a tin oxide layer, or an indium gallium zinc oxide layer.
15. A liquid crystal display device comprising the array substrate according to any one of claims 9 to 14.
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| CN104916649A (en) * | 2015-06-16 | 2015-09-16 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN105047610B (en) | 2015-09-07 | 2018-10-12 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN113658913B (en) * | 2021-07-09 | 2024-05-31 | 深圳莱宝高科技股份有限公司 | Array substrate manufacturing method, array substrate, electronic paper device and manufacturing method thereof |
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| CN102270604B (en) * | 2010-06-03 | 2013-11-20 | 北京京东方光电科技有限公司 | Structure of array substrate and manufacturing method thereof |
| CN102446925B (en) * | 2010-09-30 | 2015-05-20 | 京东方科技集团股份有限公司 | Array base plate, liquid crystal display and manufacturing method for array base plate |
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