CN103107103A - Reconfigurable operator array structure scale extension method based on wafer level packaging (WLP) form - Google Patents
Reconfigurable operator array structure scale extension method based on wafer level packaging (WLP) form Download PDFInfo
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- CN103107103A CN103107103A CN2011103576442A CN201110357644A CN103107103A CN 103107103 A CN103107103 A CN 103107103A CN 2011103576442 A CN2011103576442 A CN 2011103576442A CN 201110357644 A CN201110357644 A CN 201110357644A CN 103107103 A CN103107103 A CN 103107103A
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- array structure
- wlp
- operator array
- reconfigurable operator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention discloses a reeconfigurable operator array structure scale extension method based on a wafer level packaging (WLP) form. According to the method, adjacent input outputs (IO) of a plurality of reeconfigurable operator array structural chips can be connected on a wafer. Unconnected IOs are led out. The wafer is subjected to cutting and packaging to form multiple-scale array structural chips. The method includes a first step of photoetching, forming connecting through holes in positions of the IOs of all the chips on the wafer, and forming channels between the IOs which need connecting, a second step of carrying out aluminum evaporation, and filling the connecting through holes of the IOs and the channels between the IOs to form a first metal layer, a third step of photoetching, forming the connecting through holes in the positions of the IOs which need to be connected out, a fourth step of carrying out aluminum evaporation, and filling the connecting through holes of the IOs to enable electrical terminals to be exposed out, a fifth step of growing protruding points at each electrical terminal, a sixth step of cutting to obtain multiple-scale reeconfigurable operator array structural chips, and a seventh step of covering a layer of packaging materials on the periphery of each independent chip to provide protection. The reeconfigurable operator array structure scale extension method based on the WLP form enables the same design to be suitable for multiple-scale application requirements.
Description
[technical field]
The present invention relates to integrated circuit (IC) design and encapsulation technology field, be specifically related to a kind of Expansion method of the reconfigurable operator array structure based on the WLP packing forms.
[background technology]
Along with integrated circuit fabrication process enters the 45-22nm stage, the integrated transistor number has reached tens these scales on one single chip, makes the structure that realizes the array scale become possibility.A kind of ARRAY PROCESSING structure that is applicable to the unified shader of parallel computing that the integrated micro-system of Shenzhen Graduate School of Peking University laboratory proposes, and apply for a patent " a kind of array structure 201110083948.2 of restructural operator " for this structure.This array structure contains the demand of abundant restructural computing operator, storage operators support processing, the realization of simultaneously a large amount of path operators and interconnection resource supported data transmission, the design that this system is applicable to the restructural operator can repeatedly be programmed and be supported the needs that multiple application realizes.
The scale demand of different application pair array structures is different, in order to meet the different needs, need to provide the reconfigurable operator array structure of the different scales of a plurality of series.This patent proposes a kind of Expansion method of the reconfigurable operator array structure based on the WLP packing forms, only design a kind of reconfigurable operator array structure chip of scale, encapsulation after wafer scale connects a plurality of such array structure chips, thereby the reconfigurable operator array structure chip of formation random scale.
[summary of the invention]
A kind of Expansion method that the purpose of this invention is to provide reconfigurable operator array structure based on the WLP packing forms makes the same design can adapt to the application demand of different scales.
For achieving the above object, the invention provides a kind of Expansion method of the reconfigurable operator array structure based on the WLP packing forms.Described method is by being connected at the IO that closes on of wafer scale with a plurality of reconfigurable operator array structure chips, and the IO that do not connect of one single chip is drawn as the IO of array structure, through cutting and encapsulation, thereby forms the array structure chip of multiple scale.Step is as follows:
Step 1: photoetching, IO place's formation connecting through hole of all reconfigurable operator array structure chips, form passage between the IO that needs connect on wafer, and other local insulated oxide covers;
Need the IO that connects to be the IO on contiguous reconfigurable operator array structure chip by chip limit in described step 1, the IO of the adjacent edge of n adjacent chips can be connected as required, n represents the integer that equals greater than 1;
In described step 1, the distribution of adjacent chips can be that one-dimensional linear is adjacent, and also two dimension is adjacent;
Step 2: evaporation of aluminum, fill the connecting through hole of IO and the passage between IO, form the first layer metal layer;
The IO that in described step 2, needs is drawn guides on first layer metal by connecting through hole, prepares outward for guiding at last chip.Realize simultaneously the connection of IO of the adjacent edge of adjacent chips on first layer metal.
Step 3: photoetching, connect the IO place's formation connecting through hole that at needs, other place is insulated oxide and covers;
Step 4: evaporation of aluminum, the connecting through hole of filling IO exposes electric terminal;
Step 5: at each electric terminal place's growth salient point;
Step 6: cut as the boundary take the zone between salient point, obtain the reconfigurable operator array structure chip of different scales;
Step 7: the periphery in single individual chips covers one deck encapsulating material, exposes salient point.
Described step 7 is for one deck protection being provided to single independently chip, making it be difficult for being damaged.
The invention has the beneficial effects as follows: the invention provides a kind of Expansion method of the reconfigurable operator array structure based on the WLP packing forms, make the same design can adapt to the application demand of different scales.
[description of drawings]
Fig. 1 is a kind of embodiment of Expansion method flow diagram of the reconfigurable operator array structure based on the WLP packing forms;
Fig. 2 is a kind of wafer schematic diagram that loads the reconfigurable operator array structure chip;
Fig. 3 is the more large scale array structural representation that a kind of 4 reconfigurable operator array structure chips are built;
Fig. 4 to Figure 11 is packaging body schematic diagram in flow process shown in Figure 1.
[embodiment]
The application's feature and advantage will be by embodiment, in conjunction with the accompanying drawings.
The present invention proposes a kind of Expansion method of the reconfigurable operator array structure based on the WLP packing forms, described method is by being connected at the IO that closes on of wafer scale with a plurality of reconfigurable operator array structure chips, the IO that do not connect of one single chip is drawn as the IO of array structure, thereby forms more massive array structure.The method can be so that the same design can adapt to the application demand of different scales.
The step of described method as shown in Figure 1.
Step 1 S101: photoetching, IO place's formation connecting through hole of all reconfigurable operator array structure chips, form passage between the IO that needs connect on wafer, and other local insulated oxide covers.
Wafer described in S101 is 201 in Fig. 2, a lot of reconfigurable operator array structure chips 202 that distributing on 201, and its IO is distributed in surrounding.The IO of the adjacent edge of n adjacent chips can be connected according to the needs of using, n represents the integer that equals greater than 1.The distribution of adjacent chips can be that one-dimensional linear is adjacent simultaneously, and also two dimension is adjacent.203,204,205,206 be respectively 2,3,4,6 the more massive reconfigurable operator array structures of chips composition.
Provided the IO connection diagram of carrying out the reconfigurable operator array structure chip of Expansion in the adjacent mode of two dimension in figure three.301 is single reconfigurable operator array structure chip, and 302 is IO, and 303 is the connecting line that adjacent chips adjacent edge IO is connected.
Step 2 S102: evaporation of aluminum, fill the connecting through hole of IO and the passage between IO, form the first layer metal layer.With connecting through hole and the passage filling aluminum that forms in S101, form the first layer metal layer of conduction, do not prepared outward for drawing at last chip by the IO that passage is connected.
Step 3 S103: photoetching, connect the IO place's formation connecting through hole that at needs, other place is insulated oxide and covers.
Step 4 S104: evaporation of aluminum, the connecting through hole of filling IO exposes electric terminal.The conductive pin that so-called electric terminal namely can be connected with the external world.
Step 5 S105: at each electric terminal place's growth salient point.
Salient point in described S105 is the unit that is connected with other element after encapsulation is completed.
Step 6 S106: cut as the boundary take the zone between salient point, obtain the reconfigurable operator array structure chip of different scales.
Step 7 S107: step 7: the periphery in single individual chips covers one deck encapsulating material, exposes salient point.
Described S107 is for one deck protection being provided to single independently chip, making it be difficult for being damaged.
In Fig. 4 to Figure 11, illustrate for per step flow process in Fig. 1.
In Fig. 4,401 is wafer, and 402 is the IO on wafer.
Fig. 5 is corresponding S101, forms connecting through hole 501 at 402 places, needs connect 402 between form passage 502, other local insulated oxide 503 covers.
Fig. 6 is corresponding S102, fills 501 and 502 with aluminium 601, forms the first layer metal layer.
Fig. 7 is corresponding S103, and at IO place's formation connecting through hole 701 that needs are drawn, other place is insulated oxide 702 and covers.
Fig. 8 is corresponding S104, and filling 701,802 with aluminium 801 is conductive electric terminal.
Fig. 9 is corresponding S105, growth salient point 901 on 802.
Figure 10 is corresponding S106, and wafer is cut, and obtains the reconfigurable operator array structure chip of different scales.
Figure 11 is corresponding S107, forms one deck encapsulating material 1101 in single independently reconfigurable operator array structure chip periphery, for this chip provides protection.
Above content is in conjunction with execution mode further description made for the present invention, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (9)
1. Expansion method based on the reconfigurable operator array structure of WLP packing forms, described method is namely by being connected at the IO that closes on of wafer scale with a plurality of reconfigurable operator array structure chips, do not connect IO and draw, through cutting and encapsulation, thereby form more massive array structure chip.It is characterized in that: described method step one is photoetching, and IO place's formation connecting through hole of all chips, form passage between the IO that needs connect on wafer;
2. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: needing the IO that connects in described method step one is the IO on contiguous reconfigurable operator array structure chip by chip limit, the IO of the adjacent edge of n adjacent chips can be connected as required, the n representative equals the integer greater than 1;
3. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: in described method step one, the distribution of adjacent chips can be that one-dimensional linear is adjacent, also two dimension is adjacent;
4. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step two is evaporation of aluminum, the connecting through hole of the I that obtains in filling step one and the passage between IO form the first layer metal layer;
5. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step three is photoetching, connect the IO place's formation connecting through hole that at needs, other place is insulated oxide and covers;
6. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step four is evaporation of aluminum, fills the connecting through hole of IO, exposes electric terminal;
7. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1 is characterized in that: described method step five is at each electric terminal place's growth salient point;
8. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step six obtains the reconfigurable operator array structure chip of different scales for to cut take the zone between salient point as the boundary;
9. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step seven exposes salient point for the periphery in single individual chips covers one deck encapsulating material.
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| CN101110438A (en) * | 2006-07-19 | 2008-01-23 | 育霈科技股份有限公司 | Structure of image sensor module and a method for manufacturing of wafer level package |
| CN101197356A (en) * | 2006-12-08 | 2008-06-11 | 育霈科技股份有限公司 | Multi-chip package structure and its forming method |
| CN101211903A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | RF module package structure and its forming method |
| CN101425469A (en) * | 2007-10-30 | 2009-05-06 | 育霈科技股份有限公司 | Semi-conductor packaging method using large size panel |
| CN101436553A (en) * | 2007-11-16 | 2009-05-20 | 南茂科技股份有限公司 | Method for manufacturing package structure with reconfigured chip by metal projection |
| CN101477955A (en) * | 2008-01-04 | 2009-07-08 | 南茂科技股份有限公司 | Encapsulation structure and method for tablet reconfiguration |
| CN101609822A (en) * | 2008-06-19 | 2009-12-23 | 南茂科技股份有限公司 | Encapsulating structure that chip reconfigures and method thereof |
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- 2011-11-11 CN CN2011103576442A patent/CN103107103A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110438A (en) * | 2006-07-19 | 2008-01-23 | 育霈科技股份有限公司 | Structure of image sensor module and a method for manufacturing of wafer level package |
| CN101197356A (en) * | 2006-12-08 | 2008-06-11 | 育霈科技股份有限公司 | Multi-chip package structure and its forming method |
| CN101211903A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | RF module package structure and its forming method |
| CN101425469A (en) * | 2007-10-30 | 2009-05-06 | 育霈科技股份有限公司 | Semi-conductor packaging method using large size panel |
| CN101436553A (en) * | 2007-11-16 | 2009-05-20 | 南茂科技股份有限公司 | Method for manufacturing package structure with reconfigured chip by metal projection |
| CN101477955A (en) * | 2008-01-04 | 2009-07-08 | 南茂科技股份有限公司 | Encapsulation structure and method for tablet reconfiguration |
| CN101609822A (en) * | 2008-06-19 | 2009-12-23 | 南茂科技股份有限公司 | Encapsulating structure that chip reconfigures and method thereof |
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Application publication date: 20130515 |