CN103106063A - Analog multiplication and division method operational circuit - Google Patents

Analog multiplication and division method operational circuit Download PDF

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Publication number
CN103106063A
CN103106063A CN2013100601579A CN201310060157A CN103106063A CN 103106063 A CN103106063 A CN 103106063A CN 2013100601579 A CN2013100601579 A CN 2013100601579A CN 201310060157 A CN201310060157 A CN 201310060157A CN 103106063 A CN103106063 A CN 103106063A
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transistor
input current
current source
transistors
output
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CN103106063B (en
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李泽宏
蒋汇
曾智
刘广涛
吴明进
张仁辉
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Abstract

The invention provides an analog multiplication and division method operational circuit and belongs to the analog circuit field. The analog multiplication and division method operational circuit comprises four transistors, three input current sources and output current, wherein the four transistors are connected through Darlinton pipes or Darlinton type pipes and formed by audions. When the four transistors are in N-type semiconductor P-type semiconductor N-type semiconductor (NPN) types or P-type semiconductor N-type semiconductor P-type semiconductor (PNP) types, a positive end (or a negative end) of a first input current source is connected with base electrodes of a first transistor and a second transistor and a collector of a fourth transistor, a base electrode of the fourth transistor is connected with an emitting electrode of the first transistor and a negative end (or a positive end) of a second input current source, an emitting electrode of the second transistor is connected with a base electrode of a third transistor and a negative end (or a positive end) of a third input current source, the emitting electrodes of the third transistor and the fourth transistor are connected with the ground (or a power supply Vcc), and output current io is output from a collector of the third transistor. The analog multiplication and division method operational circuit achieves the multiplication and division operation function of two-way or three-way analog signals, and is simple in structure, small in output signal temperature coefficient, fast in operational speed, and suitable for integrated chips of bipolar, BiCMOS and boot configuration data (BCD) processes.

Description

A kind of simulation multiplication and division computing circuit
Technical field
The invention belongs to the mimic channel field, be specifically related to a kind of simulation multiplication and division computing circuit.
Background technology
Simulation multiplication and division circuit is to realize the function that multiplies each other or be divided by between two analog quantitys, it not only can be used for the computing to analog quantity, and can be used for simulating signal is changed and processed, therefore, be widely used in the fields such as communication system, measuring system, control system
Analog multiplier commonly used uses Gilbert cell mostly, as shown in Figure of description 3.Circuit is by controlling the image current i of transistor Q3 EE, i EEVariation cause the mutual conductance g of transistor Q1 and transistor Q2 mVariation, so this circuit is called again and becomes mutual conductance formula analog multiplier.Circuit output
v o = - Kv x v y , K = R D 2 RV T
Contain the amount V that is directly proportional to absolute temperature in coefficient due to the output Vo of this circuit T, temperature characterisitic is poor, and input and output are all voltage signals, has Miller effect, and arithmetic speed is slow.
The simulation division circuit utilizes the analog multiplier unit mostly, connects into form as shown in Figure 4.Therefore the problem that exists in analog multiplier still exists in analog divider, and circuit structure is complicated.And to realize three tunnel simulating signal multiplication and division computings, and need analog multiplier and divider are carried out cascade, further strengthened the complexity of circuit.
Summary of the invention
In order to solve the problems such as traditional analog multiplication/division device arithmetic speed is slow, circuit is complicated, the present invention proposes a kind of simulation multiplication and division computing circuit.This circuit can carry out multiplication or division arithmetic to the two-way simulating signal, also can carry out the multiplication and division computing to three tunnel simulating signals, and the circuit implementation is simple, and the Output rusults temperature coefficient is little, fast operation.
Technical scheme of the present invention is:
A kind of simulation multiplication and division computing circuit as shown in Figure 1, 2, comprises four transistors 11,12,13 and 14, three input current sources and an output current io; Described four transistors are Darlington transistor or are the triode formation that Darlington connects;
When four transistors are NPN transistor (as shown in Figure 1), the positive termination the first transistor 11 of the first input current source and the base stage of transistor seconds 12, connect simultaneously the collector of the 4th transistor 14, the base stage of the 4th transistor 14 connects the emitter of the first transistor and the negative terminal of the second input current source, the emitter of transistor seconds 12 connects the base stage of the 3rd transistor 13 and the negative terminal of the 3rd input current source, the grounded emitter of the 3rd transistor 13 and the 4th transistor 14, output current io is from the collector output of the 3rd transistor 13;
When four transistors are PNP transistor (as shown in Figure 2), the negative terminal of the first input current source connects the base stage of the first transistor 11 and transistor seconds 12, connect simultaneously the collector of the 4th transistor 14, the base stage of the 4th transistor 14 connects the emitter of the first transistor and the anode of the second input current source, the emitter of transistor seconds 12 connects the base stage of the 3rd transistor 13 and the anode of the 3rd input current source, the emitter of the 3rd transistor 13 and the 4th transistor 14 connects power Vcc, and output current io is from the collector output of the 3rd transistor 13.
Need to prove:
1, four transistors 11 ~ 14 in simulation multiplication and division computing circuit of the present invention can be both Darlington transistors, can be also to be connected by the Darlington that triode consists of.
2, simulation multiplication and division computing circuit of the present invention is electric current input and output type simulated multiplication and division computing circuit
Beneficial effect of the present invention: simulation multiplication and division computing circuit provided by the invention is compared with multiplication/division device commonly used, circuit structure is more simple, the Output rusults temperature coefficient is little, input and output are current signal, there is no Miller effect, fast operation is applicable to the integrated chip based on Bipolar, BiCMOS and BCD technique.
Description of drawings
Fig. 1 is that a kind of simulation multiplication and division of the present invention computing circuit is realized circuit with NPN transistor.
Fig. 2 is that a kind of simulation multiplication and division of the present invention computing circuit is realized circuit with the PNP transistor.
Fig. 3 is traditional analog multiplier.
Fig. 4 is traditional analog divider.
Fig. 5 is the current relationship curve of the concrete implementing circuit of the present invention.
Fig. 6 is the output current of the concrete implementing circuit of the present invention and the relation curve of temperature.
Embodiment
Below in conjunction with accompanying drawing, take NPN transistor as specific embodiment, the present invention is described in further details.
A kind of simulation multiplication and division computing circuit as shown in Figure 1, comprises four transistors 11,12,13 and 14, three input current sources and an output current io; Described four transistors are Darlington transistor or are the triode formation that Darlington connects;
Four transistors are NPN transistor, the positive termination the first transistor 11 of the first input current source and the base stage of transistor seconds 12, connect simultaneously the collector of the 4th transistor 14, the base stage of the 4th transistor 14 connects the emitter of the first transistor and the negative terminal of the second input current source, the emitter of transistor seconds 12 connects the base stage of the 3rd transistor 13 and the negative terminal of the 3rd input current source, the grounded emitter of the 3rd transistor 13 and the 4th transistor 14, output current io is from the collector output of the 3rd transistor 13.
The below sets forth principle of work of the present invention:
By formula I o = I s exp ( q V be kT ) And I o=I c/ 3,
V be ( 101 ) = kT q ln i 1 I s ( 101 ) , V be ( 111 ) = kT q ln i 1 β ( 101 ) · I s ( 111 )
V be ( 102 ) = kT q ln i 2 I s ( 102 ) , V be ( 112 ) = kT q ln i 2 β ( 102 ) · I s ( 112 )
V be ( 103 ) = kT q ln i 3 I s ( 103 ) , V be ( 113 ) = kT q ln i 3 β ( 103 ) · I s ( 113 )
V be ( 104 ) = kT q ln io I s ( 104 ) , V be ( 114 ) = kT q ln io β ( 104 ) · I s ( 114 )
Due to
V be(101)+V be(111)+V be(102)+V be(112)=V be(103)+V be(113)+V be(104)+V be(114)
So
i o = i 1 · i 2 · I s ( 103 ) · I s ( 104 ) · I s ( 113 ) · I s ( 114 ) · β ( 103 ) · β ( 104 ) i 3 · I s ( 101 ) · I s ( 102 ) I s ( 111 ) · I s ( 112 ) · β ( 101 ) · β ( 102 )
When 101 ~ 104 and 111 ~ 114 being one species transistor npn npn and coupling fully, and 101 ~ 104 be operated in I 3In-beta curve, during the flat site of β, β is almost irrelevant with electric current, this season
k 1 = I s ( 103 ) · I s ( 104 ) · I s ( 113 ) · I s ( 114 ) I s ( 101 ) · I s ( 102 ) · I s ( 111 ) · I s ( 112 ) = n ( 103 ) · n ( 104 ) · n ( 113 ) · n ( 114 ) n ( 101 ) · n ( 102 ) · n ( 111 ) · n ( 112 )
N wherein (101)~ n (104)n (111)n (114)The number of difference transistor 101~104,111 ~ 114.{。##.##1},
i o = k 1 · i 1 · i 2 i a
Coefficient k 1 is only relevant with 101~104,111~114 number, and is temperature independent.
As input current i1, the i2 of three input current sources, when i3 is variable input, this circuit has been realized the simulation multiplication and division computing to three road analog input signals.
When the input current i3 of the 3rd input current current source was the bias current of fixing, this circuit had been realized the analogue multiplication computing to the two-way simulating signal, output i o=k2i 1I 2, k2=k1/i 3
During for fixing bias current, this circuit has been realized the simulation division computing to the two-way simulating signal, output as the input current i2 of the input current i1 of the first input current source or the second input current source
i o=k3i 1/ i 3, k3=k1i 2Or i o=k3i 2/ i 3, k3=k1i 1
To i1, i2, i3, the current relationship of io carries out emulation.Fig. 5 is that to get transistor 101 ~ 104,111 ~ 114 numbers be all 1, i3=1.5uA, and i2 gets a value every 500nA between 500nA ~ 3uA, and the output current io that scanning obtains is with the situation of change of i1.As we can see from the figure, current i 1, i2, i3 satisfies relation between io
Figure BDA00002860527800041
K=1 herein.
Fig. 6 is the relation curve of output current io and temperature.In concrete implementing circuit figure shown in Figure 1, simulation parameter is set as follows: transistor 101 ~ 104,111 ~ 114 numbers are all 1, i1=3uA, i2=2uA, i3=1.5uA.See output current io=3.94uA in the time of-40 ℃ from curve; In the time of 125 ℃, output current io=4.173uA.In the temperature range of-40 ℃ ~ 125 ℃, the output current that is caused by temperature variation changes less than ± 3%.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (1)

1. a simulation multiplication and division computing circuit, comprise four transistors (11,12,13 and 14), three input current sources and an output current io; Described four transistors are Darlington transistor or are the triode formation that Darlington connects;
when four transistors are NPN transistor, the positive termination the first transistor (11) of the first input current source and the base stage of transistor seconds (12), connect simultaneously the collector of the 4th transistor (14), the base stage of the 4th transistor (14) connects the emitter of the first transistor and the negative terminal of the second input current source, the emitter of transistor seconds (12) connects the base stage of the 3rd transistor (13) and the negative terminal of the 3rd input current source, the grounded emitter of the 3rd transistor (13) and the 4th transistor (14), output current io is from the collector output of the 3rd transistor (13),
when four transistors are PNP transistor, the negative terminal of the first input current source connects the base stage of the first transistor (11) and transistor seconds (12), connect simultaneously the collector of the 4th transistor (14), the base stage of the 4th transistor (14) connects the emitter of the first transistor and the anode of the second input current source, the emitter of transistor seconds (12) connects the base stage of the 3rd transistor (13) and the anode of the 3rd input current source, the emitter of the 3rd transistor (13) and the 4th transistor (14) connects power Vcc, output current io is from the collector output of the 3rd transistor (13).
CN201310060157.9A 2013-02-26 2013-02-26 A kind of simulation multiplication and division computing circuit Expired - Fee Related CN103106063B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112583399A (en) * 2021-02-23 2021-03-30 上海南芯半导体科技有限公司 High-precision analog multiplier-divider
CN115016580A (en) * 2022-05-16 2022-09-06 电子科技大学 Current divider with wide input range

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3500032A (en) * 1968-02-09 1970-03-10 Ibm Analog multiplier,divider,variable gain element
EP0623993B1 (en) * 1993-04-08 1997-11-19 Philips Electronics Uk Limited Four quadrant multiplier circuit and a receiver including such a circuit
CN1208203A (en) * 1997-03-28 1999-02-17 日本电气株式会社 Composite transistor, composite-transistor pair, current squarer, and CMOS analog multiplier
CN1326164A (en) * 2000-05-30 2001-12-12 松下电器产业株式会社 Analog multiply circuit and gain variable amplify circuit
CN101387895A (en) * 2007-09-12 2009-03-18 上海源赋创盈电子科技有限公司 Current mirror and novel non-linearity multiplier composed of the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3500032A (en) * 1968-02-09 1970-03-10 Ibm Analog multiplier,divider,variable gain element
EP0623993B1 (en) * 1993-04-08 1997-11-19 Philips Electronics Uk Limited Four quadrant multiplier circuit and a receiver including such a circuit
CN1208203A (en) * 1997-03-28 1999-02-17 日本电气株式会社 Composite transistor, composite-transistor pair, current squarer, and CMOS analog multiplier
CN1326164A (en) * 2000-05-30 2001-12-12 松下电器产业株式会社 Analog multiply circuit and gain variable amplify circuit
CN101387895A (en) * 2007-09-12 2009-03-18 上海源赋创盈电子科技有限公司 Current mirror and novel non-linearity multiplier composed of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112583399A (en) * 2021-02-23 2021-03-30 上海南芯半导体科技有限公司 High-precision analog multiplier-divider
CN115016580A (en) * 2022-05-16 2022-09-06 电子科技大学 Current divider with wide input range
CN115016580B (en) * 2022-05-16 2023-02-28 电子科技大学 Current divider with wide input range

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