CN103105885A - Circuit producing reference voltage of high voltage - Google Patents
Circuit producing reference voltage of high voltage Download PDFInfo
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- CN103105885A CN103105885A CN2012105863408A CN201210586340A CN103105885A CN 103105885 A CN103105885 A CN 103105885A CN 2012105863408 A CN2012105863408 A CN 2012105863408A CN 201210586340 A CN201210586340 A CN 201210586340A CN 103105885 A CN103105885 A CN 103105885A
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Abstract
The invention provides a circuit producing reference voltage of high voltage. The circuit producing the reference voltage of the high voltage comprises a first N-channel metal oxide semiconductor (NMOS) tube, a second NMOS tube, a first resistor and a second resistor. A grid electrode of the first NMOS tube is connected with reference voltage of low voltage, a source electrode of the first NMOS tube is connected with one end of the first resistor, and the other end of the first resistor is connected with the ground. A substrate of the first NMOS tube is connected with the source electrode of the first NMOS tube. A source electrode of the second NMOS tube is connected with a drain electrode of the first NMOS tube, and a common connection point of the source electrode of the second NMOS tube and the drain electrode of the first NMOS tube is connected with an output end of the circuit producing the reference voltage of the high voltage. A substrate of the second NMOS tube is connected with the source electrode of the second NMOS tube, and a grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube. A connection joint of the grid electrode of the second NMOS tube and the drain electrode of the second NMOS tube is connected with one end of the second resistor, and the other end of the second resistor is connected with a power source end. Besides, the invention further provides a circuit producing reference voltage of another high voltage. The circuit producing the reference voltage of the high voltage is capable of producing the reference voltage based on any high voltage, so that repeated production of a set of complex reference voltage circuit is avoided, a circuit structure is simplified, and a chip area is saved.
Description
Technical field
The present invention relates to the reference voltage generating circuit technical field in Analogous Integrated Electronic Circuits, specifically, the present invention relates to a kind of circuit that produces reference voltage based on arbitrary high pressure.
Background technology
In field of analog integrated circuit, often relate to voltage detecting and current detecting.Testing circuit need to have reference voltage V ref accurately, then voltage to be detected and this reference voltage is obtained output state by comparer.If need voltage relatively based on voltage be not ground voltage, this moment, corresponding reference voltage also need to produce based on non-ground voltage.
Such as in the application scheme of multisection lithium battery protection, need to detect voltage of batteries, therefore also need to produce the reference voltage V ref1-Vref4 based on the terminal potential VC1-VC4 of each batteries.Fig. 1 is a schematic diagram that is used for the voltage detecting circuit of multiple batteries of the prior art.As shown in Figure 1, if still adopt traditional band gap (bandgap) circuit to produce reference voltage V ref1-Vref4, need many cover band gap circuit.Because a cover band gap circuit is comparatively complicated, if in order to produce these reference voltage V ref1-Vref4, the many covers of design band gap circuit can be wasted chip area undoubtedly, increases complexity in circuits, means that also chip power-consumption is larger simultaneously.
Summary of the invention
In order to overcome this difficulty, the present invention adopts comparatively simple circuit can realize other several reference voltages based on terminal potential VC1-VC4 on the basis of existing reference voltage over the ground.
Be that technical matters to be solved by this invention is to provide a kind of high pressure reference voltage generating circuit, can produce reference voltage based on arbitrary high pressure, avoid again doing a complicated reference voltage circuit of cover, simplify circuit structure, save chip area.
For solving the problems of the technologies described above, the invention provides a kind of high pressure reference voltage generating circuit, comprising: a NMOS pipe, the 2nd NMOS pipe, the first resistance and the second resistance; Wherein,
The grid of a described NMOS pipe connects a low pressure reference voltage, and the source electrode of a described NMOS pipe connects an end of described the first resistance, the other end ground connection of described the first resistance, the substrate of a described NMOS pipe and its source shorted;
The source electrode of described the 2nd NMOS pipe connects the drain electrode of a described NMOS pipe, both common joints are connected to the output terminal of described high pressure reference voltage generating circuit, the substrate of described the 2nd NMOS pipe and its source shorted, the grid of described the 2nd NMOS pipe and its drain electrode short circuit, the grid of described the 2nd NMOS pipe and the common joint of its drain electrode are connected to an end of described the second resistance, and the other end of described the second resistance connects a power end.
Alternatively, the consistent size of a described NMOS pipe and described the 2nd NMOS pipe.
Alternatively, described the first resistance is identical with the resistance of described the second resistance.
For solving the problems of the technologies described above, the present invention also provides a kind of high pressure reference voltage generating circuit, comprising: a PMOS pipe, the 2nd PMOS pipe, the first resistance and the second resistance; Wherein,
The grid of a described PMOS pipe connects the reference voltage based on a power end, and the source electrode of a described PMOS pipe connects an end of described the first resistance, another power end of another termination of described the first resistance, the substrate of a described PMOS pipe and its source shorted;
The source electrode of described the 2nd PMOS pipe connects the drain electrode of a described PMOS pipe, both common joints are connected to the output terminal of described high pressure reference voltage generating circuit, the substrate of described the 2nd PMOS pipe and its source shorted, the grid of described the 2nd PMOS pipe and its drain electrode short circuit, the grid of described the 2nd PMOS pipe and the common joint of its drain electrode are connected to an end of described the second resistance, and the other end of described the second resistance connects an arbitrary voltage.
Alternatively, the consistent size of a described PMOS pipe and described the 2nd PMOS pipe.
Alternatively, described the first resistance is identical with the resistance of described the second resistance.
Compared with prior art, the present invention has the following advantages:
The existing low pressure reference voltage (Vref4) over the ground of high pressure reference voltage generating circuit of the present invention utilization, can produce very simply the reference voltage (Vref1, Vref2 and Vref3) based on other voltage (VC2, VC3 and VC4), thereby avoid again doing a complicated reference voltage circuit of cover, simplify circuit structure, saved the area of chip.
This circuit of the present invention can be widely used in the generation based on reference voltage in the comparator circuit of high pressure, as high crosstalk cell voltage testing circuit in multiple batteries etc.
Description of drawings
The above and other features of the present invention, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, wherein:
Fig. 1 is a schematic diagram that is used for the voltage detecting circuit of multiple batteries of the prior art;
Fig. 2 is the high pressure reference voltage generating circuit of first embodiment of the invention;
Fig. 3 is the high pressure reference voltage generating circuit of second embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings; set forth in the following description more details so that fully understand the present invention; but the present invention obviously can implement with the multiple alternate manner that is different from this description; those skilled in the art can be in the situation that do similar popularization, deduction without prejudice to intension of the present invention according to practical situations, therefore should be with content constraints protection scope of the present invention of this specific embodiment.
The first embodiment of high pressure reference voltage generating circuit
Fig. 2 is the high pressure reference voltage generating circuit of first embodiment of the invention.It should be noted that this accompanying drawing all only as example, it is not to be to draw according to the condition of equal proportion, and should not be construed as limiting as the protection domain to actual requirement of the present invention with this.
As shown in Figure 2, this high pressure reference voltage generating circuit 200 mainly comprises: a NMOS pipe M1, the 2nd NMOS pipe M2, the first resistance R 1 and the second resistance R 2.Wherein, the grid of a NMOS pipe M1 meets a low pressure reference voltage V in, and the source electrode of a NMOS pipe M1 connects an end of the first resistance R 1, the other end ground connection of the first resistance R 1, substrate and its source shorted of a NMOS pipe M1.
And the source electrode of the 2nd NMOS pipe M2 connects the drain electrode of a NMOS pipe M1, both common joints are connected to the output end vo ut of high pressure reference voltage generating circuit 200, substrate and its source shorted of the 2nd NMOS pipe M2, grid and its drain electrode short circuit of the 2nd NMOS pipe M2, the grid of the 2nd NMOS pipe M2 and the common joint of its drain electrode are connected to an end of the second resistance R 2, and the other end of the second resistance R 2 connects a power end VDD.So just, produced the reference voltage V out(Vref1 based on this power end VDD), this reference voltage V out=VDD-Vin.
In the present embodiment, the consistent size of a NMOS pipe M1 and the 2nd NMOS pipe M2, and their source electrode and the equal short circuit of substrate, so their source electrode and the equal short circuit of substrate, so they also have identical threshold voltage.An other NMOS pipe M1 and the 2nd NMOS pipe M2 have same current at same branch road, equate therefore a NMOS pipe M1 and the 2nd NMOS manage the gate source voltage Vgs of M2, i.e. Vgs1=Vgs2.
In addition, in the present embodiment, the first resistance R 1 is identical with the resistance of the second resistance R 2, on same branch road, has same current, thus the pressure drop VR on the first resistance R 1 and the second resistance R 2 equate, i.e. VR1=VR2.And Vin=Vgs1+VR1, therefore VDD-Vout=Vgs2+VR2 is Vin=VDD-Vout, i.e. Vout=VDD-Vin.
Thereby by existing reference voltage V in over the ground, produced the reference voltage to VDD.
This structure can reach the certain predetermined value as the pressure reduction that will detect VDD and a voltage Vx and produce marking signal for detection of the VDD associated voltage, if only have reference voltage over the ground, because VDD can change, is difficult to realize this comparison.Produce VDD-Vref by top circuit, Vx and this voltage are directly passed through common comparer, can realize this measuring ability.Thereby avoided the complexity of circuit.
The second embodiment of high pressure reference voltage generating circuit
Fig. 3 is the high pressure reference voltage generating circuit of second embodiment of the invention.It should be noted that this accompanying drawing all only as example, it is not to be to draw according to the condition of equal proportion, and should not be construed as limiting as the protection domain to actual requirement of the present invention with this.
In addition, the present embodiment is continued to use element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has optionally omitted the explanation of some constructed content.Explanation about clipped can be with reference to previous embodiment, and the present embodiment no longer repeats to give unnecessary details.
As shown in Figure 3, this high pressure reference voltage generating circuit 300 mainly comprises: a PMOS pipe M1, the 2nd PMOS pipe M2, the first resistance R 1 and the second resistance R 2.Wherein, the grid of the one PMOS pipe M1 meets the reference voltage V in based on a power end (VDD in embodiment illustrated in fig. 1), the source electrode of the one PMOS pipe M1 connects an end of the first resistance R 1, another power end of another termination VDD of the first resistance R 1, substrate and its source shorted of a PMOS pipe M1.
And the source electrode of the 2nd PMOS pipe M2 connects the drain electrode of a PMOS pipe M1, both common joints are connected to the output end vo ut of high pressure reference voltage generating circuit 300, substrate and its source shorted of the 2nd PMOS pipe M2, grid and its drain electrode short circuit of the 2nd PMOS pipe M2, the grid of the 2nd PMOS pipe M2 and the common joint of its drain electrode are connected to an end of the second resistance R 2, and the other end of the second resistance R 2 connects an arbitrary voltage VC.So just, produced based on VC(VC2, VC3 or VC4) reference voltage V out(Vref2, Vref3), this reference voltage V out=VC+(VDD-Vin).
In the present embodiment, a PMOS pipe M1 and the 2nd PMOS pipe M2 have identical size, and their source electrode and the equal short circuit of substrate, so they also have identical threshold voltage.In addition, a PMOS pipe M1 and the 2nd PMOS pipe M2 have same current at same branch road, equate therefore a PMOS pipe M1 and the 2nd PMOS manage the gate source voltage Vsg of M2, i.e. Vsg1=Vsg2.
In addition, in the present embodiment, the first resistance R 1 is identical with the second resistance R 2 resistances, on same branch road, has same current, thus the pressure drop VR on the first resistance R 1 and the second resistance R 2 equate, i.e. VR1=VR2.Therefore obtain: VDD-Vin=Vout-VC, i.e. Vout=VC+ (VDD-Vin).
Wherein VDD-Vin is the master reference magnitude of voltage, is designated as Vref, and Vin can produce by the circuit of Fig. 2.By this circuit, can produce the reference voltage V C+Vref based on free voltage VC.In actual applications, if the detection voltage of comparer is based on the voltage on VC, can adopt the circuit generation of Fig. 3 based on the reference voltage V C+Vref of VC, then the voltage ratio of direct and needs detection.
Below in conjunction with multisection lithium battery voltage detection mode in Fig. 1 further describe Fig. 2 and embodiment illustrated in fig. 3 in high pressure reference voltage generating circuit 200,300 application at the voltage detecting circuit of multiple batteries.
Need the voltage of comparison that Vd1 and Vref1 are arranged in Fig. 1, Vd2 and Vref2, Vd3 and Vref3, Vd4 and Vref4.Wherein Vd4 and Vref4 are direct level based on ground, can directly compare, and the generation of all the other reference voltage V ref1 ~ Vref3 is difficult point.According to content of the present invention, can realize easily that this three reference voltage V ref1 ~ Vref3 produces, and then uses common comparer namely can realize the comparison of these three groups of voltages.
Circuit by in Fig. 2 changes VDD into VC1, and Vin adds reference voltage V ref4 over the ground, namely can realize Vref1=VC1-Vref4, and this voltage and Vd1 directly compare, and can realize the detection of first segment cell voltage.
Adopt the circuit in Fig. 3, the Vin input adds Vref1 voltage, and VC meets VC3, can produce Vref2=VC3+Vref4, and this voltage and Vd2 directly compare, and can realize the detection of second section cell voltage.
In like manner, continue to adopt the circuit in Fig. 3, the Vin input adds Vref1 voltage, and VC meets VC4, can produce Vref3=VC4+Vref4, and this voltage and Vd3 directly compare, and can realize the detection of the 3rd batteries voltage.
The existing low pressure reference voltage (Vref4) over the ground of high pressure reference voltage generating circuit of the present invention utilization, can produce very simply the reference voltage (Vref1, Vref2 and Vref3) based on other voltage (VC2, VC3 and VC4), thereby avoid again doing a complicated reference voltage circuit of cover, simplify circuit structure, saved the area of chip.
This circuit of the present invention can be widely used in the generation based on reference voltage in the comparator circuit of high pressure, as high crosstalk cell voltage testing circuit in multiple batteries etc.
Although the present invention with preferred embodiment openly as above, it is not to limit the present invention, and any those skilled in the art can make possible change and modification without departing from the spirit and scope of the present invention.Therefore, every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any modification, equivalent variations and modification that above embodiment does, within all falling into the protection domain that claim of the present invention defines.
Claims (6)
1. a high pressure reference voltage generating circuit (200), comprising: a NMOS pipe (M1), the 2nd NMOS pipe (M2), the first resistance (R1) and the second resistance (R2); Wherein,
The grid of a described NMOS pipe (M1) connects a low pressure reference voltage (Vin), the source electrode of a described NMOS pipe (M1) connects an end of described the first resistance (R1), the other end ground connection of described the first resistance (R1), substrate and its source shorted of a described NMOS pipe (M1);
The source electrode of described the 2nd NMOS pipe (M2) connects the drain electrode of a described NMOS pipe (M1), both common joints are connected to the output terminal (Vout) of described high pressure reference voltage generating circuit (200), substrate and its source shorted of described the 2nd NMOS pipe (M2), grid and its drain electrode short circuit of described the 2nd NMOS pipe (M2), the grid of described the 2nd NMOS pipe (M2) and the common joint of its drain electrode are connected to an end of described the second resistance (R2), and the other end of described the second resistance (R2) connects a power end (VDD).
2. high pressure reference voltage generating circuit according to claim 1 (200), is characterized in that, the consistent size of a described NMOS pipe (M1) and described the 2nd NMOS pipe (M2).
3. high pressure reference voltage generating circuit according to claim 1 (200), is characterized in that, described the first resistance (R1) is identical with the resistance of described the second resistance (R2).
4. a high pressure reference voltage generating circuit (300), comprising: a PMOS pipe (M1), the 2nd PMOS pipe (M2), the first resistance (R1) and the second resistance (R2); Wherein,
The grid of a described PMOS pipe (M1) connects the reference voltage (Vin) based on a power end, the source electrode of a described PMOS pipe (M1) connects an end of described the first resistance (R1), another power end of another termination (VDD) of described the first resistance (R1), substrate and its source shorted of a described PMOS pipe (M1);
The source electrode of described the 2nd PMOS pipe (M2) connects the drain electrode of a described PMOS pipe (M1), both common joints are connected to the output terminal (Vout) of described high pressure reference voltage generating circuit (300), substrate and its source shorted of described the 2nd PMOS pipe (M2), grid and its drain electrode short circuit of described the 2nd PMOS pipe (M2), the grid of described the 2nd PMOS pipe (M2) and the common joint of its drain electrode are connected to an end of described the second resistance (R2), and the other end of described the second resistance (R2) connects an arbitrary voltage (VC).
5. high pressure reference voltage generating circuit according to claim 4 (300), is characterized in that, the consistent size of a described PMOS pipe (M1) and described the 2nd PMOS pipe (M2).
6. high pressure reference voltage generating circuit according to claim 4 (300), is characterized in that, described the first resistance (R1) is identical with the resistance of described the second resistance (R2).
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| CN201210586340.8A CN103105885B (en) | 2012-12-28 | 2012-12-28 | Circuit producing reference voltage of high voltage |
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| CN201210586340.8A CN103105885B (en) | 2012-12-28 | 2012-12-28 | Circuit producing reference voltage of high voltage |
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| CN103105885B CN103105885B (en) | 2014-09-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416968A (en) * | 2019-08-09 | 2019-11-05 | 无锡启腾电子科技有限公司 | A kind of electrical fuse and its working method |
| CN113364436A (en) * | 2021-06-24 | 2021-09-07 | 中颖电子股份有限公司 | Voltage comparison circuit |
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| JPS60181806A (en) * | 1984-02-28 | 1985-09-17 | Sharp Corp | Reference voltage circuit |
| CN101051841A (en) * | 2007-02-06 | 2007-10-10 | 复旦大学 | Window type parallel modulus converter suitable for digital power controller |
| JP2009265955A (en) * | 2008-04-25 | 2009-11-12 | Hitachi Ulsi Systems Co Ltd | Semiconductor integrated circuit |
| CN101702514A (en) * | 2009-11-26 | 2010-05-05 | 北京中星微电子有限公司 | Battery protection control device |
| CN101902215A (en) * | 2010-08-02 | 2010-12-01 | 中颖电子有限公司 | Four-input terminal comparator |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS60181806A (en) * | 1984-02-28 | 1985-09-17 | Sharp Corp | Reference voltage circuit |
| CN101051841A (en) * | 2007-02-06 | 2007-10-10 | 复旦大学 | Window type parallel modulus converter suitable for digital power controller |
| JP2009265955A (en) * | 2008-04-25 | 2009-11-12 | Hitachi Ulsi Systems Co Ltd | Semiconductor integrated circuit |
| CN101702514A (en) * | 2009-11-26 | 2010-05-05 | 北京中星微电子有限公司 | Battery protection control device |
| CN101902215A (en) * | 2010-08-02 | 2010-12-01 | 中颖电子有限公司 | Four-input terminal comparator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416968A (en) * | 2019-08-09 | 2019-11-05 | 无锡启腾电子科技有限公司 | A kind of electrical fuse and its working method |
| CN113364436A (en) * | 2021-06-24 | 2021-09-07 | 中颖电子股份有限公司 | Voltage comparison circuit |
| CN113364436B (en) * | 2021-06-24 | 2023-11-07 | 中颖电子股份有限公司 | Voltage comparison circuit |
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| CN103105885B (en) | 2014-09-17 |
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