CN103095448B - A kind of processing method of digitized signal - Google Patents

Abstract

The invention discloses a kind of processing method and device of digitized signal, its core methed is for mapping, sorting, search and recurrence.Be mainly used in digitized signal analyzing and processing, probability analysis, statistical nature extraction and hide, data ciphering and deciphering, trend analysis and judgement etc. aspect.The processing method of digitized signal of the present invention adopts fixed-point calculation, fixed DSP is coordinated to process, greatly can improve the speed of digitized signal process, give play to the disposal ability of DSP to greatest extent, to make in the cpu system using DSP overall performance between DSP and other chip or hardware obtain larger raising.The processing method of word signal of the present invention itself has effect of encryption to digitized signal simultaneously, obfuscator can be substituted in some cases .. use, entirely prevented some utilizes language statistics rule to carry out the method cracked, the danger that the signal preventing some important or data are cracked and reveal.

Description

A kind of processing method of digitized signal

Technical field

The present invention relates to a kind of processing method and device of digitized signal, belong to signal processing analysis technical field.

Background technology

In digital information process; we often can use various algorithm; such as common all kinds of encryption-decryption algorithm; such as fourier transform algorithm (FFT DFT) etc.; in different application scenarios and field; adopt suitable data algorithm, various different target can be realized.At present the process of digitized signal is adopted more to the method process of floating-point operation, but because computer can only store integer, for the digitized signal process of magnanimity, general floating-point operation may be very slow and have error, cannot meet process and the analysis of the digitized signal of high request, and DSP cannot play its maximum effect; And also cannot encrypt in pretreatment process for some important data.

Summary of the invention

The present invention has designed and developed a kind of processing method of digitized signal and the digitized signal processing unit based on DSP.Digitized signal is all encrypted with fixed-point calculation process by the method in of the present invention, improves the efficiency of digitized signal process, accuracy and fail safe.

Technical scheme provided by the invention is:

A processing method for digitized signal, is characterized in that, comprising:

Step 1, front-end system receive raw digitized signal and it are transferred to DSP by transmission system;

Step 2, on described DSP, for the described raw digitized signal data received, carry out rough estimates, determine the basic set of all individual elements comprised in described raw digitized signal; Each individual element in described basic set maps the natural number of an order from m one by one by its order in described basic set, and set up a basic data collection, the natural carry system in wherein said basic data collection is the decimal system;

N element in step 3, described raw digitized signal, its numerical value in described basic data collection corresponding, generates a 0 rank something lost sequence be made up of n natural number by its order in described raw digitized signal;

The 1st number in step 4, described 0 rank something lost sequence is to start sequence last position of described basic data collection or first, obtain actual bit sequence, described actual bit sequence adds that m-1 obtains sequential bits sequence, described 1st number is placed on described basic data collection last and number identical with described 1st number in described basic data collection is eliminated, generate the first basic data collection, and eliminate 0 rank and lose described 1st number in sequence and the sequential bits sequence of described 1st number be placed on first that sequence is lost on described 0 rank, the 2nd number in sequence is lost on described 0 rank, to sort as stated above generation second basic data collection according to the order of described first basic data collection, and by according to the order of the first basic data collection and the sequential bits sequence of described 2nd number generated as stated above be placed on described 0 rank lose sequence second and eliminate described 2nd number, the like, described 0 rank are lost n-th in sequence and are counted with the order of the (n-1)th basic data collection and generation n-th basic data collection that sorts as stated above, and by according to the order of the (n-1)th basic data collection and the sequential bits sequence of described n-th number generated as stated above is placed on described 0 rank loses n-th of sequence and eliminate described n-th number, the sequential bits sequence of the element of each described raw digitized signal constitutes 1 rank and loses sequence,

Step 5, in the same way, the data 1 rank being lost to sequence process, and can obtain 2 rank and lose sequences, same, can obtain n rank and lose sequence, and the process of the first number that wherein every arbitrary order is lost in sequence is all start with described basic data collection;

The n rank of described generation are lost sequence and are outputted to aftertreatment systems place by step 6, described DSP, directly as a result or auxiliary data, carry out subsequent treatment.

Based on a processing unit for the digitized signal of DSP, it is characterized in that, comprising:

At least one dsp chip, it connects described front-end system and the first synchronous DRAM;

Described front-end system comprises: FPGA, the second synchronous DRAM, the 3rd synchronous DRAM, FLASH memory, A/D converter, ARM chip, power supply, USB HOST, JTAG, DM9000, RS232 and RS485, described FPGA connects described dsp chip, ARM chip, power supply, the second synchronous DRAM and A/D converter, and described ARM chip connects described USB HOST, JTAG, DM9000, RS232, RS485, FLASH memory the 3rd synchronous DRAM and aftertreatment systems.

Beneficial effect of the present invention: the processing method of digitized signal of the present invention all adopts fixed-point calculation to add the accuracy of digitized signal process, improve the speed of digitized signal process, give play to the disposal ability of DSP-especially fixed DSP to greatest extent, thus also improve the operating efficiency of other chip or the hardware be used in conjunction with DSP.The sequence taked due to method itself, to search and recurrence all belongs to most rudimentary algorithm, possess the time complexity of strict and steady, be strict with at some, with the application scenario of time correlation, there is great meaning.The processing method of word signal of the present invention itself has effect of encryption to digitized signal simultaneously, obfuscator can be substituted in some cases .. use, entirely prevented some utilizes language statistics rule to carry out the method cracked, its strict precise time complexity correlation simultaneously, Brute Force method can be prevented completely, the danger that the signal preventing some important or data are cracked and reveal.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of the processing method of a kind of digitized signal of the present invention.

Fig. 2 is the processing unit structure chart of a kind of digitized signal based on DSP of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail, can implement according to this with reference to specification word to make those skilled in the art.

Embodiment 1

As shown in Figure 1, the invention provides a kind of method of digitized signal, comprising:

Step 1, front-end system receive raw digitized signal " ebdaacaehfbihcebiiid " and it are transferred to DSP by transmission system;

Step 2, on DSP, raw digitized signal is " ebdaacaehfbihcebiiid ", its basic set a, b, c, d, e, f, g, h, I, j}, the basic that basic set is converted to is combined into { 0,1,2,3,4,5,6,7,8,9};

Sequence is lost on 0 rank that the corresponding basic data collection of step 3, raw digitized signal is mapped as " 41300204751872418883 ";

Step 4, start that the data of sequence are lost to 0 rank and process, for initial elementary data set { 0,1,2,3,4,5,6,7,8,9}, first to be processed digital 4 in initial basic set actual bit sequence be 6, this is by reverse process-number from back to front, it is 5 that actual bit sequence adds that 0-1 obtains sequential bits sequence, is placed on first that sequence is lost on 0 rank by 5, and the first number lost in sequence is eliminated by 0 rank, then after being placed on basic data collection 4, be then 01234567894, repeat before removing, the first basic is combined into 0123567894; Second numeral to be processed is 1, actual bit sequence in the first basic data collection from its last is the 9th, then corresponding convertible sequential bits sequence is 8, be placed on 0 rank lose the second of sequence by 8 and eliminate 0 rank and lose the 2nd number in sequence, then after being placed on the first basic data collection 1, be then 01235678941, repeat before removing, the second basic is combined into 0235678941; Successively be disposed, it is 58790914796836544007 that order sequenced data is lost on 1 rank obtained;

Step 5, oppositely losing order sequenced data 58790914796836544007 to 1 rank, is that the basic data collection initially arrived carries out same process with 0123456789, can obtain 2 rank and lose order sequenced data: 42339197437682860807; The like, any n rank can be obtained and lose order sequenced data;

The n rank of described generation are lost sequence and are outputted to aftertreatment systems place by step 6, DSP, directly as a result or auxiliary data, carry out subsequent treatment.

Order sequenced data (n > 0) is lost to any n rank, carries out inverse operation, n-1 rank can be obtained and lose order sequenced data, until obtain 0 rank to lose order sequenced data, then carry out simple static mappings replacement, original signal data can be restored.

From processing procedure, when processing each data, all need the determination first carrying out basic set, then be search computing, each process is all map process one to one, but each mapping is all completely different, and operating reversible, each operation all has metastable time complexity, and according to statistics, if adopt forward and reverse mixed processing, for any large data, this operation all possesses obscures function, according to what time above, this algorithm possesses very important feature in encrypting and decrypting field, has great application prospect.

For trigonometric function (such as sinusoidal or cosine) or various types of signal data such as square wave, triangular wave, if carry out losing sequence process (forward or backwards simple) to its data, then the statistical law of order sequenced data is lost clearly in its each rank, can use in application scenarios such as matching, filtering, frequency measurement, denoisings as householder method.

Embodiment 2

As shown in Figure 2, at least one dsp chip, it connects described front-end system and the first synchronous DRAM;

Front-end system comprises: FPGA, the second synchronous DRAM, the 3rd synchronous DRAM, FLASH memory, A/D converter, ARM chip, power supply, USB HOST, JTAG, DM9000, RS232 and RS485, described FPGA connects described dsp chip, ARM chip, power supply, the second synchronous DRAM and A/D converter, and described ARM chip connects described USB HOST, JTAG, DM9000, RS232, RS485, FLASH memory and the 3rd synchronous DRAM.

ARM is responsible for the input and output and the workflow management scheduling that process whole system, comprises the setting of initial configuration;

The data communication between the scheduling of sequence Processing tasks and DSP and ARM is specifically lost in the process of FPGA primary responsibility;

DSP can have single or multiple, generally determine according to the size of application data volume and the exponent number of process something lost sequence, namely the main task of DSP carries out the process of something lost sequence, comprise sequence is lost on 1 rank process to n rank, for the application of encrypting and decrypting, lose sequence process and cryptographic operation, lose reverse inverse operation and the decryption oprerations of sequence;

The input and output of device comprise the A/D processing module of USB, RS232, RS485, JTAG, Ethernet interface and exclusive data reception; For the input of the high speed large-scale digitization signal of some special occasions, provide the direct A/D processing module be connected with FPGA to receive data;

Device can carry out the synchronous of real time data or asynchronous process to receive data and to export data, also can carry out input to static or dynamic data and store, processes storage, export at any time.

Although embodiment of the present invention are open as above, but it is not restricted to listed in specification and execution mode utilization, it can be applied to various applicable the field of the invention completely, for those skilled in the art, can easily realize other amendment, therefore do not deviating under the universal that claim and equivalency range limit, the present invention is not limited to specific details and illustrates here and the legend described.

Claims (1)

1. a processing method for digitized signal, is characterized in that, comprising:

Step 1, front-end system receive raw digitized signal and it are transferred to DSP by transmission system;

Step 2, on described DSP, for the described raw digitized signal data received, carry out rough estimates, determine the basic set of all individual elements comprised in described raw digitized signal; Each individual element in described basic set maps the natural number of an order from m one by one by its order in described basic set, and set up a basic data collection, the natural carry system in wherein said basic data collection is the decimal system;

N element in step 3, described raw digitized signal, its numerical value in described basic data collection corresponding, generates a 0 rank something lost sequence be made up of n natural number by its order in described raw digitized signal;

The 1st number in step 4, described 0 rank something lost sequence is to start sequence last position of described basic data collection or first, obtain actual bit sequence, described actual bit sequence adds that m-1 obtains sequential bits sequence, described 1st number is placed on described basic data collection last and number identical with described 1st number in described basic data collection is eliminated, generate the first basic data collection, and eliminate 0 rank and lose described 1st number in sequence and the sequential bits sequence of described 1st number be placed on first that sequence is lost on described 0 rank, the 2nd number in sequence is lost on described 0 rank, to sort as stated above generation second basic data collection according to the order of described first basic data collection, and by according to the order of the first basic data collection and the sequential bits sequence of described 2nd number generated as stated above be placed on described 0 rank lose sequence second and eliminate described 2nd number, the like, described 0 rank are lost n-th in sequence and are counted with the order of the (n-1)th basic data collection and generation n-th basic data collection that sorts as stated above, and by according to the order of the (n-1)th basic data collection and the sequential bits sequence of described n-th number generated as stated above is placed on described 0 rank loses n-th of sequence and eliminate described n-th number, the sequential bits sequence of the element of each described raw digitized signal constitutes 1 rank and loses sequence,

Step 5, in the same way, the data 1 rank being lost to sequence process, and can obtain 2 rank and lose sequences, same, can obtain n rank and lose sequence, and the process of the first number that wherein every arbitrary order is lost in sequence is all start with described basic data collection;

The n rank of described generation are lost sequence and are outputted to aftertreatment systems place by step 6, described DSP, directly as a result or auxiliary data, carry out subsequent treatment.