CN103094216A - Annealing technology of NOR flash memory device and NOR flash memory device - Google Patents
Annealing technology of NOR flash memory device and NOR flash memory device Download PDFInfo
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- CN103094216A CN103094216A CN2013100109936A CN201310010993A CN103094216A CN 103094216 A CN103094216 A CN 103094216A CN 2013100109936 A CN2013100109936 A CN 2013100109936A CN 201310010993 A CN201310010993 A CN 201310010993A CN 103094216 A CN103094216 A CN 103094216A
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Abstract
The invention discloses annealing technology of a NOR flash memory device. The annealing technology of the NOR flash memory device comprises the following steps. In the process of forming a trap area, annealing is performed in a temperature changing manner, and specifically, temperature is lowered from 950 DEG C to 750 DEG C. In addition, the temperature is lowered in the slow and preferred speed of 2.5 DEG C per minute and oxygen is not included in annealing air. The invention further discloses the NOR flash memory device. A single step of technology optimization can greatly reduce static work currents of the NOR flash memory device, and therefore failure rate of the NOR flash memory device is greatly reduced.
Description
Technical field
The present invention relates to NOR flush memory device field, the NOR flush memory device that relates in particular to a kind of annealing process of NOR flush memory device and adopt this technique to make.
Background technology
The NOR flash memory is one of nonvolatile flash memory technology main on market.The NOR flush memory device provides high reliability and quick reading performance, is the choosing of carrying out code storage and the direct ideal of carrying out in mobile phone and other electronic devices.The NOR flush memory device is to the requirement of ICCSB (static working current) very high (ICCSB ﹤ 5 μ A, other similar products ﹤ 15 μ A).But more annealing process in the preparation process of NOR flush memory device, annealing has the effect that reduces stress, but the while of the L temperature drop temperature process in annealing process can produce stress to wafer again, cause the ICCSB of device larger, cause higher ICCSB failure rate.At present to reduce ICCSB by the interlock circuit layout design that client is changed light shield substantially.And be to relate to the functional verification of new edition light shield by the shortcoming that the interlock circuit layout design that client is changed light shield reduces ICCSB, and the cycle that needs is long, and the new light shield of design output, and cost compare is high.In addition, a little less than some client's designed capacity relative thin, the circuit design aspect can not effectively reduce ICCSB.
A kind of manufacture method of flash memory is disclosed for the Chinese patent of CN100514607C as Granted publication number, comprise silicon base is divided into isolated area and the district of having chance with, carry out Implantation and silicon base is carried out annealing process in the silicon base of active area and isolated area intersection, form the unit contact hole, make the unit contact hole be arranged in diffusion position line, reduce quiescent current thereby control by this method short-channel effect.This method is greatly improved for cost, and the effect of reduction quiescent current is subject to other factor interference.
Annealing process in NOR flush memory device preparation process is extremely important for reducing static working current, in the process that forms well region, will carry out the distribution situation that annealing process improves foreign atom after Implantation.In addition, in forming other technique of flush memory device, also to use annealing steps as oxide-film being adjusted into dense oxidation film etc.For annealing process, many improved measures are arranged also at present, the Chinese patent that is CN101872746A as publication number proposes to adopt ND3 annealing, make tunneling oxide layer and the silicon substrate dangling bonds at the interface can be saturated by silicon-deuterium key, unsettled silicon-hydrogen bond can be replaced by silicon-deuterium key simultaneously, so just greatly improve electrology characteristic at the interface, and then can improve the flush memory device reliability.
But present annealing process is the cycle annealing mode mostly, is so that wafer is annealed in the mode that a certain temperature spot stops certain hour, this annealing way can be in wafer residual more stress, affect the reduction of static working current.And all contain oxygen in present annealing way in annealing atmosphere, the existence of oxygen improves the activity of wafer surface, can increase stress in the heat treatment of annealing, causes higher static working current.
Summary of the invention
The object of the invention is to propose a kind of annealing process of NOR flush memory device, can solve the problem that the larger ICCSB of device causes higher ICCSB failure rate.
For reaching this purpose, the present invention by the following technical solutions:
A kind of annealing process of NOR flush memory device, be included in and form well region on Semiconductor substrate, described well region is annealed, it is characterized in that, described annealing is alternating temperature annealing, is namely under annealing atmosphere, second temperature of the first greenhouse cooling with temperature from 900-1000 ℃ in 700-800 ℃, complete the annealing to described well region, and do not contain O in described annealing atmosphere
2
Further, cooling is to be down to 750 ℃ from 950 ℃.
Further, cooling is to be down to 800 ℃ from 1000 ℃.
Further, cooling is to be down to 700 ℃ from 900 ℃.
Further, cooling rate is: 1-5 ℃/Min.
Further, cooling rate is preferably 2.5 ℃/Min.
The time of further, well region being annealed is 40-200Min.
Further, annealing time is preferably 90Min.
Further, annealing atmosphere is N
2
Further, N
2The flow of atmosphere is 15-18L/Min.
Further, N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Further, annealing is to carry out in continuous oven.
Further, the technique of described formation well region comprises and at first defines active area, then define the well region of difference in functionality by photoetching and injection, the well region of difference in functionality comprises high pressure P/N well region and low pressure P/N well region, and the integral body after defining the difference in functionality well region pushes away trap technique.
The present invention provides the NOR flush memory device that adopts above-mentioned annealing process to make simultaneously.
Compared with prior art, advantage of the present invention is with alternating temperature annealing and makes the such single-step process optimization of oxygen-free gas in annealing atmosphere effectively reduce the ICCSB of NOR flush memory device, thereby effectively reduce the failure rate of NOR flush memory device, do not need to change the interlock circuit layout design of light shield, proving period is short and can not increase extra cost.
Description of drawings
Fig. 1 is the annealing process flow chart of NOR flush memory device in the embodiment of the present invention.
Fig. 2 is the comparison diagram that contains the ICCSB failure rate of oxygen and oxygen-free NOR flush memory device in the embodiment of the present invention in annealing atmosphere.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.Be understandable that, specific embodiment described herein only is used for explaining the present invention, but not limitation of the invention.Also need to prove in addition, for convenience of description, only show part related to the present invention in accompanying drawing but not entire infrastructure.
In embodiments of the present invention, the processing step that forms the NOR flush memory device comprises: at first be formed with the step 101 in source region such as accompanying drawing 1 on Semiconductor substrate, then define the step 102 of well region such as the accompanying drawing 1 of difference in functionality by photoetching and injection, the well region of difference in functionality comprises high pressure P/N well region and low pressure P/N well region, carries out integral body and push away trap technique after defining the difference in functionality well region.
The step that is formed with the source region can be included in deposition SiN layer on Semiconductor substrate, and Semiconductor substrate can be for covering germanium (GOI) on silicon (Si), SiGe (SiGe), silicon-on-insulator (SOI), silicon-on-insulator germanium (SGOI), insulating barrier.The mode of then adopt taking a picture with the design transfer of light shield to wafer, adopt shallow trench isolation to etch pattern from the mode of (STI) etching, deposit afterwards high-density plasma (HDP) oxide skin(coating), adopt again the mode of reverse etching to etch active area structure, adopt at last the mode of STI chemico-mechanical polishing (CMP) to make the wafer surface planarization.
The mode of employing Implantation can form the well region of difference in functionality, and the well region of difference in functionality comprises high pressure P/N well region and low pressure P/N well region, carries out integral body and push away trap technique after defining the difference in functionality well region.Be more than the technique that forms the flush memory device well region, complete pushing away trap afterwards in order to improve the distribution of foreign atom in wafer, carry out annealing process, as the step 103 in accompanying drawing 1 and 104.When implementing annealing process, in order to improve the effect of annealing, reduce the value of ICCSB, and then reduce failure rate, the present invention has adopted following specific embodiment:
Specific embodiment one:
The technique of annealing is at first wafer to be placed in 950 ℃ of temperature, under annealing atmosphere, cooling rate with 2.5 ℃/Min cools the temperature to 750 ℃, whole process need 90Min, first with the cooling rate of 2.5 ℃/Min, temperature at the uniform velocity is down near 750 ℃ by 950 ℃, as 760 ℃ of left and right, slow down afterwards cooling rate, guarantee that temperature stabilization reaches 750 ℃.Find with a large amount of experimental studies, the mode of progressively lowering the temperature with slower cooling rate is annealed and can be reduced stress in wafer, reduce the ICCSB of device, the best results that wherein obtains with the cooling rate cooling of 2.5 ℃/Min, the ICCSB value that test obtains device is minimum.The test result of experiment finds, the ICCSB value that adopts the cooling rate of 2.5 ℃/Min to anneal to obtain can satisfy the needs of device performance, and can take into account and not improve the operation duration, and then not raise the cost mostly lower than 5 μ A.Find that simultaneously it is a better value that annealing temperature is down to 750 ℃ by 950 ℃.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N
2, N wherein
2Flow is: an import N
2Flow N
2(1) be 2L/Min, another import N
2Flow N
2(2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.
Choose the sample of three groups of flush memory devices and tested, all a plurality of flush memory devices have been carried out the test of ICCSB failure rate in every group of sample.For sample sets 1, contain a certain amount of oxygen (flow as oxygen inlet is 0.84L/Min) in annealing atmosphere; For sample sets 2, complete oxygen-free gas in annealing atmosphere; For sample sets 3, the amount of oxygen that contains in annealing atmosphere is larger.The test result of experiment is found, the sample sets 1 that contains a certain amount of oxygen in annealing atmosphere, the failure rate of ICCSB is in 4% left and right, the sample sets 3 that oxygenous amount is larger, the actual effect rate of ICCSB is in 6% left and right, and the sample sets 2 of oxygen-free gas in annealing atmosphere, the failure rate of ICCSB has decline by a relatively large margin under 2%.The result of experiment as shown in Figure 2.
Specific embodiment two:
The technique of annealing be with wafer in 950 ℃ of temperature, under annealing atmosphere, cool the temperature to 750 ℃ with the cooling rate of 5 ℃/Min, whole process need 40Min, mode with progressively cooling is annealed, and can reduce the stress in wafer, reduces the ICCSB of device.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N
2, N wherein
2Flow is: an import N
2Flow N
2(1) be 2L/Min, another import N
2Flow N
2(2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.
The experiment discovery, in annealing atmosphere, oxygen-free gas is compared with oxygenous, and the failure rate of ICCSB significantly decreases.
Specific embodiment three:
The technique of annealing is at first wafer to be placed in 950 ℃ of temperature, under annealing atmosphere, cools the temperature to 750 ℃, whole process need 200Min with the cooling rate of 1 ℃/Min.The mode of progressively lowering the temperature with slower cooling rate is annealed and can be reduced stress in wafer, reduces the ICCSB of device.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N
2, N wherein
2Flow is: an import N
2Flow N
2(1) be 2L/Min, another import N
2Flow N
2(2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.The experiment discovery, in annealing atmosphere, oxygen-free gas is compared with oxygenous, and the failure rate of ICCSB significantly decreases.
Specific embodiment four:
Annealing technique be with wafer in 1000 ℃ of temperature, under annealing atmosphere, cooling rate with 2.5 ℃/Min cools the temperature to 800 ℃, whole process need 90Min, first with the cooling rate of 2.5 ℃/Min, temperature at the uniform velocity is down near 800 ℃ by 1000 ℃, as 790 ℃ of left and right, slow down afterwards cooling rate, guarantee that temperature stabilization reaches 800 ℃.Find with a large amount of experimental studies, the mode of progressively lowering the temperature with slower cooling rate is annealed and can be reduced stress in wafer, reduce the ICCSB of device, the best results that wherein obtains with the cooling rate cooling of 2.5 ℃/Min, the ICCSB value that test obtains device is minimum, and can take into account and improve performance of devices and do not improve the operation duration, and then not raise the cost.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N
2, N wherein
2Flow is: an import N
2Flow N
2(1) be 2L/Min, another import N
2Flow N
2(2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.The experiment discovery, in annealing atmosphere, oxygen-free gas is compared with oxygenous, and the failure rate of ICCSB significantly decreases.
Specific embodiment five:
Annealing technique be with wafer in 900 ℃, under annealing atmosphere, cooling rate with 2.5 ℃/Min cools the temperature to 700 ℃, whole process need 90Min, first with the cooling rate of 2.5 ℃/Min, temperature at the uniform velocity is down near 700 ℃ by 900 ℃, as 710 ℃ of left and right, slow down afterwards cooling rate, guarantee that temperature stabilization reaches 700 ℃.Find with a large amount of experimental studies, the mode of progressively lowering the temperature with slower cooling rate is annealed and can be reduced stress in wafer, reduce the ICCSB of device, the best results that wherein obtains with the cooling rate cooling of 2.5 ℃/Min, the ICCSB value that test obtains device is minimum, and can take into account and improve performance of devices and do not improve the operation duration, and then not raise the cost.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N
2, N wherein
2Flow is: an import N
2Flow N
2(1) be 2L/Min, another import N
2Flow N
2(2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.The experiment discovery, in annealing atmosphere, oxygen-free gas is compared with oxygenous, and the failure rate of ICCSB significantly decreases.
Specific embodiment six:
The technique of annealing is at first wafer to be placed in 1000 ℃ of temperature, under annealing atmosphere, cools the temperature to 800 ℃, whole process need 200Min with the cooling rate of 1 ℃/Min.The mode of progressively lowering the temperature with slower cooling rate is annealed and can be reduced stress in wafer, reduces the ICCSB of device.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N
2, N wherein
2Flow is: an import N
2Flow N
2(1) be 2L/Min, another import N
2Flow N
2(2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.The experiment discovery, in annealing atmosphere, oxygen-free gas is compared with oxygenous, and the failure rate of ICCSB significantly decreases.
Specific embodiment seven:
The technique of annealing be with wafer in 1000 ℃ of temperature, under annealing atmosphere, cool the temperature to 800 ℃ with the cooling rate of 5 ℃/Min, whole process need 40Min, mode with progressively cooling is annealed, and can reduce the stress in wafer, reduces the ICCSB of device.
Annealing is to carry out in continuous oven, and the annealing atmosphere of employing is N2, and N2 flow wherein is: the flow N2(1 of an import N2) be 2L/Min, the flow N2(2 of another import N2) be 15-18L/Min.N
2Atmosphere is high pure nitrogen, and concrete purity is 99.9999%.
Adopt high pure nitrogen as annealing atmosphere, make oxygen-free gas in annealing atmosphere, reduce the activity of wafer surface, and then reduce the stress in wafer, reduce ICCSB, reduce the failure rate of ICCSB.The experiment discovery, in annealing atmosphere, oxygen-free gas is compared with oxygenous, and the failure rate of ICCSB significantly decreases.
Specific embodiment eight:
A kind of flush memory device, be included in the active area that forms on Semiconductor substrate, and by photoetching and the well region that injects the difference in functionality that defines, the well region of difference in functionality comprises high pressure P/N well region and low pressure P/N well region, carry out integral body and push away trap technique after defining the difference in functionality well region, complete pushing away trap afterwards in order to improve the distribution of foreign atom in wafer, carry out annealing process.Annealing process adopts the arbitrary technique in specific embodiment 1-7 to carry out.
Preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that to the invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not break away from protection scope of the present invention.Therefore, although by above embodiment, the present invention is described in further detail, the present invention is not limited only to above embodiment, in the situation that do not break away from the present invention's design, can also comprise more other equivalent embodiment, and scope of the present invention is determined by appended claim scope.
Claims (11)
1. the annealing process of a NOR flush memory device comprises:
Form well region on Semiconductor substrate,
Described well region is annealed, it is characterized in that, described annealing is alternating temperature annealing, namely under annealing atmosphere, second temperature of the first greenhouse cooling with temperature from 900-1000 ℃ in 700-800 ℃ completed the annealing to described well region, and do not contained O in described annealing atmosphere
2
2. annealing process according to claim 1, is characterized in that, described cooling is to be down to 750 ℃ from 950 ℃.
3. annealing process according to claim 1, is characterized in that, described cooling is to be down to 800 ℃ from 1000 ℃.
4. annealing process according to claim 1, is characterized in that, described cooling is to be down to 700 ℃ from 900 ℃.
5. the described annealing process of any one according to claim 1-4, is characterized in that, wherein cooling rate is: 1-5 ℃/Min.
6. annealing process according to claim 5, is characterized in that, described cooling rate is: 2.5 ℃/Min.
7. the described annealing process of any one according to claim 1-4, is characterized in that, the time that well region is annealed is 40-200Min.
8. annealing process according to claim 7, is characterized in that, the time that well region is annealed is 90Min.
9. the described annealing process of any one according to claim 1-4, is characterized in that, described annealing atmosphere is N
2
10. annealing process according to claim 9, is characterized in that, described N
2The flow of atmosphere is 15-18L/Min.
11. a NOR flush memory device is characterized in that, makes and adopts in claim 1-10 the described annealing process of any one to anneal in its process.
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2013
- 2013-01-11 CN CN2013100109936A patent/CN103094216A/en active Pending
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Application publication date: 20130508 |