CN103094117A - Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS) - Google Patents

Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS) Download PDF

Info

Publication number
CN103094117A
CN103094117A CN2011103404982A CN201110340498A CN103094117A CN 103094117 A CN103094117 A CN 103094117A CN 2011103404982 A CN2011103404982 A CN 2011103404982A CN 201110340498 A CN201110340498 A CN 201110340498A CN 103094117 A CN103094117 A CN 103094117A
Authority
CN
China
Prior art keywords
oxide layer
groove
epitaxial loayer
silicon dioxide
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103404982A
Other languages
Chinese (zh)
Other versions
CN103094117B (en
Inventor
金勤海
沈浩峰
袁秉荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN201110340498.2A priority Critical patent/CN103094117B/en
Publication of CN103094117A publication Critical patent/CN103094117A/en
Application granted granted Critical
Publication of CN103094117B publication Critical patent/CN103094117B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

The invention discloses a technique method of manufacturing a bottom thick grate oxide layer groove metal oxide semiconductor (MOS). The technique method of manufacturing the bottom thick grate oxide layer groove MOS comprises the following steps. The first step is that an epitaxial layer grows on a heavily-doped silicon substrate, and a first lightly-doped epitaxial layer is formed; the second step is that silicon dioxide grows on the first lightly-doped epitaxial layer; the third step is that a photoresist pattern is formed; the fourth step that the silicon dioxide which is unblocked by photoresist is etched cleanly, so that the first lightly-doped epitaxial layer except the photoresist is exposed, and then the photoresist is eliminated; the fifth step is that a second epitaxial layer grows selectively; the sixth step is the silicon dioxide is etched backward to required thickness through wet process or dry process etching technology, and a groove and a thick grate oxide layer at the bottom of the groove are formed. According to the technique method of manufacturing the bottom thick grate oxide layer groove MOS, selectively epitaxial growth is adopted to form the groove, the oxide layer inside the groove is etched backward to the required thickness so as to serve as the thick grate oxide layer at the bottom of the groove. According to the technique method of manufacturing the bottom thick grate oxide layer groove MOS, the structure of the bottom thick grate oxide layer groove MOS is enabled to be easily formed and controlled.

Description

Make the process of bottom thick grating oxide layer groove MOS
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, be specifically related to a kind of process of making bottom thick grating oxide layer groove MOS.
Background technology
Bottom thick grating oxide layer (thickness is 500~10000 dusts) MOS (metal-oxide semiconductor (MOS)) can make that between the device grid leak, electric capacity reduces greatly.Existing technique forms groove by etching, but this method makes the formation of bottom thick grating oxide layer very difficult.And existing technique generally only has one deck extension in heavy doping, and when needs have two-layer outer time-delay, prior art processes is controlled accurate not to the relative position of extension and groove, therefore makes the Comparision difficulty of optimizing epi dopant and device performance.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of process of making bottom thick grating oxide layer groove MOS, and it can easily be realized and control so that the formation of the bottom thick grating oxide layer of groove MOS becomes.
For solving the problems of the technologies described above, the technical solution that the present invention makes the process of bottom thick grating oxide layer groove MOS is to comprise the following steps:
The first step at heavily doped silicon Grown epitaxial loayer, forms the first light dope epitaxial loayer;
Second step, the silicon dioxide of growing on the first light dope epitaxial loayer;
The thickness of formed silicon dioxide is equal to, or greater than the follow-up gash depth that will form.
The 3rd step, adopt photoetching process, gluing, photoetching on silicon dioxide form photoetching offset plate figure;
The 4th step, etching, the silicon dioxide etching of not blocked by photoresist is clean, expose the first light dope epitaxial loayer beyond photoresist; Then remove photoresist;
The 5th step, selective growth the second epitaxial loayer; Superficial growth the second light dope epitaxial loayer at the first light dope epitaxial loayer that exposes;
The gash depth of the thickness of formed the second light dope epitaxial loayer for forming.
The 6th step, adopt wet method or dry etching technology, return and carve silicon dioxide to needed thickness, form the thick grating oxide layer of groove and bottom thereof.
The technique effect that the present invention can reach is:
The present invention adopts selective epitaxial growth to form groove, and returns the thickness that the oxide layer in the ditch groove extremely needs, to serve as the thick grating oxide layer of channel bottom.
The present invention can make bottom thick grating oxide layer trench MOS structure easily form and control, and can accurately control the position of the relative groove of epitaxial loayer of double-deck extension groove MOS, thereby can by controlling respectively the doping content of two-layer extension, come puncture voltage and the on state resistance of optimised devices.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 to Fig. 5 makes the corresponding structural representation of each step of the process of bottom thick grating oxide layer groove MOS with the present invention;
Fig. 6 is the schematic cross-section that adopts the made bottom thick grating oxide layer groove MOS device of the present invention.
Embodiment
The present invention makes the process of bottom thick grating oxide layer groove MOS, comprises the following steps:
The first step as shown in Figure 1, at heavily doped silicon Grown epitaxial loayer, forms the first light dope epitaxial loayer; The heavy doping bulk concentration is 10 18/ cm 3Above;
Second step, as shown in Figure 1, the silicon dioxide of growing on the first light dope epitaxial loayer, its thickness is equal to, or greater than the follow-up gash depth that will form;
The 3rd step, as shown in Figure 2, adopt photoetching process, gluing, photoetching on silicon dioxide form photoetching offset plate figure;
The 4th step, as shown in Figure 3, etching, the silicon dioxide etching of not blocked by photoresist is clean, expose the first light dope epitaxial loayer beyond photoresist; Then remove photoresist;
The 5th step, as shown in Figure 4, selective growth the second epitaxial loayer; At the superficial growth second light dope epitaxial loayer of the first light dope epitaxial loayer that exposes, and do not grow on silicon dioxide;
The thickness of the second light dope epitaxial loayer is to want the gash depth that forms;
The 6th step, as shown in Figure 5, adopt existing wet method or dry etching technology, return and carve silicon dioxide to needed thickness, namely form the thick grating oxide layer of groove and bottom thereof;
The silicon dioxide that remains is namely as the thick grating oxide layer of channel bottom;
Adopt the present invention, can make groove MOS device as shown in Figure 6.

Claims (3)

1. a process of making bottom thick grating oxide layer groove MOS, is characterized in that, comprises the following steps:
The first step at heavily doped silicon Grown epitaxial loayer, forms the first light dope epitaxial loayer;
Second step, the silicon dioxide of growing on the first light dope epitaxial loayer;
The 3rd step, adopt photoetching process, gluing, photoetching on silicon dioxide form photoetching offset plate figure;
The 4th step, etching, the silicon dioxide etching of not blocked by photoresist is clean, expose the first light dope epitaxial loayer beyond photoresist; Then remove photoresist;
The 5th step, selective growth the second epitaxial loayer; Superficial growth the second light dope epitaxial loayer at the first light dope epitaxial loayer that exposes;
The 6th step, adopt wet method or dry etching technology, return and carve silicon dioxide to needed thickness, form the thick grating oxide layer of groove and bottom thereof.
2. process of making bottom thick grating oxide layer groove MOS according to claim 1, is characterized in that, the thickness of the formed silicon dioxide of described second step is equal to, or greater than the follow-up gash depth that will form.
3. process of making bottom thick grating oxide layer groove MOS according to claim 1 and 2, is characterized in that, the gash depth of thickness for forming of described the 5th formed the second light dope epitaxial loayer of step.
CN201110340498.2A 2011-11-01 2011-11-01 Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS) Active CN103094117B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110340498.2A CN103094117B (en) 2011-11-01 2011-11-01 Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110340498.2A CN103094117B (en) 2011-11-01 2011-11-01 Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS)

Publications (2)

Publication Number Publication Date
CN103094117A true CN103094117A (en) 2013-05-08
CN103094117B CN103094117B (en) 2015-06-03

Family

ID=48206544

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110340498.2A Active CN103094117B (en) 2011-11-01 2011-11-01 Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS)

Country Status (1)

Country Link
CN (1) CN103094117B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1314714A (en) * 2000-03-22 2001-09-26 精工电子有限公司 Vertical metal-oxide-semiconductor transistor
US20060023781A1 (en) * 2004-07-27 2006-02-02 Leung Ka Y Digital PWM controller with efficiency optimization
US20100176448A1 (en) * 2008-06-23 2010-07-15 Force Mos Technology Co. Ltd. Intergrated trench mosfet with trench schottky rectifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1314714A (en) * 2000-03-22 2001-09-26 精工电子有限公司 Vertical metal-oxide-semiconductor transistor
US20060023781A1 (en) * 2004-07-27 2006-02-02 Leung Ka Y Digital PWM controller with efficiency optimization
US20100176448A1 (en) * 2008-06-23 2010-07-15 Force Mos Technology Co. Ltd. Intergrated trench mosfet with trench schottky rectifier

Also Published As

Publication number Publication date
CN103094117B (en) 2015-06-03

Similar Documents

Publication Publication Date Title
CN102983171B (en) The vertical structure without knot surrounding-gate MOSFET device and manufacture method thereof
CN108649072A (en) A kind of groove MOSFET device and its manufacturing method of low on-resistance
CN103579003B (en) A kind of method making super node MOSFET
CN103000534B (en) Groove-type P-type metal oxide semiconductor power transistor manufacture method
CN101431020B (en) Production method of T type polysilicon gate electrode
CN103779415B (en) Planar power MOS device and manufacture method thereof
CN103094118B (en) Technique method of manufacturing double-layer gate groove metal oxide semiconductor (MOS)
CN103094074B (en) Technique method of manufacturing bottom thick gate oxide layer groove Metal Oxide Semiconductor (MOS) through selective epitaxy
CN103094115B (en) Technique method of manufacturing double-layer gate groove metal oxide semiconductor (MOS)
CN103094117B (en) Technique method of manufacturing bottom thick grate oxide layer groove metal oxide semiconductor (MOS)
CN104392917B (en) A kind of forming method of all-around-gate structure
CN104347375A (en) Method for etching grid polysilicom by using oxide film as barrier layer
CN105679809A (en) Manufacturing method of groove-type super junctions
CN206134689U (en) Low pressure trench gate DMOS device of high integration
CN105355559A (en) Method for preparing semiconductor device
CN102479816B (en) Metal-oxide semiconductor type field-effect transistor and manufacturing method thereof
CN103094116A (en) Technique method of manufacturing groove metal oxide semiconductor (MOS)
CN102437193B (en) Bidirectional high-voltage MOS (metal oxide semiconductor) transistor in BCD (bipolar-CMOS-DMOS) technology and manufacturing method thereof
CN107887447A (en) A kind of MOS type device and its manufacture method
CN105448981A (en) VDMOS device, drain electrode structure thereof, and manufacturing method
CN104779164A (en) Method for increasing breakdown voltage of gate oxide layer of trench-type VDMOS
CN209515675U (en) A kind of separation grid MOSFET component
CN104241356B (en) DMOS device and manufacturing method thereof
CN207852683U (en) A kind of groove MOSFET device of low on-resistance
CN103390653B (en) Groove structure schottky device and manufacture method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140107

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TA01 Transfer of patent application right

Effective date of registration: 20140107

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Applicant before: Shanghai Huahong NEC Electronics Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant