CN103091561A - Device obtaining direct current signals from alternative current and direct current superposition signals and method thereof - Google Patents

Abstract

The invention discloses a device obtaining direct current signals from alternative current and direct current overlapped signals. The device obtaining the direct current signals from the alternative current and direct current overlapped signals comprises a controller which sends out control commands according to time sequence, a whole cycle sampling switch connected with the controller and being switched on and off according to the control commands outputted by the controller, an integral circuit connected with an output end of the whole cycle sampling switch, a sampling maintain switch, a sampling holder connected with the other end of the sampling maintain switch, wherein an integral capacitance on the integral circuit conducts integral sampling of inputted overlapped signals, and one end of the sampling maintain switch is connected with the output end of the integral circuit. After sampling of the integral circuit is finished, under the control of the controller, the whole cycle sampling switch is disconnected, the sampling maintain switch is closed, voltage of the integral capacitance is transferred to the sampling holder to be kept. The device obtaining the direct current signals from the alternative current and the direct current overlapped signals can eliminate power line interference of the overlapped signals, ensure test of the instrument not to be influenced by alternative current signals, and improve test speed.

Description

Extract the device and method of direct current signal from the alternating current-direct current superposed signal

Technical field

The present invention relates to a kind of device and method that extracts direct current signal from the alternating current-direct current superposed signal.

Background technology

Megger test is to allow a DC voltage be connected to detected element two ends, and electric current and voltage by element two ends come the computing element insulation resistance.During test, measured piece substantially is in the high resistant shape and approaches open circuit.Test sample input impedance is very high, and is very responsive to the electromagnetic interference (EMI) of environment.The DC voltage relevant due to tested electric current is 0.1-10mVDC, finds by the measurement of side circuit, and the interference of circuit is mainly two parts, and major part is that power frequency is disturbed (20mVp), and a part is white noise (5mVp) in addition.And the amplitude of white noise is far smaller than the power frequency interference.The white noise undesired signal can be removed by simple filtering circuit, on not impact of test speed.Interference when therefore testing is mainly that power frequency is disturbed, and it is 50Hz, 60Hz that power frequency is disturbed common frequency.When adopting at present the Insulation Resistance Tester test, be to adopt multi-stage filter circuit to realize the filtering power frequency interference signals.There is following problem in multi-stage filter circuit:

Multiple-stage filtering certainly exists the problem of low pass flex point and attenuation degree.Due to the accuracy requirement of signal, need to adopt the smooth filtering circuit of characteristic.And these class circuit 10 frequency doubling attenuation coefficients comparisons are little, need to adopt multi-stage superimposed.Calculate the flex point of low pass-3DB of 10 frequencys multiplication by power frequency just at 5Hz, 6Hz, multi-stage superimposed just poorer.Consider that response speed just can not adopt the decay of too many level.Decay is not enough cause the interference attenuation of data after amplitude larger, still can flood test data when little current sample, the lower limit of measuring current can't improve.The general test electric current is all in the 10E-10 magnitude, and response speed is greater than 500 milliseconds (with reference to Fig. 2).Therefore, the removal undesired signal of employing multi-stage filter circuit, time delay is very large, makes test speed slowly and data stability formation antagonistic relations, can't realize response fast and high stable measurement.Under can passing through, this structure proves with explanation:

With reference to Fig. 1, in figure when not gathering electric current, the interference waveform that test lead is unsettled, actual test is disturbed may be larger.Appliance requires with this signal compression to the size that does not affect test signal.It is that 1nA electric current, sampling resistor are that 10M, instrument internal are enlarged into 100 times that the circuit of figure is used for gathering maximum current.That is to say the great talent 10mVDC of sampled value, is 1V after amplifying.The circuit sampling precision is 1%, needs the electric current of steady testing 10pA, and namely the sampled signal amplitude is 0.1mV.And AC noise has 20mVp, large 200 times than the stable sampled value of actual needs.If this signal is amplified analog-to-digital conversion circuit together will can't work over the test signal upper limit.Will be with the 20mVp interference attenuation below 0.1mV, exchanging to disturb probably needs decay 60DB just can meet design requirement.Interference wave is the power frequency environmental radiation, and frequency ratio is lower.Filtering must bring the slack-off problem of response speed.Instrument in the past adopts the two-stage Butterworth filter, makes the response speed of sample circuit need the hundreds of millisecond, can't satisfy quick test request.

In addition, due to test signal extremely a little less than, the foregoing circuit magnification ratio is very high, when amplifying test signal, undesired signal is amplified simultaneously, so that block the work of AD sample circuit.

Summary of the invention

For above-mentioned technical matters, the object of the present invention is to provide a kind of device and method that extracts direct current signal from the alternating current-direct current superposed signal, the power frequency that the present invention not only can remove in superposed signal is disturbed, and guarantees that the test of instrument is not affected by AC signal, makes test speed also obtain raising.

Realize that technical scheme of the present invention is as follows:

A kind of device that extracts direct current signal from the alternating current-direct current superposed signal comprises the controller that sends steering order according to sequential; And

The integer-period sampled switch that is connected with controller carries out closure or disconnection according to the steering order of controller output, and the closure time of this integer-period sampled switch equals the cycle of undesired signal; And

The integrating circuit that is connected with integer-period sampled output switching terminal, at integer-period sampled switch period of contact, the integrating capacitor on this integrating circuit is carried out the integration sampling to the superposed signal of input; And

The sampling maintained switch that one end is connected with the integrating circuit output terminal, the sampling maintained switch carries out closure or disconnection according to the steering order of controller output; And

The sampling holder that is connected with the sampling maintained switch other end, after the integrating circuit sampling is complete, under the control of controller, integer-period sampled switch is disconnected, the sampling maintained switch is closed, and the voltage transfer on described integrating capacitor is preserved to sampling holder.

Further, also comprise a discharge switch that is connected with controller, the two ends of this discharge switch are in parallel with the integrating capacitor of integrating circuit, under the control of controller, the sampling maintained switch is disconnected, discharge switch is closed, before integration period next time, guarantees that the electric charge on described integrating capacitor is zero.

Further, described controller is CPU or sequential logical circuit.

Further, described sampling holder comprises sampling capacitance and operational amplifier, one end of sampling capacitance is connected with the in-phase input end of operational amplifier, the other end ground connection of sampling capacitance, and the inverting input of operational amplifier is connected with the output terminal of this operational amplifier.

Further, described operational amplifier is the operational amplifier of high input impedance, low output impedance.

A kind of method of extracting direct current signal from the alternating current-direct current superposed signal comprises the following steps:

Step 1, at first controller sends steering order according to sequential makes integer-period sampled switch closed, the closure time of integer-period sampled switch equals the cycle of undesired signal, and at integer-period sampled switch period of contact, the integrating capacitor on integrating circuit is taken a sample to the superposed signal of input;

Step 2, after integrating capacitor sampling was complete, controller was controlled integer-period sampled switch and is disconnected, and controlled simultaneously the sampling maintained switch closed, output again after the voltage transfer on integrating capacitor is preserved to the sampling holder.

Further, also comprise step 3, under the control sequential of controller, after voltage transfer on integrating capacitor is completed to sampling holder, controller disconnects the sampling maintained switch, is parallel to the discharge switch closure at integrating capacitor two ends, makes on integrating capacitor and discharges, before integration period next time, guarantee that the electric charge on described integrating capacitor is zero.

Further, after step 2 is completed, calculate by following formula from the output voltage of sampling holder:

$\frac{\mathrm{Vo}}{V1}=\frac{1}{\mathrm{RC}}*{\∫}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In following formula, 1/RC is the sampling scale-up factor, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the relevant DC voltage of tested electric current, A*sin(ω t+r) be the integration power frequency component, T/RC is the sampling scale-up factor, and A*sin (r) * Kt is the ripple size of output.

Adopted such scheme, at first make integer-period sampled maintained switch closed by controller, by integrating circuit, the superposed signal of input is carried out the integration sampling, equal the cycle of undesired signal due to the closure time of integer-period sampled switch, therefore, in sampled signal, the AC signal in superposed signal is zero just, and the voltage on integrating capacitor is the direct-flow signal voltage of sampling.When the time of integration sampling was a complete cycle of power frequency interference signals, controller disconnected integer-period sampled maintained switch, made simultaneously the sampling maintained switch closed, output again after the voltage transfer on integrating capacitor is preserved to the sampling holder.By the device that extracts direct current signal from the alternating current-direct current superposed signal of the present invention, the time delay of sampled signal is not more than 100mS.And the time delay of circuit greater than 500mS, had been accelerated the test rate of instrument when testing apparatus is used greatly in the past, satisfied the requirement of high speed megger test.Measuring stability also improves a lot and satisfies the performance requirement of new instrument.

Description of drawings

Fig. 1 is sampling, the amplification High frequency filter signal comparison diagram when in prior art, Insulation Resistance Tester is tested;

Fig. 2 is Insulation Resistance Tester test disturbance response figure in prior art: (introducing sign mutation with hand touching test lead);

Fig. 3 is the circuit theory diagrams that extract the device of direct current signal from the alternating current-direct current superposed signal of the present invention;

Fig. 4 is the sequential chart of each switch of control of controller;

Fig. 5 for adopt the device that extracts direct current signal from the alternating current-direct current superposed signal of the present invention signal is sampled and integration after, signal keeps comparing figure with output signal;

Fig. 6 for the device collection of extracting direct current signal from the alternating current-direct current superposed signal of this employing invention and integration after signal disturbance response figure (introducing sign mutation with hand touching test lead);

Embodiment

With reference to Fig. 3 to Fig. 4, a kind of device that extracts direct current signal from the alternating current-direct current superposed signal of the present invention comprises the controller that sends steering order according to sequential, and this controller is CPU or sequential logical circuit.And

The integer-period sampled K switch 1 that is connected with controller is carried out closure or disconnection according to the steering order of controller output, and the closure time of this integer-period sampled switch equals the cycle of undesired signal.And

The integrating circuit that is connected with integer-period sampled output switching terminal, at integer-period sampled switch period of contact, the integrating capacitor on integrating circuit is carried out the integration sampling to the superposed signal of input.Equal the cycle of undesired signal due to the closure time of integer-period sampled switch, therefore, in sampled signal, the AC signal in superposed signal is zero just, and the voltage on integrating capacitor is the direct-flow signal voltage of sampling.Integrating circuit is comprised of operational amplifier UA, integrating capacitor C1 and resistance R, one end of resistance R is connected with integer-period sampled K switch 1, the other end of resistance R is connected in the inverting input of operational amplifier UA, the in-phase input end ground connection of operational amplifier UA, the two ends of capacitor C 1 are connected with output terminal with the inverting input of operational amplifier UA respectively.And

The sampling maintained switch K3 that one end is connected with the integrating circuit output terminal, sampling maintained switch K3 carries out closure or disconnection according to the steering order of controller output; And

The sampling holder that is connected with the sampling maintained switch K3 other end, after the integrating circuit sampling is complete, under the control of controller, integer-period sampled K switch 1 is disconnected, K3 is closed for the sampling maintained switch, and the voltage transfer on described integrating capacitor is preserved to sampling holder.Sampling holder comprises sampling capacitance C2 and operational amplifier UB, the end of sampling capacitance C2 is connected with the in-phase input end of operational amplifier UB, the other end ground connection of sampling capacitance C2, the inverting input of operational amplifier UB is connected with the output terminal of this operational amplifier.Operational amplifier UB is the operational amplifier of high input impedance, low output impedance, and operational amplifier can effectively amplify the carrying out of sending in this operational amplifier effectively.And

The discharge switch K2 that is connected with controller, the two ends of this discharge switch K2 are in parallel with the integrating capacitor C1 of integrating circuit, under the control of controller, sampling maintained switch K3 is disconnected, discharge switch is closed, before integration period next time, guarantees that the electric charge on described integrating capacitor is zero.

With reference to Fig. 3 to Fig. 4, extract the method for direct current signal from the alternating current-direct current superposed signal, comprise the following steps:

Step 1, at first controller sends steering order according to sequential makes integer-period sampled switch closed, the closure time of integer-period sampled switch equals the cycle of undesired signal, and at integer-period sampled switch period of contact, the integrating capacitor on integrating circuit is taken a sample to the superposed signal of input;

Step 2, after integrating capacitor sampling was complete, controller was controlled integer-period sampled switch and is disconnected, and controlled simultaneously the sampling maintained switch closed, output again after the voltage transfer on integrating capacitor is preserved to the sampling holder.

After step 2 is completed, calculate by following formula from the output voltage of sampling holder:

$\frac{\mathrm{Vo}}{V1}=\frac{1}{\mathrm{RC}}*{\∫}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}---\left(1\right)$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})---\left(2\right)$

In following formula, 1/RC is the sampling scale-up factor, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the relevant DC voltage of tested electric current, A*sin(ω t+r) be the integration power frequency component, T/RC is the sampling scale-up factor, and A*sin (r) * Kt is the ripple size of output.

Following formula (2) is a calculating formula that the simplification step obtains, and principle of the present invention is integration, is calculated as follows with concrete mathematical derivation:

Power frequency interference period: T

Power frequency disturbance angle velocity: ω=T/ (2* π)

Power frequency noise amplitudes: A

Power frequency interference signals is: A*sin(ω t)

Integration start-up phase parallactic angle: r

The integration power frequency component is: A*sin(ω t+r)

The deviation of integration period and interference period: Kt

The actual integration cycle is: T (1+Kt)

Formula is as follows:

$\frac{\mathrm{Vo}}{V1}=\frac{1}{\mathrm{RC}}*{\∫}_0^{T(1+\mathrm{Kt})}(\mathrm{Vx}+A*\sin (\mathrm{\ωt}+r))\mathrm{dt}$

$=\frac{1}{\mathrm{RC}}*T(1+\mathrm{Kt})*\mathrm{Vx}+\frac{1}{\mathrm{RC}}*\frac{A}{\mathrm{\ω}}*(\cos \left(r\right)-\cos (2*\mathrm{\π}*\mathrm{Kt}+r)$

Because circuit is actual when realizing: Kt myopia is zero

Cso (r)-cos (2* π * Kt+r) can think that waveform is at cos(r) little increment of locating, following formula can be written as

$=\frac{T}{\mathrm{RC}}*(1+\mathrm{Kt})*\mathrm{Vx}-\frac{1}{\mathrm{RC}}*\frac{A}{\mathrm{\ω}}*\sin \left(r\right)*(2*\mathrm{\π}*\mathrm{Kt})$

$=\frac{T}{\mathrm{RC}}*((1+\mathrm{Kt})*\mathrm{Vx}-A*\sin \left(r\right)*\mathrm{Kt})$

T/RC can think the scale-up factor of sampling, and is fixed constant after circuit is determined, can easily compensate by stoichiometric coefficient to come.

The ripple size of output is: A*sin (r) * Kt, Kt has directly determined the ripple amplitude.If need the decay (1000 times) of 60DB, Kt＜0.1% gets final product, and base was tens nanoseconds during instrumentation control system, if do not consider the stability of power frequency supply, the timeorder error of instrument generally can be less than 0.01%.

And (1+Kt) in * Vx: introduce deviation less than 0.1% during Kt＜0.1%, on the not impact of 1% measuring accuracy.

Therefore, through top concrete calculation procedure, finally obtain the calculating formula of following formula (2).

Step 3, under the control sequential of controller, after voltage transfer on integrating capacitor is completed to sampling holder, controller disconnects the sampling maintained switch, be parallel to the discharge switch closure at integrating capacitor two ends, make on integrating capacitor and discharge, before integration period next time, guarantee that the electric charge on described integrating capacitor is zero.

With reference to Fig. 5 and Fig. 6, by the device that extracts direct current signal from the alternating current-direct current superposed signal of the present invention, the time delay of sampled signal is not more than 100mS.And the time delay of circuit compared Fig. 5 and Fig. 1 greater than 500mS(in the past, and Fig. 6 and Fig. 2 are compared), greatly accelerated the test rate of instrument when testing apparatus is used, satisfy the requirement of high speed megger test.Measuring stability also improves a lot and satisfies the performance requirement of new instrument.

Claims (8)

1. a device that extracts direct current signal from the alternating current-direct current superposed signal, is characterized in that, comprises the controller that sends steering order according to sequential; And

The integer-period sampled switch that is connected with controller carries out closure or disconnection according to the steering order of controller output, and the closure time of this integer-period sampled switch equals the cycle of undesired signal; And

The integrating circuit that is connected with integer-period sampled output switching terminal, at integer-period sampled switch period of contact, the integrating capacitor on this integrating circuit is carried out the integration sampling to the superposed signal of input; And

The sampling maintained switch that one end is connected with the integrating circuit output terminal, the sampling maintained switch carries out closure or disconnection according to the steering order of controller output; And

The sampling holder that is connected with the sampling maintained switch other end, after the integrating circuit sampling is complete, under the control of controller, integer-period sampled switch is disconnected, the sampling maintained switch is closed, and the voltage transfer on described integrating capacitor is preserved to sampling holder.

2. a kind of device that extracts direct current signal from the alternating current-direct current superposed signal according to claim 1, it is characterized in that, also comprise a discharge switch that is connected with controller, the two ends of this discharge switch are in parallel with the integrating capacitor of integrating circuit, under the control of controller, the sampling maintained switch is disconnected, discharge switch is closed, before integration period next time, guarantee that the electric charge on described integrating capacitor is zero.

3. a kind of device that extracts direct current signal from the alternating current-direct current superposed signal according to claim 1 and 2, is characterized in that, described controller is CPU or sequential logical circuit.

4. a kind of device that extracts direct current signal from the alternating current-direct current superposed signal according to claim 1 and 2, it is characterized in that, described sampling holder comprises sampling capacitance and operational amplifier, one end of sampling capacitance is connected with the in-phase input end of operational amplifier, the other end ground connection of sampling capacitance, the inverting input of operational amplifier is connected with the output terminal of this operational amplifier.

5. a kind of device that extracts direct current signal from the alternating current-direct current superposed signal according to claim 4, is characterized in that, described operational amplifier is the operational amplifier of high input impedance, low output impedance.

6. a method of extracting direct current signal from the alternating current-direct current superposed signal, is characterized in that, comprises the following steps:

Step 1, at first controller sends steering order according to sequential makes integer-period sampled switch closed, the closure time of integer-period sampled switch equals the cycle of undesired signal, and at integer-period sampled switch period of contact, the integrating capacitor on integrating circuit is advanced the superposed signal of input ₁The row sampling;

Step 2, after integrating capacitor sampling was complete, controller was controlled integer-period sampled switch and is disconnected, and controlled simultaneously the sampling maintained switch closed, output again after the voltage transfer on integrating capacitor is preserved to the sampling holder.

7. the method for extracting direct current signal from the alternating current-direct current superposed signal according to claim 6, it is characterized in that, also comprise step 3, under the control sequential of controller, after the voltage transfer on integrating capacitor was completed to sampling holder, controller disconnected the sampling maintained switch, be parallel to the discharge switch closure at integrating capacitor two ends, make on integrating capacitor and discharge, before integration period next time, guarantee that the electric charge on described integrating capacitor is zero.

8. the according to claim 6 or 7 described methods of extracting direct current signal from the alternating current-direct current superposed signal, is characterized in that, after step 2 is completed, calculates by following formula from the output voltage of sampling holder:

In following formula, 1/RC is the sampling scale-up factor, Kt is the deviation of integration period and interference period, T (1+Kt) is the actual integration cycle, Vx is the relevant DC voltage of tested electric current, A*sin(ω t+r) be the integration power frequency component, T/RC is the sampling scale-up factor, and A*sin (r) * Kt is the ripple size of output.

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