CN103067675B - Cmos pixel array calibration system - Google Patents
Cmos pixel array calibration system Download PDFInfo
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Abstract
A kind of cmos pixel array calibration system, including：Pel array, it includes at least a line calibration pixel and multirow pixel to be corrected, and each calibration pixel generates first voltage signal according to a reference voltage signal, and each pixel to be corrected is based on opto-electronic conversion generation second voltage signal；At least one AD conversion unit, for first voltage signal, second voltage signal to be separately converted into the first data signal and the second data signal；Voltage generating unit, for providing reference voltage signal to calibration pixel according to a benchmark data signal；Row driving circuits, for generating one group of clock signal, clock signal gates a line calibration pixel or a line pixel to be corrected respectively；Digital calibration unit, the second data signal is corrected and exported for comparing the difference of the first data signal and benchmark data signal, and according to difference.It makes each region of cmos pixel array approach the susceptibility of light, the homogeneity of imaging is good.
Description
Technical field
The present invention relates to IC design field, more specifically to a kind of cmos pixel array calibration system.
Background technology
Cmos image sensor and ccd image sensor are all the semiconductor devices for converting optical signals into electric signal,
Cmos image sensor cost is lower, power consumption is also lower, and in the modern life, cmos image sensor has obtained largely should
With such as industrial camera, civil camera, mobile phone, the first-class equipment of monitoring camera.
However, each regional imaging heterogeneity of usual cmos pixel array, variant to the susceptibility of light in other words, this is not
Insignificant problem.On the one hand, under identical process conditions, because the batch residing for component, position are different, cmos pixel battle array
The imaging contexts for arranging each region can be variant；On the other hand, each pixel under the excitation of optical signal via different circuit paths
Output image signal, and also bring along different semaphores via different circuit paths and lose, even if each pixel all obtains
Same amount of optical signal, different circuit paths can also make have a notable difference between the electric signal of each pixel output.
Therefore, industry it is expected to obtain a kind of cmos pixel array calibration system, and it can overcome component poor to a certain extent
The difference that different and each pixel is brought via different circuit paths output digit signals, makes each region of cmos pixel array to light
Susceptibility is close, the homogeneity of imaging is good.
The content of the invention
It is an object of the present invention to provide a kind of cmos pixel array calibration system, and it makes each area of cmos pixel array
Domain approaches to the susceptibility of light, the homogeneity of imaging is good.
To achieve the above object, technical solution of the present invention is as follows：
A kind of cmos pixel array calibration system, including：Pel array, it includes at least a line calibration pixel and multirow and treated
Correction pixels, calibration pixel and pixel to be corrected are set in the matrix form；Calibration pixel is according to reference voltage signal generation the
One voltage signal；Pixel to be corrected is based on opto-electronic conversion generation second voltage signal；At least one AD conversion unit, for inciting somebody to action
First voltage signal, the second voltage signal of pixel to be corrected output of calibration pixel output are separately converted to the first data signal
With the second data signal；Voltage generating unit, for providing reference voltage signal to calibration pixel；Row driving circuits,
For generating one group of clock signal, clock signal gates a line calibration pixel or a line pixel to be corrected respectively；Digital calibration list
Member, school is carried out to the second data signal for comparing the difference of the first data signal and benchmark data signal, and according to difference
Just and export.
Preferably, AD conversion unit is a ramp voltage formula AD conversion unit, and it includes a ramp voltage input；
Voltage generating unit also generates a ramp voltage to input the ramp voltage input of AD conversion unit, and calibration pixel is defeated
First voltage signal, the second voltage signal of pixel to be corrected output gone out is separately converted to the first data signal and the second numeral
Signal.
Preferably, a line calibration picture is only gated in a clock signal timing cycles in office for row driving circuits generation
Element or a line pixel to be corrected.
Preferably, AD conversion unit is multiple, and is corresponded with calibration pixel, with concurrently by multiple first voltages
Signal is converted to the first data signal or multiple second voltage signals concurrently is converted into the second data signal.
Preferably, digital calibration unit includes multiple adders, multiple subtracters and multiple memory cell, adder,
Subtracter and memory cell correspond with AD conversion unit respectively, and each subtracter calculates corresponding analog-to-digital conversion
The difference of the first data signal and benchmark data signal of unit output, and difference deposit is corresponding with the AD conversion unit
In memory cell, adder corresponding with the AD conversion unit reads difference from the memory cell, asks for the analog-to-digital conversion list
The second data signal and the difference sum of member output simultaneously export.
Preferably, digital calibration unit includes multiple output ends, and output end simultaneously corresponds with AD conversion unit, with simultaneously
Row output it is multiple it is calibrated after the second data signal.
Cmos pixel array calibration system provided by the invention, believed based on the calibration pixel in pel array to reference voltage
Number loss brought, the picture signal exported to the pixel to be corrected in pel array are corrected, and make cmos pixel array
Each region approaches to the susceptibility of light, the homogeneity of imaging is good.
A kind of method being corrected another object of the present invention is to provide output to cmos pixel array, it is calibrated
Original appearance of the image exported afterwards closer to scene during imaging.
To achieve the above object, the another technical scheme of the present invention is as follows：
A kind of method that output to cmos pixel array is corrected, comprises the following steps：A) pel array, is selected
One-row pixels are calibration pixel；B), one benchmark data signal is provided and be converted to a reference voltage signal through DA, and to each calibration
Pixel applies reference voltage signal；C) the first voltage signal of each calibration pixel output, is measured, and by first voltage signal through AD
Be converted to the first data signal；D) difference of the first data signal and benchmark data signal, is calculated；E), obtained according in step d)
The difference arrived, the second data signal is corrected, the second data signal receives light by each pixel to be corrected in pel array
Signal and the second voltage signal that exports obtain through AD conversion.
Brief description of the drawings
Fig. 1 shows the cmos pixel array calibration system structure diagram of first embodiment of the invention；
Fig. 2 shows the cmos pixel array calibration system structure diagram of second embodiment of the invention；
Fig. 3 shows the flow signal for the method that the output to cmos pixel array of third embodiment of the invention is corrected
Figure.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.
It should be noted that according to any embodiment of the present invention, cmos pixel array calibration system comprises at least pixel
Array, AD conversion unit, the light of intake is converted to voltage signal by pel array, then is changed into digital letter through AD conversion unit
Number, form digital picture output.
As shown in figure 1, the cmos pixel array calibration system of first embodiment of the invention include pel array, row control and
Drive circuit 20, multiple AD conversion units 30, voltage generating unit 40 and digital calibration unit 50.
Wherein, respectively form the structure of part and function is described as follows：
Pel array includes a line calibration pixel 101 and multirow pixel 102 to be corrected, and often capable number of pixels is equal, from
And set in the matrix form.Each calibration pixel 101 has a voltage signal inputs, a clock signal input and an electricity
Signal output part is pressed, calibration pixel 101 can generate first voltage signal according to a reference voltage signal, and reference voltage is each picture
Element receives the voltage that should be exported in theory after a same amount of optical signal.Each pixel 102 to be corrected has clock signal input
End and a voltage signal output end, pixel 102 to be corrected are based on opto-electronic conversion generation second voltage signal.
The output end of row driving circuits 20 respectively with each calibration pixel 101 and each pixel 102 to be corrected
Clock signal input connects, and it generates one group of clock signal, and this group of clock signal gates a line calibration pixel 101 or one respectively
Row pixel 102 to be corrected, when gating calibration pixel 101, calibration pixel 101 is in running order；Gate a line pixel to be corrected
When 102, row pixel 102 to be corrected is in running order, can carry out opto-electronic conversion.
The number of AD conversion unit 30 is identical with the specific number of calibration pixel 101, i.e., also with a line pixel to be corrected
102 specific number is equal, and they are corresponded.Each AD conversion unit 30 have a voltage signal inputs, with
And a digital signal output end, its first voltage signal for exporting each calibration pixel 101, each pixel 102 to be corrected export
Second voltage signal is separately converted to the first data signal and the second data signal；With this embodiment, AD conversion can be parallel
Ground is carried out.According to the gating respectively of row driving circuits 20, first voltage signal and second voltage signal will not be applied simultaneously
The voltage signal inputs of AD conversion unit 30 are added on, to prevent from interfering.AD conversion unit 30 can use existing skill
Any analog-digital converter in art.
Voltage generating unit 40, it has a digital signal input end, a voltage signal output end, its voltage signal output end
It is connected with the voltage signal inputs of each calibration pixel 101, the external benchmark data signal of its digital signal input end, it will
The benchmark data signal of input is converted to reference voltage signal, and is supplied to each calibration pixel 101, then by respective circuit point
First voltage signal corresponding to each calibration pixel 101 is not exported.Benchmark data signal is that each pixel receives phase in pel array
The data signal that should be exported in theory after one optical signal of same amount, which represent a kind of ideal situation, reference voltage signal is by base
Quasi- data signal converts through DA.
Digital calibration unit 50, it has multiple inputs and multiple output ends, its input and AD conversion unit 30
Digital signal output end connect and correspond, its output end also corresponds with input.When it can be to multiple inputs
Signal is calibrated simultaneously when, its multiple output end also can concurrently export it is multiple it is calibrated after signal.Digital calibration unit
50 compare the difference of the first data signal and benchmark data signal, and the second data signal is corrected simultaneously further according to above-mentioned difference
Final output.
According to the embodiment, because benchmark data signal is that each pixel receives a same amount of optical signal in pel array
The data signal that should be exported in theory afterwards, thus, the difference of first voltage signal and reference voltage signal characterizes cmos pixel
The loss that array and other circuits, part come to the transfer tape of voltage signal, the difference of the first data signal and benchmark data signal
Value then characterizes the loss of this signal transmission with digital quantity.Therefore, in the present invention, digital calibration unit 50 is according to the first numeral
Signal and the difference of benchmark data signal, the second number exported to each pixel 102 to be corrected in pel array after AD conversion
Word signal is corrected, so that each region of cmos pixel array approaches to the susceptibility of light, the homogeneity of imaging is good.
Further, a line school is only gated in the clock signal timing cycles in office that row driving circuits 20 generate
Quasi- pixel 101 or a line pixel 102 to be corrected.
Further, digital calibration unit 50 includes multiple adders, multiple subtracters and multiple memory cell.Each
Adder, subtracter and memory cell correspond with an AD conversion unit 30 respectively；Each subtracter calculates and it
The difference of the first data signal that corresponding AD conversion unit 30 exports and benchmark data signal, and the difference is stored in and is somebody's turn to do
In memory cell corresponding to AD conversion unit 30, read with the 30 corresponding adder of AD conversion unit from the memory cell
Difference, ask for the second data signal and the difference sum and final output of the AD conversion unit 30 output.So as to row control
When gating a line pixel 102 to be corrected with drive circuit 20, the second number for being exported to row pixel to be corrected 102 through AD conversion
The correction of word signal can be carried out parallel.
Further, the output end of digital calibration unit 50 is multiple to be corresponded with AD conversion unit 30, with parallel
Export it is multiple it is calibrated after the second data signal.
Further, cmos pixel array generation coloured image, pel array is by multiple red pixels, multiple green pixels
And multiple blue pixels are formed.
As shown in Fig. 2 the cmos pixel array calibration system of second embodiment of the invention include pel array, row control and
Drive circuit 20, multiple AD conversion units 30, voltage generating unit 40, digital calibration unit 50 and data signal setup unit
60.Pel array also includes a line calibration pixel 101 and multirow pixel 102 to be corrected, and often capable number of pixels is equal.
Wherein calibration pixel 101, pixel to be corrected 102, row driving circuits 20 and digital calibration unit 50
Structure is identical with function and first embodiment of the invention.
Unlike first embodiment of the invention, AD conversion unit 30 is a ramp voltage formula analog-to-digital conversion list
Member, it also has a ramp voltage input；Voltage generating unit 40 also generates a ramp voltage to input AD conversion unit
Ramp voltage input, the second electricity that first voltage signal that calibration pixel 101 exports, pixel to be corrected 102 are exported
Pressure signal is separately converted to the first data signal and the second data signal.
Data signal setup unit 60 is used to set benchmark data signal, and it exports a base value to voltage generating unit 40
For generating reference voltage signal, it is also connected word signal with digital calibration unit 50, so that digital calibration unit 50 calculates the
The difference of one data signal and benchmark data signal.User can set benchmark data signal by data signal setup unit 60,
Benchmark data signal is that each pixel receives the data signal exported in theory after same amount of optical signal in pel array, first
The difference of data signal and benchmark data signal characterizes cmos pixel array with digital quantity and other circuits, part are believed to voltage
Number transfer tape come loss.
Based on the above-mentioned difference calculated, the embodiment is to each pixel 102 to be corrected in pel array after AD conversion
Second data signal of output is corrected, so that each region of cmos pixel array is close, imaging to the susceptibility of light
Homogeneity is good.
Further, a line school is only gated in the clock signal timing cycles in office that row driving circuits 20 generate
Quasi- pixel 101 or a line pixel 102 to be corrected.
Further, digital calibration unit 50 includes multiple adders, multiple subtracters and multiple memory cell.Each
Adder, subtracter and memory cell correspond with an AD conversion unit 30 respectively；Each subtracter calculates and it
The difference of the first data signal that corresponding AD conversion unit 30 exports and benchmark data signal, and the difference is stored in and is somebody's turn to do
In memory cell corresponding to AD conversion unit 30, read with the 30 corresponding adder of AD conversion unit from the memory cell
Difference, ask for the second data signal and the difference sum and final output of the AD conversion unit 30 output.Controlled according to row
The clock signal for being used to gate sent with drive circuit 20, the correction to the second data signal can be carried out parallel.
Further, the output end of digital calibration unit 50 is multiple to be corresponded with AD conversion unit 30, with parallel
Export it is multiple it is calibrated after the second data signal.
Further, cmos pixel array generation coloured image, pel array is by multiple red pixels, multiple green pixels
And multiple blue pixels are formed.
As shown in figure 3, third embodiment of the invention provides a kind of method that output to cmos pixel array is corrected,
Comprise the following steps：
S10, the one-row pixels of selected cmos pixel array are calibration pixel.
S11, a benchmark data signal is provided and is converted to a reference voltage signal through DA, and apply base to each calibration pixel
Quasi- voltage signal.
S12, the first voltage signal of each calibration pixel output of measurement, and be the first number through AD conversion by first voltage signal
Word signal.
S13, the difference for calculating the first data signal and benchmark data signal.
S14, according to the difference obtained in step S13, the second data signal is corrected, the second data signal is by pixel
The second voltage signal that each pixel to be corrected in array receives optical signal and exported obtains through AD conversion.
The embodiment is according to the first data signal and the difference of benchmark data signal, to each picture to be corrected in pel array
The second data signal for being exported after AD conversion of element is corrected, so as to the output of cmos pixel array image closer into
As when scene original appearance.
Further, step S14 is specifically included：
S141, gating a line pixel to be corrected, according to the difference obtained in step S13, to each pixel to be corrected in the row
Corresponding second data signal is corrected and exported；
S142, repeat the above steps S141, until often the second data signal corresponding to capable pixel to be corrected has been corrected
And export.
Above-described is only the preferred embodiments of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. a kind of cmos pixel array calibration system, including：
Pel array, it includes at least a line calibration pixel and multirow pixel to be corrected, the calibration pixel and pixel to be corrected
Set in the matrix form；The calibration pixel generates first voltage signal according to a reference voltage signal；The pixel to be corrected
Second voltage signal is generated based on opto-electronic conversion；
At least one AD conversion unit, for the calibration pixel is exported first voltage signal, the pixel to be corrected
The second voltage signal of output is separately converted to the first data signal and the second data signal, the number of the AD conversion unit
It is identical with the number of number and a line pixel to be calibrated of calibration pixel；
Voltage generating unit, for providing the reference voltage signal to the calibration pixel；
Row driving circuits, for generating one group of clock signal, the clock signal gates respectively calibrates picture described in a line
Pixel to be corrected described in element or a line；
Digital calibration unit, for first data signal and the difference of benchmark data signal, and according to the difference
Value is corrected and exported to second data signal.
2. cmos pixel array calibration system as claimed in claim 1, it is characterised in that the AD conversion unit is one oblique
Slope voltage-type AD conversion unit, it includes a ramp voltage input；The voltage generating unit also generates a ramp voltage
To input the ramp voltage input of the AD conversion unit, the first voltage signal that the calibration pixel is exported, institute
The second voltage signal for stating pixel output to be corrected is separately converted to first data signal and the second data signal.
3. cmos pixel array calibration system as claimed in claim 1, it is characterised in that the row driving circuits life
Into a clock signal timing cycles in office in only gate pixel to be corrected described in calibration pixel described in a line or a line.
4. cmos pixel array calibration system as claimed in claim 1, it is characterised in that the AD conversion unit is more
It is individual, and corresponded with the calibration pixel, so that multiple first voltage signals concurrently are converted into first numeral
Multiple second voltage signals are concurrently converted to second data signal by signal.
5. cmos pixel array calibration system as claimed in claim 4, it is characterised in that the digital calibration unit includes
Multiple adders, multiple subtracters and multiple memory cell, the adder, subtracter and memory cell respectively with it is described
AD conversion unit corresponds, and each subtracter calculates the first number of corresponding AD conversion unit output
Word signal and the difference of the benchmark data signal, and the difference is stored in the storage corresponding with the AD conversion unit
In unit, the adder corresponding with the AD conversion unit reads the difference from the memory cell, asks for the modulus and turns
Change the second data signal and the difference sum of unit output and export.
6. cmos pixel array calibration system as claimed in claim 5, it is characterised in that the digital calibration unit includes more
Individual output end, the output end and the AD conversion unit correspond, with parallel output it is multiple it is calibrated after described the
Two digital signal.
7. the cmos pixel array calibration system as any one of claim 1 to 6, it is characterised in that it also includes one
Data signal setup unit, the base value is exported for setting the benchmark data signal, and to the voltage generating unit
Word signal.
8. cmos pixel array calibration system as claimed in claim 7, it is characterised in that the pel array is used to generate coloured silk
Color image, the pel array are made up of multiple red pixels, multiple green pixels and multiple blue pixels.
9. a kind of method that output to cmos pixel array is corrected, comprises the following steps：
A), the one-row pixels for selecting the pel array are calibration pixel；
B), one benchmark data signal is provided and be converted to a reference voltage signal through DA, and applies institute to each calibration pixel
State reference voltage signal；
C), measure the first voltage signal of each calibration pixel output, and be the through AD conversion by the first voltage signal
One data signal；
D) difference of first data signal and the benchmark data signal, is calculated；
E), according to the difference obtained in step d), the second data signal is corrected, second data signal is by institute
The second voltage signal that each pixel to be corrected in pel array receives optical signal and exported is stated to obtain through AD conversion.
10. method as claimed in claim 9, it is characterised in that the step e) is specifically included：
Pixel to be corrected described in a line is gated, according to the difference obtained in step d), pixel to be corrected each to the row is corresponding
Second data signal be corrected and export；
Repeat the above steps, until often second data signal corresponding to the capable pixel to be corrected has been corrected.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1875395A (en) * | 2003-09-23 | 2006-12-06 | 伊格尼斯创新有限公司 | Electric circuit and method for driving luminescence pixel array |
| CN101521755A (en) * | 2008-12-15 | 2009-09-02 | 昆山锐芯微电子有限公司 | Cmos image sensor reading circuit and reading method |
| CN102647566A (en) * | 2011-02-17 | 2012-08-22 | 全视科技有限公司 | Analog row black level calibration for cmos image sensor |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4345004B2 (en) * | 2004-04-23 | 2009-10-14 | ソニー株式会社 | Optical black level adjustment circuit |
| US8045029B2 (en) * | 2004-04-26 | 2011-10-25 | Intellectual Ventures Ii Llc | CMOS image sensor for high speed signal processing |
| JP4351658B2 (en) * | 2005-07-21 | 2009-10-28 | マイクロン テクノロジー， インク． | Memory capacity reduction method, memory capacity reduction noise reduction circuit, and memory capacity reduction device |
| JP5407264B2 (en) * | 2008-10-09 | 2014-02-05 | ソニー株式会社 | Solid-state imaging device and camera system |
| US8625012B2 (en) * | 2009-02-05 | 2014-01-07 | The Hong Kong University Of Science And Technology | Apparatus and method for improving dynamic range and linearity of CMOS image sensor |
| US8310580B2 (en) * | 2009-07-27 | 2012-11-13 | Sony Corporation | Solid-state imaging device and camera system for suppressing occurrence of quantization vertical streaks |
| CN201837500U (en) * | 2010-10-22 | 2011-05-18 | 深圳市天微电子有限公司 | Tire pressure monitoring chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1875395A (en) * | 2003-09-23 | 2006-12-06 | 伊格尼斯创新有限公司 | Electric circuit and method for driving luminescence pixel array |
| CN101521755A (en) * | 2008-12-15 | 2009-09-02 | 昆山锐芯微电子有限公司 | Cmos image sensor reading circuit and reading method |
| CN102647566A (en) * | 2011-02-17 | 2012-08-22 | 全视科技有限公司 | Analog row black level calibration for cmos image sensor |
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