CN103067195A - Signalling system 7 collection system slot-time/data exchanging controller and implement method thereof - Google Patents
Signalling system 7 collection system slot-time/data exchanging controller and implement method thereof Download PDFInfo
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Abstract
The invention provides a signalling system 7 collection system slot-time/data exchanging controller which comprises an exchanging control board module, one or a plurality of line interface board modules, one or a plurality of back line-out board modules and a back board module. The signalling system 7 collection system slot-time/data exchanging controller is powerful in link processing capacity and has highly reliable access, and a physical link has automatic error redundancy processing capacity. The invention further provides a gain redundancy processing method of an E 1 link.
Description
Technical field
The invention belongs to communication technology application, particularly the Signaling System Number 7 passage based on E1 detects, and the time slot of Signaling System Number 7 acquisition system/exchanges data controller and its implementation.
Background technology
PCM (Pulse Code Modulation), namely pulse code modulation is a kind of technology that analog signal (such as speech) is changed into the digital signal that is suitable for transmitting by sampling, quantification and coding.
The PCM technology is widely used in communication network, and in the PCM circuit, the most frequently used line code is HDB3 code (HighDensity Bipoiar3), wherein uses the HDB3 coding among the E1.The link of each E1 has 32 time slots.0 time slot is used for frame to be delimited, and other remaining time slots both can the transmission of data, also can transferring voice, the wherein general command transmitting of the 16th time slot.Signaling System Number 7 acquisition system time slot/exchanges data controller (SuperDXC) is commonly called as the time slot convergence, hereinafter to be referred as SuperDXC.
Signalling system No.7 is called again common channel signalling.Namely with the signaling method of time division way a high speed data link transmission a group speech channel signaling, be generally used for interoffice.The Signaling System 7(SS-7) that uses in China is called Chinese Signaling System 7(SS-7).The SS7 net is the outer data communication network of a band, and it is superimposed upon on network operator's the switching network, is the important component part of supporting network.Signaling System 7(SS-7) adopts the multifunctional modular design, is a kind of signaling system that more is fit to digital communications network.
When E1 was used for Signaling System Number 7, in 32 time slots (Time Slot), the 0th time slot was used as frame synchronization information, and normal operation the 16th time slot is as the passage of signalling system No.7, and all the other 30 time slots are used as voice channel.In some system, sometimes also use other time slot to be used as the passage of signalling system No.7.
Because what signalling system No.7 used in link layer is the HDLC agreement, therefore in general collecting device all can be equipped with a plurality of HDLC passages to gather signaling data.When we need to monitor the signaling in the E1 transmission link, the signal collecting equipment of front end is overlapped on the E1 link that will monitor by E1 high resistant head, and the HDLC channel slot of configuration signal collecting device and the actual time slot correspondence that takies of signalling system No.7, the hdlc controller of collecting device receives signaling data and break into the Ethernet data bag, passes to background system data are processed and analyzed.
Because initial time slot and the shared timeslot number of signalling system No.7 in the E1 link is unfixed, need to the HDLC channel parameters of collecting device manually be arranged.If variation has occured in the shared time slot (comprising initial time slot position and timeslot number) of signaling, just need the manager of artificial notice collecting device again the parameter of HDLC passage to be configured, cumbersomely so also make mistakes easily.
In addition, in general the time slot in the E1 link only has a part wherein to be used for transmitting signalling system No.7, if directly the E1 link connection that will monitor to collecting device, this E1 interface resource to collecting device will form very large waste.
Signaling monitoring system is by the access of high-ohmic cross-connection, mirror image, bypass from signaling network, and the time slot convergence function by SuperDXC accurately copies signaling link, mainly is the signaling data of 16 slot transmission on the link.The position of SuperDXC in the networking is in signaling networking detection system foremost, in machine room telecommunications digital distribution frame (DDF), accurately gather 16 time slots among the E1, by self powerful time slot convergence aggregation feature, realize the 16 time slots input of each E1, the full time slot output of 32 time slots has made things convenient for the signaling monitoring system of rear end to carry out data acquisition and protocal analysis.Most equipment can only be supported 16 E1 at present, and access efficiency is low, poor stability.
In existing signaling monitoring system, mostly rely on high-ohmic cross-connection, the mirror image access scheme, the mode of high resistant has physically been isolated " transmission network " and " monitoring network system ", and the physical signalling of the two is independent of each other.The effect of the high resistant link physical signal of having decayed, the E1 chip internal adopt carry out first signal amplify after the technical scheme of framing again.The signaling of the 16th time slot is the object of monitoring in the E1 link, and the 16th time slot is distributed among each E1, and the E1 link on the DDF frame is many, and how numerous scattered time slot convergences being converged is a huge engineering.Gather link group for huge E1, the in good time state of each link needs the attendant to go to the scene to check, the investigation faulty link, and both wastes of manpower of such operation, also cumbersome, and make mistakes easily.
Summary of the invention
In order to solve the technical problem that exists in the Signaling System Number 7 acquisition system of above-mentioned present stage based on E1, just need to provide one to have powerful link processing ability, have high reliability access, physical link has the Signaling System Number 7 acquisition system time slot of wrong automatic redundant disposal ability/exchanges data controller.
The present invention proposes a kind of Signaling System Number 7 acquisition system time slot/exchanges data controller, comprise such as lower module: exchange control board module is used for the operation of control appliance each several part, from network interface, serial ports or E1 control mouthful reception control command; One or more line interface plate module, be used for extracting data from the E1 circuit and remove simultaneously shake, according to the system synchronization clock, comprise frame alignment signal, the data communication device that receives is crossed PCM BUS bus give the switching matrix that exchanges in the control board module, be used for time gas exchange, each line interface plate module has 64 input interfaces, 16 output interfaces; One or more rear outlet board modules are used for the E1 signal leading rear panel module that inputs or outputs, and by rear panel module and line interface base module communication, signal are not done any processing in the communication process; Rear panel module is used for connecting each functional module and reaches to each module for power supply.
An aspect according to the embodiment of the invention, every Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC extracts the 64Kbit/s time slot from the E1 signal of 256 or 64 2Mbit/s, synthetic 16 tunnel, 64 road or 128 road 2M signals output through synchronously, behind the switching matrix of these 64Kbit/s time slots, thus realize the intersection of multi-channel E 1 signal and copy.
According to an aspect of the embodiment of the invention, exchange control board module further comprises following part: CPU, CPLD module, switching matrix group, a plurality of E1 transceiver (E1LIU).
According to an aspect of the embodiment of the invention, the line interface plate module further comprises following part: a plurality of E1 transceivers (E1LIU), a bus driver module, 1 CPLD module.
The invention allows for a kind of gain redundancy processing method to the E1 link, comprise the steps:
The first step, (amplify or reduce) regulated in gain to the input of E1 link controller, the variation of gain causes that the signal power of every link of e1 controller input ensues change, causes like this framer of the inner rear end of e1 controller the situation that abnormality alarming (LOS or LOF or AIS or the alarm of CODE error code) or alarm are eliminated to occur;
Second step continues to detect the e1 controller Link State, if find that chain circuit alarming exists, then forwards for the 3rd step to;
The 3rd step, the chain circuit alarming of the e1 controller that detects is carried out redundancy process, in following period of time, after the multiple redundancy processing, the e1 controller chain circuit alarming still exists;
The 4th step, continuation is regulated (increase or reduce) to the gain of e1 controller link, until e1 controller chain circuit alarming state is eliminated, so just found the suitable yield value of every link of e1 controller, the use link does not have the link gain value in the alarm status situation, and system link is all settled out.
Description of drawings
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments:
Accompanying drawing 1 is the functional block diagram of the Signaling System Number 7 acquisition system time slot/exchanges data controller according to the embodiment of the invention.
Accompanying drawing 3 is depicted as the line interface base block diagram according to the embodiment of the invention.
Accompanying drawing 4 is depicted as the front view of Signaling System Number 7 acquisition system time slot according to the embodiment of the invention/exchanges data controller.
Accompanying drawing 6 is depicted as the basic principle that realizes according to the gain redundancy processing method of the E1 signal of the embodiment of the invention.
Fig. 7-1 is depicted as the redundant process chart (1) of gain-adjusted of the present invention.
Fig. 7-2 is depicted as the redundant process chart (2) of gain-adjusted of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
According to a specific embodiment of the present invention, a kind of Signaling System Number 7 acquisition system time slot/exchanges data controller (SuperDXC) is provided, every SuperDXC extracts the 64Kbit/s time slot from 256 or 64 2Mbit/sE1 signals, synthetic 16 tunnel, 64 road or 128 road 2M signals output through synchronously, behind the switching matrix of these 64Kbit/s time slots, thus realize the intersection of multi-channel E 1 signal and copy.SuperDXC comprises such as lower module:
Exchange control board module is used for the operation of control appliance each several part, from network interface, serial ports or E1 control mouthful reception control command.
One or more line interface plate module, be used for extracting data from the E1 circuit and remove simultaneously shake, according to system synchronization clock (comprising frame alignment signal), the data communication device that receives is crossed PCM BUS bus give switching matrix on the control board, be used for time gas exchange, every line interface base has 64 input interfaces, 16 output interfaces.
One or more rear outlet board modules are used for the E1 signal leading backboard that inputs or outputs, and by backboard and line interface board communications, signal are not done any processing in the communication process.
Rear panel module is used for connecting each functional module and reaches to each module for power supply.
The hardware of Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC can be achieved as follows function: the maximum access capability of separate unit is 256 2M signals, maximum crossing is the clog-free interconnection of 8192 * 2048 64K time slots, support simultaneously 64K, n * 64K, the interconnection of high speed 2M.Support the E1 interface physical layer alarm information indicating before the link access, such as LOS, LOF, AIS, RDI alarm, and test result passed to centralized-control center by network interface, E1 circuit; Control centre can realize concentrating warning information management, time slot configuration management.
The SuperDXC digital cross connect equipment adopts the design of modularization card insertion type structure, and integrated circuit board adopts 2mm industrial standard connector to connect.RMS2F reference standard CPCI Full-size card (6U) Design of Mechanical Structure, backboard is 4U (8 groove position), can be installed on standard 4U (8 groove position) CompactPCI cabinet (integrated circuit board, backboard and CompactPCI are incompatible), the part integrated circuit board is supported hot plug; Its power acquisition standard C ompactPCI power module, the duplicate supply Hot Spare is supported hot plug; Its capacity of trunk is option and installment as required.
The SuperDXC digital cross connect equipment is mainly by 1 exchange control board, 1-4 piece line interface base, outlet board and 1 backboard consist of behind the 1-4 piece, give each functional module power supply by system power supply, the system monitoring module links to each other with switching control module, operation conditions to each functional module is monitored, in case monitor warning information or operating trouble, just report switching control module, hardware block diagram is as shown in Figure 1.
Exchange control board module can be by with MPC860T (the core frequency 50MHz of Motorola Inc., support 10/100BASE-T) be the embedded processor system of core, switching matrix chipset with the large scale digital switching matrix MT90826 of Zarlink company formation, and the interface chips such as Ethernet interface, E1 circuit, logic auxiliary circuit realize that specific implementation is referring to accompanying drawing 2.Switching control module can be achieved as follows function:
A) operation of control appliance each several part is from network interface, serial ports or E1 control mouthful reception control command;
B) (PCM BUS bus is the technology that the E1 signal synthetic a tunnel that the multi-path line interface unit receives is transmitted to extracting and be put into PCM BUS bus by line interface base from the E1 circuit, here the spy refers to the synthetic 8M data flow circuit of 4 road 2M data, adopt this technology can save limited connector resource, make things convenient for wiring board design) on the E1 signal do time gas exchange, and send back to line interface base by PCM BUS bus;
C) receive and the clock selecting to be recovered from the E1 circuit by line interface base as the system synchronization clock, and the system synchronization clock, comprise frame alignment signal, be distributed to the circuit that needs, comprise LIM;
Line interface unit (LIU) array that LIM can be comprised of 4 road E1 line interface chip DS21Q50 of MAXIM-DALLAS company, can receive and dispatch 16 * 4 road E1 signals, and the auxiliary circuit such as total line traffic control consists of by totally 16.LIM can be achieved as follows function:
A) extract data from the E1 circuit and remove simultaneously shake, according to the system synchronization clock, comprise frame alignment signal, the data communication device that receives is crossed PCM BUS bus give switching matrix on the control board, be used for time gas exchange, every line interface base has 64 input interfaces, 16 output interfaces;
B) by the data after the PCM BUS reception control board time gas exchange, generate the output of E1 signal;
C) extract line clock;
D) on the line interface base of RMS2F with the hot plug control circuit;
The outlet board module can be achieved as follows function:
With I/O E1 signal leading backboard, give line interface base (signal not being done any processing) by backboard, pcb board adopts the differential lines wiring rule.
Every outlet board has 64 input interfaces, 32 output interfaces.
Rear panel module can be achieved as follows function:
Connecting each functional module reaches to each module for power supply, with reference to CompactPCI backboard Design of Mechanical Structure.
Next, function and the specific implementation of all modules of Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC are described in detail.
The realization block diagram of switching control module can be referring to accompanying drawing 2.The CPU of exchange control board module can adopt the MPC860T processor, and core frequency 50MHz, FLASH ROM can adopt AM29LV160D FLASH rom chip, 16Mbit, 16 of data-bus widths.Its data/address bus links to each other with CPU through drive circuit.By CSO control addressing.Be used for storage facilities software and preserve parameter.SDRAM can adopt 4 SDRAM holders, forms 32Mbyte holder space, 32 of data-bus widths, and its data/address bus directly links to each other with CPU.By CS2 (CS_SDRAM) control addressing.Be used for the program operation fully.CPLD can adopt XC95144XL, and its Main Function has two: the one, support the cpu system operation, and produce necessary bus logic signal (sheet choosing); Another function is control PCM data clock, in namely selecting or external clock as system synchronization, and after producing various clock signals, send to modules (TDM of line interface base, matrix, LIU, CPU).
The switching matrix group can adopt 3 MT90826, is the core component of realizing that digital crossover connects.Adopt two-stage cascade to use input 2M number of signals as the requirement of 4 times of output 2M number of signals.64 8M PCM BUS signals that namely are comprised of by PCM BUS 256 2M signals (4 line interface bases respectively access 64 tunnel) enter respectively two chip matrixs (each 32 road input signal), after time gas exchange, flow to second level chip matrix 32 road signals, again through its time gas exchange, export 16 road 8M PCM BUS signals and send line interface base (every plank 4 tunnel) back to, behind LIU, can generate totally 64 road E1 signals.
LIU chip and chip matrix on the line interface base are all supported PCM BUS, do not need extra circuit auxiliary.Can reduce wiring board cabling and connector quantity.
E1LIU can adopt DS21Q50, contains 4 road E1 transceivers.Wherein one the tunnel is used for receiving the E1 control signal, sends the TDM circuit of CPU to.One the tunnel is used for recovering the E1BITS clock (gives CPLD by its inner PLL direct frequency doubling, selects as the system synchronization clock for it behind 16.384MHz.
10/100BASE-T PHY can adopt LXT970A, and it is the 10/100BASE-T PHY device of standard, has standard MII interface, directly links to each other with the MII interface of CPU, is used for Ethernet to the control of equipment.
RS232 is used for transferring the RS232 serial ports of surveying, and is connected to the SMC port of CPU.
Temperature sensor can adopt MAX6509, is a kind of cheaply temperature sensor, and its temperature warning thresholding can be set by non-essential resistance.Be used for the temperature on the observation circuit plate.
PLL can adopt CY2071AF.The clock that is used for the 2.048MHz square wave of input, sinusoidal wave frequency multiplication are produced 16.384MHz is selected as the system synchronization clock for it to CPLD.
Plate border interface: the interface of exchange control board and other modules of equipment is all by being connected to realize with backboard.
Line interface base Model Implement block diagram can be referring to accompanying drawing 3.The E1 LIU of line interface plate module can adopt DS21Q50, and single-chip four transceivers work under the 8M IBO pattern (PCM BUS).Bus driver can adopt 74LVT16245, to reduce the load of exchange control board bus driver.CPLD can adopt XC95144XL, is used for bus logic control (producing the sheet choosing), and selects line-recovered clock (16.384MHz delivers to the exchange control board, as system clock).
Clock drives: drive the PCM clock signal of system by the exchange control board.
Hot-swapping controller (and hot plug switch): adopt MAX4271, be used for the hot plug of control circuit interface board, and when circuit power transships, cut off the electricity supply protective circuit
Temperature sensor: adopting MAX6509, is a kind of cheaply temperature sensor, and its temperature warning thresholding can be set by non-essential resistance.Be used for the temperature on the observation circuit plate.
The distribution of memory headroom is determined jointly by the inner chip selection logic of CPLD and CPU.
The effect of rear outlet board module is that the E1 line signal on the line interface base is drawn, and signal is not done any processing, only does connection.
The front view of Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC equipment as shown in Figure 4.
The rearview of Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC equipment as shown in Figure 5.
Time-slot cross by input copies, and SuperDXC supports the full time slot input of 256 E1, and the full time slot of 64 E1 is exported, and has satisfied the extraction convergence function of 16 sequence control signalings in every speech channel of telecommunications digital distribution frame (DDF).
For hundreds of E1 on the DDF frame, traditional collecting device is restrained and is converged, and access capacity is very limited, and the quantity of access E1 is few.SuperDXC has realized the interconnection of large capacity E1 circuit digital, and 64～256 2M signals are converted to any 16～64 2M signals outputs (clog-free interconnection).Have multistage convergence function, by a plurality of DXC cascades, product extends to the transfer capability of any amount 2M.
At present domestic manufacturer does not support non-framing (unframe) link, and SuperDXC has realized that framing (frame) link or non-framing (unframe) link are configurable, has realized that framing link and non-framing link mix access way.
The signaling monitoring system front end uses SuperDXC by high-ohmic cross-connection, mirror image access.The mode of high-ohmic cross-connection is isolated transmission network and signaling monitoring system, the such physical signalling process that a decay arranged and amplify, the effect of the high resistant signal of having decayed, E1 chip internal adopt carry out first signal amplify after the principle of framing again.If deal with improperly after the signal attenuation, cause easily distorted signals, circuit produces a large amount of error codes, so how gain is regulated? it is much rear suitable to be adjusted to, front end can or can not produce error code, this process has one to comprise the redundancy determination that line signal is interfered from gain-adjusted-alarm feedback-gain-adjusted process repeatedly, does not have an alarm until link is working properly.The high resistant access had both been supported in input, also supported 120 Ω access; Export 75 Ω, 120 Ω are optional.
In order to solve the technical problem, according to one embodiment of present invention, proposed a kind of gain redundancy processing method to the E1 signal, be used for control is regulated in the gain of the E1 link of Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC equipment.More weak through the link physical signal behind the high-ohmic cross-connection, need to amplify signal and decode.Whether physical signalling can successfully decode depends on whether distortion of signal after the amplification.If physical signalling too a little less than so the E1 chip can not be correctly decoded, if the excessive so link of physical signalling also can produce the code error code.What is gain amplified on earth? this depends on the quality of link signal.The action of this gain-adjusted is to be controlled by the CPU on Signaling System Number 7 acquisition system time slot/exchanges data controller SuperDXC to finish, concrete realization can realize by embedded software, also can realize by the mode that hardware or software and hardware combine.
The principle that the gain redundancy processing method of E1 signal is realized is as shown in Figure 6: the mode that is combined by CPU control embedded software, hardware or software and hardware is regulated the gain of E1 link; The based on feedback link alarm; Interpretation is processed, and alarm is redundant to be processed, and be sure of that link has alarm; The alarm feedback; Continue to regulate the chip gain, until chain circuit alarming is eliminated; No longer chip is regulated gain, until system stability gets off.
Concrete performing step is:
The first step, (amplify or reduce) regulated in gain to the input of E1 link controller, the variation of gain causes that the signal power of every link of e1 controller input ensues change, causes like this framer of the inner rear end of e1 controller the situation that abnormality alarming (LOS or LOF or AIS or the alarm of CODE error code) or alarm are eliminated to occur;
Second step continues to detect the e1 controller Link State, if find that chain circuit alarming exists, then forwards for the 3rd step to;
The 3rd step, the chain circuit alarming of the e1 controller that detects is carried out redundancy process, in following period of time, after the multiple redundancy processing, the e1 controller chain circuit alarming still exists;
The 4th step, continuation is regulated (increase or reduce) to the gain of e1 controller link, until e1 controller chain circuit alarming state is eliminated, so just found the suitable yield value of every link of e1 controller, the use link does not have the link gain value in the alarm status situation, and system link is all settled out.
By top such circulation feedback procedure, end-use device uses suitable link gain, select a link clock that does not have alarm as system clock from 256 links of input, the quality of system clock has determined whether SuperDXC can carry out reliable and stable work again.This shows that the redundant major function of processing of the gain of E1 signal is the selection of link gain adjusting and system clock.
The redundant process chart of the gain of E1 signal such as Fig. 7-1 and 7-2.Detailed process is described below:
By a process autoAdjustGain, carry out once every one second interval, automatically regulate the chip gain;
1. 256 physical link code of each time scan round error code state, statistics leave (the corresponding variable setGainCounts state of each link) in the ver variable in.
2. do you judge that it is 0 that some Link State gains arrange? if 0, then turn back to the beginning entrance and continue cycle detection.If non-zero status, do you judge that so this poll detects number of times pollNum and reached 100 times? behind poll 100 times, process begins detection statistics (every poll 100 times, unification are removed the counting of adding up and done a final response action) from entrance again.
3. if wrap count reaches 100 times, begin to judge that the correct number of times rightNum of each link is less than 50? if it is wrong many that correct number of times less than 50, illustrates, errNumInLongTime is cumulative for the link error counting.If correct number of times rightNum illustrates so that greater than 50 link is relatively stable within a period of time, link time counting errNumInLongTime is clear 0, and it is clear 0 that link is correctly counted, and turn step 4.If wrap count pollNum turns step 4. less than 100 times
4. detect link LOS or LOF arranged? if do not have LOS or LOF, returning entrance, to carry out next time that poll detects and remove error counter errNum be 0, and correct counter rightNum accumulates once.If LOS or LOF are arranged, error counter errNum accumulates once and jumps to step 5;
5. is misjudgment counter errNum less than 5? is long counter errNumInLongTime less than 3 during link error? if condition all satisfies, be similar to so and think that current link gain is correct, flow process is returned the poll that entrance execution in step 1 is carried out next time.If condition does not satisfy, execution in step 6.
6. judge whether yield value gainFail reaches maximum gain and count GAIN_FAIL_MAX_NUM (4), is finding simultaneously gain flag F indGain 0?
7. if condition satisfies, illustrate that all yield values of each link attempt being provided with one time, in a plurality of yield values of a link, do not find suitable gain, error count errNum clear 0, GainFail clear 0, flow process is restarted step 1 like this, and chain circuit alarming and error situation are added up in all gains of each link of poll again again.If condition is satisfied, obtain a yield value from the link gain tabulation so and be configured to the current link of System on Chip/SoC, finish this inspection judgement flow process and return, restart step 1, carry out gain configuration and the judgement of next round.
Because the configuration of each gain all causes the variation of chain circuit alarming state, this state feeds back to gain by chip and judges interface, so after link gain arranges, can cause immediately the variation of Link State, the variation meeting of Link State changes because of flow process.This is the process of a positive feedback.Until link finds suitable yield value automatically, eliminate chain circuit alarming, system link is all settled out.
It should be appreciated by those skilled in the art, the mode that method and apparatus of the present invention can adopt hardware, software or hardware and software to combine realizes by variety of ways such as microprocessor, digital signal processor, field programmable logic unit or gate arrays.
In sum, although the present invention with the preferred embodiment disclosure as above, yet it is not to limit the present invention.The general technical staff of the technical field of the invention without departing from the spirit and scope of the present invention, can do various changes and modification.Therefore, protection scope of the present invention is as the criterion when looking accompanying the scope that claim defines.
Claims (8)
1. Signaling System Number 7 acquisition system time slot/exchanges data controller (SuperDXC) is characterized in that, comprises such as lower module:
Exchange control board module is used for the operation of control appliance each several part, from network interface, serial ports or E1 control mouthful reception control command;
One or more line interface plate module, be used for extracting data from the E1 circuit and remove simultaneously shake, according to the system synchronization clock, comprise frame alignment signal, the data communication device that receives is crossed PCM BUS bus give the switching matrix that exchanges in the control board module, be used for time gas exchange, each line interface plate module has 64 input interfaces, 16 output interfaces;
One or more rear outlet board modules are used for the E1 signal leading rear panel module that inputs or outputs, and by rear panel module and line interface base module communication, signal are not done any processing in the communication process;
Rear panel module is used for connecting each functional module and reaches to each module for power supply.
2. Signaling System Number 7 acquisition system time slot as claimed in claim 1/exchanges data controller, it is characterized in that: every SuperDXC extracts the 64Kbit/s time slot from the E1 signal of 256 or 64 2Mbit/s, synthetic 16 tunnel, 64 road or 128 road 2M signals output through synchronously, behind the switching matrix of these 64Kbit/s time slots, thus realize the intersection of multi-channel E 1 signal and copy.
3. Signaling System Number 7 acquisition system time slot as claimed in claim 1/exchanges data controller, it is characterized in that exchange control board module further comprises following part: CPU, CPLD module, switching matrix group, a plurality of E1 transceiver (E1 LIU).
4. Signaling System Number 7 acquisition system time slot as claimed in claim 1/exchanges data controller is characterized in that the line interface plate module further comprises following part: a plurality of E1 transceivers (E1LIU), a bus driver module, 1 CPLD module.
5. the gain redundancy processing method to the E1 link is characterized in that, comprises the steps:
The first step, input gain to the E1 link controller is regulated, the variation of gain causes that the signal power of every link of e1 controller input ensues change, causes like this framer of the inner rear end of e1 controller the situation that abnormality alarming or alarm are eliminated to occur;
Second step continues to detect the e1 controller Link State, if find that chain circuit alarming exists, then forwards for the 3rd step to;
The 3rd step, the chain circuit alarming of the e1 controller that detects is carried out redundancy process, in following period of time, after the multiple redundancy processing, the e1 controller chain circuit alarming still exists;
The 4th step, continuation is regulated the gain of e1 controller link, until e1 controller chain circuit alarming state is eliminated, has so just found the suitable yield value of every link of e1 controller, the use link does not have the link gain value in the alarm status situation, and system link is all settled out.
6. method as claimed in claim 5 is characterized in that, also comprises: last, and from 256 links of input, select a link clock that does not have alarm as system clock.
7. method as claimed in claim 5, it is characterized in that: the abnormality alarming in the first step is LOS, LOF, AIS or the alarm of CODE error code.
8. method as claimed in claim 5 is characterized in that: can be amplification or reduce the adjusting that gains.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104244119A (en) * | 2013-12-26 | 2014-12-24 | 深圳市邦彦信息技术有限公司 | Time slot exchange device and method based on FPGA |
| CN108664433A (en) * | 2018-05-11 | 2018-10-16 | 成都坤恒顺维科技股份有限公司 | A kind of low time delay shake high speed signal switching technology and the backboard using the Technology design |
| CN110225211A (en) * | 2019-05-07 | 2019-09-10 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Multichannel pulse modified modulating voice exchange system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104244119A (en) * | 2013-12-26 | 2014-12-24 | 深圳市邦彦信息技术有限公司 | Time slot exchange device and method based on FPGA |
| CN104244119B (en) * | 2013-12-26 | 2018-05-08 | 邦彦技术股份有限公司 | Time slot exchange device and method based on FPGA |
| CN108664433A (en) * | 2018-05-11 | 2018-10-16 | 成都坤恒顺维科技股份有限公司 | A kind of low time delay shake high speed signal switching technology and the backboard using the Technology design |
| CN110225211A (en) * | 2019-05-07 | 2019-09-10 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Multichannel pulse modified modulating voice exchange system and method |
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