CN103066936B - A kind of prime amplifier is by controlling the offset correction method of time delay - Google Patents
A kind of prime amplifier is by controlling the offset correction method of time delay Download PDFInfo
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- CN103066936B CN103066936B CN201210569537.0A CN201210569537A CN103066936B CN 103066936 B CN103066936 B CN 103066936B CN 201210569537 A CN201210569537 A CN 201210569537A CN 103066936 B CN103066936 B CN 103066936B
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Abstract
The invention discloses a kind of prime amplifier by controlling the offset correction method of time delay, described prime amplifier comprises the first PMOS transistor, second PMOS transistor, 3rd nmos pass transistor, 4th nmos pass transistor and the 5th nmos pass transistor, by carrying out regulable control to the signal initial time of the control signal on load pipe first PMOS transistor MP1 and the second PMOS transistor MP2 grid, thus regulate the average current on the branch road of the left and right sides, and then when there is imbalance in circuit, also can guarantee that power supply is equal to the pressure drop of left and right sides output Nodes, thus guarantee that output end voltage Voutp and Voutn is equal, imbalance is corrected.Prime amplifier of the present invention is by controlling, in the offset correction method of time delay, not need to set up controllable electric perhaps metal-oxide-semiconductor in preamplifier circuit, therefore can not cause load effect to input terminal voltage.
Description
Technical field
The present invention relates to analog circuit prime amplifier, particularly relate to a kind of offset correction method of prime amplifier.
Background technology
The circuit structure diagram of prime amplifier as shown in Figure 1, comprises the first PMOS transistor MP1, the second PMOS transistor MP2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4 and the 5th nmos pass transistor MN5.Wherein, the grid connection control signal CLKP of the first PMOS transistor MP1, the source electrode of the first PMOS transistor MP1 connects power vd D, and the drain electrode of the first PMOS transistor MP1 is connected with the drain electrode of the 3rd nmos pass transistor MN3, the reverse output voltage Voutn of the end output amplifier that is connected; The grid connection control signal CLKP of the second PMOS transistor MP2, the source electrode of the second PMOS transistor MP2 connects power vd D, the drain electrode of the second PMOS transistor MP2 is connected with the drain electrode of the 4th nmos pass transistor MN4, the forward output voltage Voutp of the end output amplifier that is connected; The source electrode of the 3rd nmos pass transistor MN3 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 3rd nmos pass transistor MN3 connects forward input voltage vin p; The source electrode of the 4th nmos pass transistor MN4 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 4th nmos pass transistor MN4 connects reverse input voltage vin n; The source ground GND of the 5th nmos pass transistor MN5, the grid connection control signal CLKP of the 5th nmos pass transistor MN5.Drive the sequential chart of the control signal CLKP of the first PMOS transistor MP1, the second PMOS transistor MP2 and the 5th nmos pass transistor MN5 as shown in Figure 2, its clock signal clk according to prime amplifier work produces, frequency is identical with the frequency of clock signal clk, amplitude initial value is 0, and steady-state value is supply voltage value VDD.Control signal produces t1 moment input clock signal CLK in circuit, then, after postponing a bit of time t2 moment, start to produce control signal CLKP.
During the work of this prime amplifier, under the driving of control signal CLKP, there is electric current in circuit in prime amplifier, completes the amplification to input signal (forward input voltage vin p deducts reverse input voltage vin n).During work, the first PMOS transistor MP1 and the second PMOS transistor MP2 is as load pipe, and the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4 is as input pipe, and the 5th nmos pass transistor MN5 is as the offset providing bias current.If the left branch road of circuit (MP1-MN3 branch road) and right branch road (MP2-MN4 branch road) both sides full symmetric, then when inputting equal forward input voltage vin p and reverse input voltage vin n, in circuit, to flow through electric current equal for the right and left, in circuit, forward output voltage Voutp equals reverse output voltage Voutn, now there is not imbalance in circuit.But, under practical situation, impossible full symmetric about circuit, in circuit, the size of the mismatch of components and parts such as the first PMOS transistor MP1 and the second PMOS transistor MP2 is unequal, or the size of the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4 is unequal, these factors all can cause occurring offset voltage in amplifier, as input voltage vin p=Vinn, the electric current that the right and left flows through is unequal, and in output voltage, Vinp is not equal to Vinn.The resolution capability of prime amplifier to input signal can be reduced after there is imbalance.As prevented large device as a part for dynamic comparer, then and then reduce the resolution capability of dynamic comparer to input signal.
In order to correct the offset voltage existed in the large device of prevention, controllable capacitor array can be connected at output node Voutp with Voutn of prime amplifier, reduce offset voltage by the size of regulating capacitor array capacitor.Also at the two ends paralleling MOS pipe of input pipe the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4, offset voltage can be reduced by regulating the gate bias voltage of metal-oxide-semiconductor.But these two kinds are reduced in the method for offset voltage, the controllable capacitor being connected to prime amplifier output node or the metal-oxide-semiconductor being connected in parallel on input pipe both sides all can produce load effect to output voltage Voutp and Voutn, thus reduce the speed of prime amplifier.As prevented large device as a part for dynamic comparer, then and then the speed of comparator can be reduced.
Summary of the invention
Technical problem to be solved by this invention is: make up above-mentioned the deficiencies in the prior art, a kind of prime amplifier is proposed by controlling the offset correction method of time delay, offset voltage in prime amplifier can be corrected, load effect can not be caused to input terminal voltage simultaneously.
Technical problem of the present invention is solved by following technical scheme:
A kind of prime amplifier is by controlling the offset correction method of time delay, described prime amplifier comprises the first PMOS transistor, second PMOS transistor, 3rd nmos pass transistor, 4th nmos pass transistor and the 5th nmos pass transistor, the source electrode of described first PMOS transistor connects power supply, and the drain electrode of described first PMOS transistor is connected with the drain electrode of described 3rd nmos pass transistor, the reverse output voltage of the end output amplifier that is connected; The source electrode of described second PMOS transistor connects power supply, and the drain electrode of described second PMOS transistor is connected with the drain electrode of described 4th nmos pass transistor, the forward output voltage of the end output amplifier that is connected; The source electrode of described 3rd nmos pass transistor is connected with the drain electrode of described 5th nmos pass transistor, and the grid of described 3rd nmos pass transistor connects forward input voltage; The source electrode of described 4th nmos pass transistor is connected with the drain electrode of described 5th nmos pass transistor, and the grid of described 4th nmos pass transistor connects reverse input voltage; The source ground of described 5th nmos pass transistor, the grid of described 5th nmos pass transistor connects the 3rd control signal; The grid of described first PMOS transistor connects the first control signal, and the grid of described second PMOS transistor connects the second control signal; Described control method comprises the following steps: before adjustment, and the signal initial time controlling described first control signal and described second control signal is positioned at synchronization, is set to for the first moment; The described forward input voltage that control inputs is equal and described reverse input power, then when regulating:
The first situation: if imbalance is greater than described reverse output voltage for described forward output voltage, then keep the signal initial time of described second control signal constant, regulate described first control signal in the following manner: the initial value 11) setting moment point, described initial value is greater than described first moment, is less than the moment that described 3rd control signal reaches stable state; 12) more new record current correction number of times, the signal initial time controlling described first control signal is the value of described moment point; 13) judge whether the value of current correction number of times equals set point, if not, then enters step 14); If so, then adjustment process is terminated; 14) judge the size of now described forward output voltage and described reverse output voltage, if described forward output voltage is still greater than described reverse output voltage, then the described moment is tuned up, return step 12); If described forward output voltage is less than described reverse output voltage, then the described moment is turned down, return step 12);
Second case: if imbalance is less than described reverse output voltage for described forward output voltage, then keep the signal initial time of described first control signal constant, regulate described second control signal in the following manner: the initial value 21) setting moment point, described initial value is greater than described first moment, is less than the moment that described 3rd control signal reaches stable state; 22) more new record current correction number of times, the signal initial time controlling described second control signal is the value of described moment point; 23) judge whether the value of now number of corrections equals set point, if not, then enters step 24); If so, then adjustment process is terminated; 24) judge the size of now described forward output voltage and described reverse output voltage, if described forward output voltage is still less than described reverse output voltage, then the described moment is tuned up, return step 22); If described forward output voltage is greater than described reverse output voltage, then the described moment is turned down; Return step 22).
The beneficial effect that the present invention is compared with the prior art is:
The offset correction method of prime amplifier of the present invention, by carrying out regulable control to the signal initial time of the control signal on load pipe first PMOS transistor MP1 and the second PMOS transistor MP2 grid, thus regulate the average current on the branch road of the left and right sides, and then when there is imbalance in circuit, also can guarantee that power supply is equal to the pressure drop of left and right sides output Nodes, thus guarantee that output end voltage Voutp and Voutn is equal, imbalance is corrected.In bearing calibration of the present invention, do not need in preamplifier circuit, set up controllable electric perhaps metal-oxide-semiconductor, therefore can not cause load effect to input terminal voltage.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of prime amplifier in prior art;
Fig. 2 is the sequential chart of the control signal in prior art in prime amplifier;
Fig. 3 is the circuit structure diagram of the prime amplifier in the specific embodiment of the invention;
Fig. 4 is for the flow chart regulating the first control signal during the first imbalance situation in the prime amplifier in the specific embodiment of the invention;
Fig. 5 is the sequential chart for control signal during the first imbalance situation in the prime amplifier in the specific embodiment of the invention;
Fig. 6 is for the transient current-time plot regulating both sides branch road all around during the first imbalance situation in the prime amplifier in the specific embodiment of the invention;
Fig. 7 is for the flow chart regulating the second control signal during the second imbalance situation in the prime amplifier in the specific embodiment of the invention;
Fig. 8 is the sequential chart for control signal during the second imbalance situation in the prime amplifier in the specific embodiment of the invention;
Fig. 9 is for the transient current-time plot regulating both sides branch road all around during the second imbalance situation in the prime amplifier in the specific embodiment of the invention.
Embodiment
Contrast accompanying drawing below in conjunction with embodiment the present invention is described in further details.
In this embodiment, a kind of offset correction method of prime amplifier is proposed, for there is imbalance in prime amplifier, when having offset voltage to be formed, when input forward input voltage vin p equals reverse input voltage vin n, output forward output voltage Voutp as far as possible close to equaling reverse output voltage Voutn, can reduce offset voltage to the impact of circuit.Offset correction method for prime amplifier circuit structure diagram as shown in Figure 3, prime amplifier comprises the first PMOS transistor, the second PMOS transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor.
Wherein, identical in the same prior art that is connected to each other of five metal-oxide-semiconductors, the source electrode MP1 of the first PMOS transistor connects power vd D, and the drain electrode of the first PMOS transistor MP1 is connected with the drain electrode of the 3rd nmos pass transistor MN3, the reverse output voltage Voutn of the end output amplifier that is connected; The source electrode of the second PMOS transistor MP2 connects power vd D, and the drain electrode of the second PMOS transistor MP2 is connected with the drain electrode of the 4th nmos pass transistor MN4, the forward output voltage Voutp of the end output amplifier that is connected; The source electrode of the 3rd nmos pass transistor MN3 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 3rd nmos pass transistor MN3 connects forward input voltage vin p; The source electrode of the 4th nmos pass transistor MN4 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 4th nmos pass transistor MN4 connects reverse input voltage vin n; The source ground of the 5th nmos pass transistor MN5, the grid of the 5th nmos pass transistor MN5 connects the 3rd control signal CLKP.3rd control signal CLKP is identical with prior art, is equally to produce circuit by control signal to produce according to the clock signal clk of prime amplifier work, and frequency is identical with the frequency of clock signal clk.Control signal produces the clock signal clk of circuit at t1 moment (as shown in Figure 5) input prime amplifier, then in the t2 moment (as shown in Figure 5) after postponing a bit of time, start to produce the 3rd control signal CLKP.Circuit structure is with the difference be connected in prior art: the grid of the first PMOS transistor connects the first control signal CLK1, and the grid of the second PMOS transistor connects the second control signal CLK2.To be point situation carry out continuous initial time adjustment to one of them of the first control signal CLK1 and the second control signal CLK2 to offset correction method, generation initial time does not wait has two of delay control signals to be applied on the grid of two load metal-oxide-semiconductors (MP1 and MP2) each other, realize the correction to offset voltage, load effect can not be caused to output simultaneously.
Before correction adjustment, the first control signal CLK1 and the second control signal CLK2 initial time are positioned at synchronization, are set to for the first moment.This first moment can be identical with the initial time t2 of the 3rd control signal CLKP, also can the initial time t2 time delay for some time of relative 3rd control signal CLKP.In this embodiment, control described first moment identical with the initial time t2 of described 3rd control signal CLKP, namely control signal produces circuit after t1 moment input clock signal CLK, postpones the t2 moment after a period of time to produce the first control signal CLK1, the second control signal CLK2 and the 3rd control signal CLKP exports simultaneously.But it should be noted that, the control before regulating mainly need guarantee that the initial time of the first control signal CLK1 and the second control signal CLK2 is positioned at synchronization herein.Simultaneously, the forward input voltage vin p that control inputs is equal and reverse input power Vinn, if now there is imbalance in prime amplifier, then there will be two kinds of situations, one is that imbalance makes the 3rd nmos pass transistor MN3 flow through larger electric current I the 1, four nmos pass transistor MN4 to flow through less electric current I 2, so under the load resistance that load pipe (MP1 with MP2) is identical, pressure drop on MP1 is comparatively large, then oppositely output voltage Voutn can be less, namely there will be Voutp > Voutn.Two is that imbalance makes the 3rd nmos pass transistor MN3 flow through less electric current I 1,4th nmos pass transistor MN4 flows through larger electric current I 2, so under the load resistance that load pipe (MP1 with MP2) is identical, pressure drop on MP1 is less, then oppositely output voltage Voutn can be comparatively large, namely there will be Voutp < Voutn.According to these two kinds of situations, take corresponding measure respectively.
In a first situation, lack of proper care as forward output voltage Voutp is greater than reverse output voltage Voutn, then keep the signal initial time of the second control signal CLK2 constant, regulate the first control signal CLK1 in the following manner, flow chart during adjustment as shown in Figure 4.Adjustment process comprises the following steps:
11) the initial value tb1 of moment point tb is set.Wherein, initial value tb1 is greater than described first moment, is less than the moment that described 3rd control signal CLKP reaches stable state.
In this step, requiring to be greater than for the first moment, is namely ensure that follow-up first control signal CLK1 can produce time delay by relative second control signal CLK2; Requiring to be less than the moment that CLKP reaches stable state, is to ensure that the first control signal CLK1 at least applies before the 3rd control signal reaches stable state, is unlikely to delay too of a specified duration.In this embodiment, initial value tb1 is and is greater than moment t2, is less than moment t3(as shown in Figure 5).In this embodiment, moment point was greater than for the first moment, same setting moment before referring to relative to two moment (operation time as initial in circuit be 0 or receive clock signal start to produce the moment t1 etc. of control signal), moment point and the time difference in setting moment are greater than time difference in the first moment and setting moment.After the setting moment, the first moment first arrived, and arrived after moment point.Moment point is less than the stable state moment, same setting moment before referring to relative to two moment (operation time as initial in circuit be 0 or receive clock signal start to produce the moment t1 etc. of control signal), moment point and the time difference in setting moment are less than time difference in stable state moment and setting moment.After the setting moment, the first moment first arrived, and arrived after moment point, then was arrive in the stable state moment.
12) more new record current correction number of times, the signal initial time controlling the first control signal CLK1 is the value of moment point tb.
As shown in Figure 5, be the sequential chart of each control signal under this kind of imbalance situation.After regulating the initial time of the first control signal CLK1, the t2 moment only produces the 3rd control signal CLKP and the second control signal CLK2, after postponing a period of time, just produces the first control signal CLK1 to the tb moment.
As shown in Figure 6, be the curve chart of the transient current-time in adjustment all around two branch roads.Figure middle and upper part is divided into the curve chart before adjustment, and bottom is divided into the curve chart after adjustment.Can obtain from figure: for the first time before correction adjustment, produce applying control signal at moment t2 simultaneously, imbalance makes the transient current I1 that left branch flows through larger, the transient current I2 that right branch flows through is less, and the moment arriving conducting stable state after two branch roads apply control signal is always identical, as moment T in Fig. 6.Then moment t2 is in moment T time section, the average current (as drawn the area of horizontal line part in Fig. 6) of left branch is also greater than the average current (as drawn the area of oblique line portion in Fig. 6) of right branch, thus pressure drop in left branch is comparatively large, occurs the detuning phenomena of Voutp > Voutn.And after regulating, first control signal just produces at moment tb and is applied with, then left branch occurs that the moment of electric current postpones to some extent, thus the curve of electric current I 1 moves to right along time shaft in Fig. 6, make left branch to occur the moment (i.e. tb) of electric current diminished relatively to the time difference in the moment (i.e. T) of steady operation, thus the average current of left branch diminishes, pressure drop on MP1 is diminished (being tending towards equal with pressure drop on MP2), reverse output voltage Voutn is then made to become large, make two output end voltages be tending towards equal, improve imbalance.Timing for the first time, current correction number of times is 1, then the signal initial time of the first control signal CLK1 is initial value tb1.During second-order correction, current correction number of times is 2, then the value tb2 returned after the signal initial time of the first control signal CLK1 is follow-up adjustment.The rest may be inferred, until last timing, current correction number of times is set point N, then the value tbN returned after the signal initial time of the first control signal CLK1 is follow-up adjustment, after this terminates adjustment, and signal initial time keeps tbN constant.
13) judge whether the value of current correction number of times equals set point, if not, then enters step 14); If so, then adjustment process is terminated.
In this step, the judgement of setting number of corrections, when more the number of corrections of new record arrives the set point that presets N time in step 12), namely represents that correction adjustment has reached user's instructions for use, thus terminates correction.After this signal initial time of the first control signal CLK1 is remained value tbN during last adjustment.Number of corrections set point N then by the user of prime amplifier according to the speed of offset correction and required precision sets itself.
14) size of now forward output voltage Voutp and reverse output voltage Voutn is judged, if forward output voltage Voutp is still greater than reverse output voltage Voutn, then represent that now offset correction regulates not yet in place, moment point tb is tuned up, return step 12), thus continue the delay time increasing the first control signal CLK1 that load pipe MP1 applies, continue to shorten in left branch and apply the time difference that the signal moment reaches the stable state moment, continue to reduce the average current in left branch, improve offset influence further, until reach the number of corrections of setting.If forward output voltage Voutp is less than reverse output voltage Voutn, the Best Point that then represents that now offset correction is adjusted, arrive another imbalance situation, then moment point tb is turned down, return step 12), both sides output voltage is made to be tending towards the value of equal tb, until reach the number of corrections of setting to find.
In the adjustment process of above-mentioned control signal, only regulate the signal initial time of the first control signal CLK1, frequency and amplitude determine according to the clock signal clk of described prime amplifier, the same with amplitude with the frequency of clock signal clk.
Preferably, in step 11), the initial value of moment point tb is set to the median in the first moment t2 to stable state moment t3 interval, when tuning up moment point tb in step 14) or turn moment point tb down, all gets interval median.Such as, the initial value of time adjustment point tb can be set to the median t4 that (t2, t3) is interval, when needing to tune up tb after initial value gets t4, then get the median t5 of tb for interval (t4, t3); Need to turn tb down after initial value gets t4, then get the median t6 of tb for interval (t2, t4), the like.The method of getting median is adopted to accelerate adjustment process.
By above-mentioned control, namely achieve under the first imbalance situation, input pipe MN3 pipe flows through larger transient current, and left branch produces output voltage Voutn in the relatively short time from applying the signal to steady operation; Input pipe MN4 pipe flows through less transient current, right branch produces output voltage Voutp in the relatively long time from applying the signal to steady operation, the pressure drop of power vd D after overload pipe MP1 is made to be tending towards equal with the pressure drop after overload MP2 after repeatedly regulating, reach output voltage forward output voltage Voutp to be tending towards equaling reverse output voltage Voutn, thus reduce the offset voltage influence even eliminating prime amplifier.
In this case, lack of proper care as forward output voltage Voutp is less than reverse output voltage Voutn, then keep the signal initial time of the first control signal CLK1 constant, regulate the second control signal CLK2 in the following manner, flow chart during adjustment as shown in Figure 7.Adjustment process comprises the following steps:
21) the initial value tb1 of moment point tb is set.Wherein, initial value tb1 is greater than aforementioned first moment, is less than the moment that described 3rd control signal CLKP reaches stable state.
In this step, requiring to be greater than for the first moment, is namely ensure that follow-up second control signal CLK2 can produce time delay by relative first control signal CLK1; Requiring to be less than the moment that CLKP reaches stable state, is to ensure that the second control signal CLK2 at least applies before the 3rd control signal reaches stable state, is unlikely to delay too of a specified duration.。Be in this embodiment and be greater than moment t2, be less than moment t3(as shown in Figure 8).
22) more new record current correction number of times, the signal initial time controlling the second control signal CLK2 is the value of moment point tb.
As shown in Figure 8, be the sequential chart of each control signal under this kind of imbalance situation.After regulating the initial time of the second control signal CLK2, the t2 moment only produces the 3rd control signal CLKP and the first control signal CLK1, after postponing a period of time, just produces the second control signal CLK2 to the tb moment.
As shown in Figure 9, be the curve chart of the transient current-time in adjustment all around two branch roads.Figure middle and upper part is divided into the curve chart before adjustment, and bottom is divided into the curve chart after adjustment.Can obtain from figure: for the first time before correction adjustment, produce applying control signal at moment t2 simultaneously, imbalance makes the transient current I1 that left branch flows through less, the transient current I2 that right branch flows through is larger, and the moment arriving conducting stable state after two branch roads apply control signal is always identical, as moment T in Fig. 9.Then moment t2 is in moment T time section, the average current (as drawn the area of horizontal line part in Fig. 9) of right branch is also greater than the average current (as drawn the area of oblique line portion in Fig. 9) of left branch, thus pressure drop in right branch is comparatively large, occurs the detuning phenomena of Voutp < Voutn.And after regulating, second control signal just produces at moment tb and is applied with, then right branch occurs that the moment of electric current postpones to some extent, thus the curve of electric current I 2 moves to right along time shaft in Fig. 9, make right branch to occur the moment (i.e. tb) of electric current diminished relatively to the time difference in the moment (i.e. T) of steady operation, thus the average current of right branch diminishes, pressure drop on MP2 is diminished (being tending towards equal with pressure drop on MP1), forward output voltage Voutp is then made to become large, make two output end voltages be tending towards equal, improve imbalance.Similarly, timing for the first time, current correction number of times is 1, then the signal initial time of the second control signal CLK2 is initial value tb1.During second-order correction, current correction number of times is 2, then the value tb2 returned after the signal initial time of the second control signal CLK2 is follow-up adjustment.The rest may be inferred, until last timing, current correction number of times is set point N, then the value tbN returned after the signal initial time of the second control signal CLK2 is follow-up adjustment, after this terminates adjustment, and signal initial time keeps tbN constant.
23) judge whether the value of current correction number of times equals set point, if not, then enters step 24); If so, then adjustment process is terminated.Similarly, number of corrections set point N then by the user of prime amplifier according to the speed of offset correction and required precision sets itself.
24) size of now forward output voltage Voutp and reverse output voltage Voutn is judged, if forward output voltage Voutp is still less than reverse output voltage Voutn, then represent that now offset correction regulates not yet in place, moment point tb is tuned up, return step 22), thus continue the delay time increasing the second control signal CLK2 that load pipe MP2 applies, continue to shorten in left branch and apply the time difference that the signal moment reaches the stable state moment, continue to reduce the average current in right branch, improve offset influence further, until reach the number of corrections of setting.If forward output voltage Voutp is greater than reverse output voltage Voutn, then the Best Point that represents that now offset correction is adjusted, has arrived another imbalance situation, has then been turned down by moment point tb; Return step 22), to find the value making both sides output voltage be tending towards equal tb, until reach the number of corrections of setting.
Similarly, in the adjustment process of above-mentioned control signal, only regulate the signal initial time of the second control signal CLK2, frequency and amplitude determine according to the clock signal clk of described prime amplifier, the same with amplitude with the frequency of clock signal clk.
Equally preferably, step 21) in, the initial value of moment point tb is set to the median of the first moment to stable state moment interval, be the median in interval (t2, t3), step 24) in when tuning up moment point tb or turn moment point tb down, all get interval median, can adjustment process be accelerated.
By above-mentioned control, namely achieve under the second imbalance situation, input pipe MN3 pipe flows through less transient current, and left branch produces output voltage Voutn in the relatively long time from applying the signal to steady operation; Input pipe MN4 pipe flows through larger transient current, right branch produces output voltage Voutp in the relatively short time from applying the signal to steady operation, the pressure drop of power vd D after overload pipe MP1 is made to be tending towards equal with the pressure drop after overload MP2 after repeatedly regulating, reach output voltage forward output voltage Voutp to be tending towards equaling reverse output voltage Voutn, thus reduce the offset voltage influence even eliminating prime amplifier.
The offset correction method of this embodiment, according to above-mentioned adjustment process: the first, the comparative result (magnitude relationship of Voutp and Voutn) applying the first control signal CLK1 and the second control signal CLK2 according to synchronization before correction is determined to need adjustment first control signal CLK1 or the second control signal CLK2.After determining, do not need will remain unchanged in the trimming process of the control signal of adjustment then below, need the control signal of adjustment then will continue conditioning signal initial time in trimming process below, until whole trimming process terminates.The second, do not need the signal adjusting signal initial time can be identical with the 3rd control signal CLKP in trimming process, its signal initial time be all set to moment t2, therefore can share a signal generating circuit; The signal adjusting signal initial time is needed to compare with CLKP signal the change should only had on initial time, one section of time delay moment tp after moment t2 produces and applies, and signal generating circuit can increase delay circuit and carry out adjusting on the basis that the 3rd control signal produces circuit.3rd, for the prime amplifier shown in Fig. 3, in order to ensure that it normally works, MP3 and MP4 needs to turn off completely, and therefore the maximum of CLK1 and CLK2 signal is VDD.
The offset correction method of this embodiment, control the initial time of the control signal of prime amplifier two load metal-oxide-semiconductor (MP1 and MP2) grids, make the time difference on the branch road of the left and right sides from generation current to steady operation different, namely mean that the average current on the branch road of left and right is different, namely the pressure drop voltage on load pipe is different, thus realizes the correction to prime amplifier input offset voltage.Do not need in offset correction process to set up controllable electric perhaps metal-oxide-semiconductor in preamplifier circuit, therefore can not cause load effect to input terminal voltage, thus can guarantee the speed of amplifier during offset correction yet.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, make some substituting or obvious modification without departing from the inventive concept of the premise, and performance or purposes identical, all should be considered as belonging to protection scope of the present invention.
Claims (3)
1. a prime amplifier is by controlling the offset correction method of time delay, described prime amplifier comprises the first PMOS transistor, second PMOS transistor, 3rd nmos pass transistor, 4th nmos pass transistor and the 5th nmos pass transistor, the source electrode of described first PMOS transistor connects power supply, and the drain electrode of described first PMOS transistor is connected with the drain electrode of described 3rd nmos pass transistor, the reverse output voltage (Voutn) of the end output amplifier that is connected; The source electrode of described second PMOS transistor connects power supply, and the drain electrode of described second PMOS transistor is connected with the drain electrode of described 4th nmos pass transistor, the forward output voltage (Voutp) of the end output amplifier that is connected; The source electrode of described 3rd nmos pass transistor is connected with the drain electrode of described 5th nmos pass transistor, and the grid of described 3rd nmos pass transistor connects forward input voltage (Vinp); The source electrode of described 4th nmos pass transistor is connected with the drain electrode of described 5th nmos pass transistor, and the grid of described 4th nmos pass transistor connects reverse input voltage (Vinn); The source ground of described 5th nmos pass transistor, the grid of described 5th nmos pass transistor connects the 3rd control signal (CLKP);
It is characterized in that: the grid of described first PMOS transistor connects the first control signal (CLK1), the grid of described second PMOS transistor connects the second control signal (CLK2); Described offset correction method comprises the following steps: before adjustment, and the signal initial time controlling described first control signal (CLK1) and described second control signal (CLK2) is positioned at synchronization, is set to for the first moment; The described forward input voltage (Vinp) that control inputs is equal and described reverse input power (Vinn), then when regulating:
The first situation: if imbalance is greater than described reverse output voltage (Voutn) for described forward output voltage (Voutp), then keep the signal initial time of described second control signal (CLK2) constant, regulate described first control signal (CLK1) in the following manner: the initial value 11) setting moment point (tb), described initial value is greater than described first moment, is less than the moment that described 3rd control signal (CLKP) reaches stable state; 12) more new record current correction number of times, the signal initial time controlling described first control signal (CLK1) is the value of described moment point (tb); 13) judge whether the value of current correction number of times equals set point, if not, then enters step 14); If so, then adjustment process is terminated; 14) size of now described forward output voltage (Voutp) and described reverse output voltage (Voutn) is judged, if described forward output voltage (Voutp) is still greater than described reverse output voltage (Voutn), then described moment point (tb) is tuned up, return step 12); If described forward output voltage (Voutp) is less than described reverse output voltage (Voutn), then described moment point (tb) is turned down, return step 12);
Second case: if imbalance is less than described reverse output voltage (Voutn) for described forward output voltage (Voutp), then keep the signal initial time of described first control signal (CLK1) constant, regulate described second control signal (CLK2) in the following manner: the initial value 21) setting moment point (tb), described initial value is greater than described first moment, is less than the moment that described 3rd control signal (CLKP) reaches stable state; 22) more new record current correction number of times, the signal initial time controlling described second control signal (CLK2) is the value of described moment point (tb); 23) judge whether the value of now number of corrections equals set point, if not, then enters step 24); If so, then adjustment process is terminated; 24) size of now described forward output voltage (Voutp) and described reverse output voltage (Voutn) is judged, if described forward output voltage (Voutp) is still less than described reverse output voltage (Voutn), then described moment point (tb) is tuned up, return step 22); If described forward output voltage (Voutp) is greater than described reverse output voltage (Voutn), then described moment point (tb) is turned down; Return step 22).
2. prime amplifier according to claim 1 is by controlling the offset correction method of time delay, it is characterized in that: step 11 in the first situation described) in or described second case step 21) in the initial value of moment point (tb) be set to median in described first moment to described stable state moment interval.
3. prime amplifier according to claim 1 is by controlling the offset correction method of time delay, it is characterized in that: step 14 in the first situation described) in or described second case step 24) in all get the median of interval range when tuning up or turn down described moment point (tb); When tuning up described moment point (tb), described interval range is (x, t3); When turning described moment point (tb) down, described interval range is (t2, x), and wherein, x represents the value of moment point (tb) before current adjustment, and t2 represented for the first moment, and t3 represents the stable state moment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210569537.0A CN103066936B (en) | 2012-12-25 | 2012-12-25 | A kind of prime amplifier is by controlling the offset correction method of time delay |
| HK13106690.5A HK1179771A1 (en) | 2012-12-25 | 2013-06-05 | A method for offset adjusting of preamplifier by controlling delay |
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| CN201210569537.0A CN103066936B (en) | 2012-12-25 | 2012-12-25 | A kind of prime amplifier is by controlling the offset correction method of time delay |
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| CN201323555Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | Signal preamplifier circuit |
| CN101610070A (en) * | 2008-06-19 | 2009-12-23 | 承景科技股份有限公司 | The method of preamplifier and middle calibrated offset voltage thereof |
| CN101964661A (en) * | 2009-07-23 | 2011-02-02 | 雷凌科技股份有限公司 | Comparator for pipeline type analog-digital converter and related signal sampling method |
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|---|---|---|---|---|
| US7683716B2 (en) * | 2008-06-04 | 2010-03-23 | Texas Instruments Incorporated | Constant output common mode voltage of a pre-amplifier circuit |
| JP2010213042A (en) * | 2009-03-11 | 2010-09-24 | Renesas Electronics Corp | Amplifier circuit and analog/digital conversion circuit |
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2012
- 2012-12-25 CN CN201210569537.0A patent/CN103066936B/en not_active Expired - Fee Related
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| CN101610070A (en) * | 2008-06-19 | 2009-12-23 | 承景科技股份有限公司 | The method of preamplifier and middle calibrated offset voltage thereof |
| CN201323555Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | Signal preamplifier circuit |
| CN101964661A (en) * | 2009-07-23 | 2011-02-02 | 雷凌科技股份有限公司 | Comparator for pipeline type analog-digital converter and related signal sampling method |
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| HK1179771A1 (en) | 2013-10-04 |
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