CN103066072B - Positive-intrinsic-negative (PIN) diode array structure and manufacturing method thereof - Google Patents
Positive-intrinsic-negative (PIN) diode array structure and manufacturing method thereof Download PDFInfo
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- CN103066072B CN103066072B CN201110316107.3A CN201110316107A CN103066072B CN 103066072 B CN103066072 B CN 103066072B CN 201110316107 A CN201110316107 A CN 201110316107A CN 103066072 B CN103066072 B CN 103066072B
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Abstract
The invention discloses a positive-intrinsic-negative (PIN) diode array structure. The structure is formed by a plurality of PIN diodes which are connected in parallel. The each PIN diode comprises a substrate, an N type cathode, an intrinsic semiconductor, a P type anode, an isolation region and an N-type outer-base-region cathode. The N type cathode which is in a round sheet shape is formed above the substrate. The 1.2 micron-3 micron intrinsic semiconductor is grown above a middle portion of the N type cathode with the round sheet shape. The N-type outer-base-region cathode with an annular shape is formed above a peripheral portion of the N type cathode with the round sheet shape. The P type anode with the round sheet shape is formed above a central area of the intrinsic semiconductor which is far from an N type cathode terminal. The invention also discloses a manufacturing method of the PIN diode array structure. According to the invention, through increasing a thickness of an epitaxial layer and reducing leakage of electricity during reverse bias, reverse isolation of a large signal is improved when a reverse bias voltage is increased. A stray capacitance is minimized through a parallel connection of same units and design optimization. A small positive series resistance and the positive and negative stray capacitances are obtained so as to reduce positive insertion losses.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, specifically belong to a kind of the PIN diode array and the manufacture method thereof that are compatible with the high-isolation low-insertion loss of bipolar technology.
Background technology
The typical apply of radio frequency electric switch is wireless transceiver.Wireless transceiver as shown in Figure 1, is made up of following four parts: power amplifier (PA), low noise amplifier (LNA), radio frequency electric switch, logic control circuit usually.Power amplifier and low noise amplifier are connected to antenna by radio frequency electric switch, and radio frequency signal transmits and receives.Because the signal passing to antenna from power amplifier is sufficiently strong, connected radio frequency electric switch needs as far as possible low forward conduction loss.And to low noise amplifier, the signal come from power amplifier can be come in from reverse-biased radio frequency electric switch thus form signal cross-talk, connected radio frequency electric switch needs as far as possible high reverse isolation.Owing to being applied to the transmitting and receiving of radio-frequency front-end, radio frequency electric switch must possess transmission delay as far as possible low, low, reverse isolation degree is as far as possible high and can process the feature being greater than 100 milliwatt signals as far as possible to insert (forward conduction) loss.
PIN diode meets above requirement, and it is a kind of radio frequency electric switch, is widely used in needing radio frequency signal to carry out in the circuit opened and closed.PIN diode (positive – intrinsic-negative diode) is by highly doped p type anode, non-impurity-doped or low-doped wide intrinsic silicon area (Intrinsic), and highly doped N-type negative electrode composition, its operation principle is: when PIN diode add one exceed the voltage of conduction threshold time, low-doped intrinsic silicon area is completely depleted, junction capacitance increases rapidly, and conducting resistance (insertion loss) reduces; When diode is reverse-biased, width of depletion region is approximately equal to intrinsic silicon sector width, and junction capacitance is very little, and conducting resistance is very large, and isolation is very high.The insertion loss of PIN diode and isolation are similar to and square being directly proportional of the thickness of intrinsic silicon area.So, to low insertion loss requirement, intrinsic silicon area thickness to be reduced as far as possible; To high-isolation requirement, then need to increase intrinsic silicon area thickness as far as possible.
The form of conventional PIN diode many employings discrete device, product existing packaged on market is sold, and shortcoming is that needs are external on pcb board, and volume is large, costly.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of PIN diode array structure, and insertion loss is low, and reverse isolation degree is high and its manufacturing process can be compatible with bipolar technology.
For solving the problems of the technologies described above, the invention provides a kind of PIN diode array structure, described array structure is composed in parallel by multiple PIN diode single tube, each PIN diode single tube comprises substrate, N-type negative electrode, intrinsic semiconductor, p type anode, isolated area, N-type outer base area negative electrode, described surface is formed with disc-shaped N-type negative electrode, above the mid portion of disc-shaped N-type negative electrode, growth has thickness to be the intrinsic semiconductor of 1.2 μm ~ 3 μm, the circular N-type outer base area negative electrode coaxial with disc-shaped N-type negative electrode is formed above the peripheral part of disc-shaped N-type negative electrode, described intrinsic semiconductor is affixed with circular N-type outer base area negative electrode near the periphery of described N-type cathode terminal, the disc-shaped p type anode coaxial with disc-shaped N-type negative electrode is formed above the middle section of described intrinsic semiconductor away from N-type cathode terminal, described intrinsic semiconductor is isolated by the circular isolated area coaxial with disc-shaped N-type negative electrode with between the negative electrode of circular N-type outer base area away from the periphery of N-type cathode terminal and disc-shaped p type anode periphery, described array structure is in square, and adjacent PIN diode single tube shares N-type outer base area negative electrode.
Preferably, described N-type negative electrode is octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, and described isolated area is that octagon is circular, and described p type anode is octagon disc-shaped.
Further, be formed with P type isolated area below the isolated area between described p type anode and N-type outer base area negative electrode, described intrinsic semiconductor is formed with P type isolated area away from below the isolated area between the periphery of N-type cathode terminal and N-type outer base area negative electrode.
Further, described isolated area is the isolation of field oxygen, or shallow trench isolation from, or the isolation of field oxygen or shallow trench isolation from the middle of increase deep trench.
For solving the problems of the technologies described above, present invention also offers a kind of manufacture method of PIN diode array structure, comprising the following steps:
Step one, P type substrate carries out N-type ion implantation, forms a disc-shaped N-type negative electrode;
Step 2, carries out outer layer growth at the whole upper surface of base plate comprising disc-shaped N-type negative electrode, forms the intrinsic semiconductor that thickness is 1.2 μm ~ 3 μm;
Step 3, the epitaxial loayer above disc-shaped N-type negative electrode forms the circular isolated area coaxial with disc-shaped N-type negative electrode;
Step 4, the epitaxial loayer outside circular isolated area outer rim, the outer rim along circular isolated area is carried out N ion implantation and to be gone directly disc-shaped N-type negative electrode, is formed coaxial with disc-shaped N-type negative electrode and is connected the circular N-type outer base area negative electrode of disc-shaped N-type negative electrode;
Step 5, above the epitaxial loayer in circular isolated area inner edge, the boron ion implantation of carrying out high dose forms the highly doped disc-shaped p type anode coaxial with disc-shaped N-type negative electrode, forms PIN diode single tube;
Step 6, carries out parallel connection by multiple PIN diode single tube, and adjacent PIN diode single tube shares circular N-type outer base area negative electrode, forms array structure.
Further, P type ion implantation is carried out below circular isolated area between disc-shaped p type anode and circular N-type outer base area negative electrode, form circular P type isolated area, simultaneously carry out P type ion implantation at epitaxial loayer away from below the circular isolated area between the periphery of disc-shaped N-type cathode terminal and circular N-type outer base area negative electrode, form circular P type isolated area.The ion implantation dosage of described circular P type isolated area is 10
14cm
-2~ 5x10
15cm
-2, Implantation Energy is 50keV ~ 200keV.
Wherein, the injection ion of described disc-shaped N-type negative electrode is arsenic, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 50keV ~ 100keV; Described epitaxial loayer is that non-impurity-doped or N-type are low-doped, and doping content is 10
14cm
-3~ 10
16cm
-3; The injection ion of described circular N-type outer base area negative electrode is phosphorus, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 50keV ~ 100keV; The injection ion of disc-shaped p type anode is boron, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 5keV ~ 50keV.
Wherein, described N-type negative electrode is octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, and described isolated area is that octagon is circular, and described p type anode is octagon disc-shaped.
Pin diode switch of the present invention is by increasing the thickness of epitaxial loayer, reduce electric leakage during reverse bias, the reverse isolation degree of large-signal is improved when increasing reverse bias voltage, and by the design of in parallel identical unit optimization, regulate forward and reverse static bias voltage, parasitic capacitance is minimized, obtains less forward series resistance and forward and reverse parasitic capacitance, reduce forward insertion loss, when realizing process unlike signal intensity, meet the requirement of insertion loss and reverse isolation degree simultaneously.Meanwhile, pin diode switch of the present invention can be integrated in germanium silicon (or conventional) bipolar technology, does not need to increase the cost of technology, for the complete function realizing wireless transceiver at single-chip provides low cost solution.
Accompanying drawing explanation
Below in conjunction with the drawings and the specific embodiments, the present invention is described in further detail.
Fig. 1 is wireless transceiver schematic diagram;
Fig. 2 is the schematic top plan view of PIN diode array structure of the present invention;
Fig. 3-Fig. 5 is the device architecture schematic diagram in PIN diode single tube manufacturing process of the present invention;
Fig. 6 is the device architecture schematic top plan view of PIN diode single tube of the present invention.
Embodiment
PIN diode array structure of the present invention, is composed in parallel by multiple PIN diode single tube, and each PIN diode single tube comprises substrate 1, N-type negative electrode 2, intrinsic semiconductor 3, p type anode 7, isolated area 4, N-type outer base area negative electrode 5.For making parasitic capacitance minimum, the in parallel array formed is preferably or close to square, array structure vertical view as shown in Figure 2, described array structure has 9 PIN diode single tubes to form the quadrate array of 3 × 3, and adjacent PIN diode single tube shares N-type outer base area negative electrode 5.
Disc-shaped N-type negative electrode 2 is formed above described substrate 1, above the mid portion of disc-shaped N-type negative electrode 2, growth has thickness to be the intrinsic semiconductor 3 of 1.2 μm ~ 3 μm, the circular N-type outer base area negative electrode 5 coaxial with disc-shaped N-type negative electrode 2 is formed above the peripheral part of disc-shaped N-type negative electrode 2, described intrinsic semiconductor 3 is affixed with circular N-type outer base area negative electrode 5 near the periphery of described N-type negative electrode 2 end, the disc-shaped p type anode 7 coaxial with disc-shaped N-type negative electrode 2 is formed above the middle section of described intrinsic semiconductor 3 away from N-type negative electrode 2 end, described intrinsic semiconductor 3 is isolated by the circular isolated area 4 coaxial with disc-shaped N-type negative electrode 2 with between the negative electrode of circular N-type outer base area 5 away from the periphery of N-type negative electrode 2 end and disc-shaped p type anode 7 periphery.
Be formed with P type isolated area 6 below isolated area 4 between described p type anode 7 and N-type outer base area negative electrode 5, described intrinsic semiconductor 3 is formed with P type isolated area 6 away from below the isolated area 4 between the periphery of N-type negative electrode 2 end and N-type outer base area negative electrode 5.
Described isolated area 4 be field oxygen isolation, or shallow trench isolation from, or oxygen on the scene isolation or shallow trench isolation from the middle of increase deep trench.
Described substrate 1, N-type negative electrode 2, p type anode 7, isolated area 4, N-type outer base area negative electrode 5, P type isolated area 6 can be the shape close to circle such as regular hexagon, octagon, positive ten hexagons simultaneously, in the preferred embodiment, as shown in Figure 6, described N-type negative electrode 2 is octagon disc-shaped, described N-type outer base area negative electrode 5 is that octagon is circular, described isolated area 4 is that octagon is circular, described p type anode 7 is octagon disc-shaped, and described P type isolated area 6 is that octagon is circular.
The manufacture method of the PIN diode array structure in the present embodiment, as shown in Figures 3 to 5, comprises the following steps:
Step one, P-type silicon substrate 1 carries out N-type ion implantation, forms a disc-shaped N-type negative electrode 2, and the injection ion of N-type negative electrode 2 is arsenic, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 50keV ~ 100keV;
Step 2, carries out outer layer growth at whole silicon substrate 1 upper surface comprising disc-shaped N-type negative electrode 2, forms the intrinsic semiconductor 3 that thickness is 1.2 μm ~ 3 μm, as shown in Figure 3, described epitaxial loayer is that non-impurity-doped or N-type are low-doped, and impurity is phosphorus, and doping content is 10
14cm
-3~ 10
16cm
-3;
Step 3, epitaxial loayer outside circular isolated area 4 outer rim, outer rim along circular isolated area 4 is carried out N ion implantation and to be gone directly disc-shaped N-type negative electrode 2, formed coaxial with disc-shaped N-type negative electrode 2 and be connected the circular N-type outer base area negative electrode 5 of disc-shaped N-type negative electrode 2, the injection ion of described circular N-type outer base area negative electrode 5 is phosphorus, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 50keV ~ 100keV;
Step 4, P type ion implantation is carried out below circular isolated area 4 between disc-shaped p type anode 7 and circular N-type outer base area negative electrode 5, form circular P type isolated area 6, simultaneously carry out P type ion implantation at epitaxial loayer away from below the circular isolated area 4 between the periphery of disc-shaped N-type negative electrode 2 end and circular N-type outer base area negative electrode 5, form circular P type isolated area 6; The ion implantation dosage of described circular P type isolated area is 10
14cm
-2~ 5x10
15cm
-2, Implantation Energy is 50keV ~ 200keV, and the distance between described annular P type isolated area 6 and N-type negative electrode 2 is 2 ~ 5 microns, forms reverse junction isolation;
Step 5, the epitaxial loayer above disc-shaped N-type negative electrode 2 forms the circular isolated area 4 coaxial with disc-shaped N-type negative electrode 2, and described isolated area 4 is the isolation of field oxygen, or shallow trench isolation from, or oxygen on the scene isolation or shallow trench isolation from middle increase deep trench;
Step 6, above epitaxial loayer in circular isolated area 4 inner edge, carry out the boron ion implantation of high dose, form the highly doped disc-shaped p type anode 7 coaxial with disc-shaped N-type negative electrode, or add that outer base area boron injects the highly doped p type anode of formation with germanium and silicon epitaxial in germanium silicon technology; The injection ion of disc-shaped p type anode 7 is boron, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 5keV ~ 50keV, forms PIN diode single tube;
Step 7, carries out parallel connection by multiple PIN diode single tube, and adjacent PIN diode single tube shares circular N-type outer base area negative electrode 5, forms array structure.
The periphery use oxygen of array structure or shallow trench isolation from, also can add deep trench isolation again in the middle of oxygen on the scene or shallow trench.
The present invention, by increasing the thickness of N-type epitaxy layer, reduces electric leakage during reverse bias, thus utilizes the method increasing reverse bias voltage to improve the reverse isolation degree of large-signal.Simultaneously in order to avoid insertion loss that the increase of N-type epitaxy layer thickness causes the increase of forward series resistance namely higher, the present invention is again by the identical unit of parallel connection and optimal design carrys out minimum parasitic capacitance, obtain less forward series resistance and forward and reverse parasitic capacitance, can be integrated into like this in bipolar technology flow process and realize satisfactory radio frequency electric switch, thus realize the complete function of wireless transceiver on a single chip, do not need to increase the cost of technology, for the complete function realizing wireless transceiver at single-chip provides low cost solution.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. a PIN diode array structure, is characterized in that,
Described array structure is composed in parallel by multiple PIN diode single tube;
Each PIN diode single tube comprises substrate, N-type negative electrode, intrinsic semiconductor, p type anode, isolated area, N-type outer base area negative electrode;
Described surface is formed with disc-shaped N-type negative electrode, above the mid portion of disc-shaped N-type negative electrode, growth has thickness to be the intrinsic semiconductor of 1.2 μm ~ 3 μm, the circular N-type outer base area negative electrode coaxial with disc-shaped N-type negative electrode is formed above the peripheral part of disc-shaped N-type negative electrode, described intrinsic semiconductor is affixed with circular N-type outer base area negative electrode near the periphery of described N-type cathode terminal, the disc-shaped p type anode coaxial with disc-shaped N-type negative electrode is formed above the middle section of described intrinsic semiconductor away from N-type cathode terminal, described intrinsic semiconductor is isolated by the circular isolated area coaxial with disc-shaped N-type negative electrode with between the negative electrode of circular N-type outer base area away from the periphery of N-type cathode terminal and disc-shaped p type anode periphery,
Described array structure is in square, and adjacent PIN diode single tube shares N-type outer base area negative electrode.
2. PIN diode array structure according to claim 1, it is characterized in that, described N-type negative electrode is octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, described isolated area is that octagon is circular, and described p type anode is octagon disc-shaped.
3. PIN diode array structure according to claim 1, it is characterized in that, be formed with P type isolated area below isolated area between described p type anode and N-type outer base area negative electrode, described intrinsic semiconductor is formed with P type isolated area away from below the isolated area between the periphery of N-type cathode terminal and N-type outer base area negative electrode.
4. PIN diode array structure according to claim 3, is characterized in that, described isolated area is the isolation of field oxygen, or shallow trench isolation from, or the isolation of field oxygen or shallow trench isolation from the middle of increase deep trench.
5. a manufacture method for PIN diode array structure, is characterized in that, comprises the following steps:
Step one, P type substrate carries out N-type ion implantation, forms a disc-shaped N-type negative electrode;
Step 2, carries out outer layer growth at the whole upper surface of base plate comprising disc-shaped N-type negative electrode, forms the intrinsic semiconductor that thickness is 1.2 μm ~ 3 μm;
Step 3, the epitaxial loayer outside circular isolated area outer rim, the outer rim along circular isolated area is carried out N ion implantation and to be gone directly disc-shaped N-type negative electrode, is formed coaxial with disc-shaped N-type negative electrode and is connected the circular N-type outer base area negative electrode of disc-shaped N-type negative electrode;
Step 4, the epitaxial loayer above disc-shaped N-type negative electrode forms the circular isolated area coaxial with disc-shaped N-type negative electrode;
Step 5, above the epitaxial loayer in circular isolated area inner edge, the boron ion implantation of carrying out high dose forms the highly doped disc-shaped p type anode coaxial with disc-shaped N-type negative electrode, forms PIN diode single tube;
Step 6, carries out parallel connection by multiple PIN diode single tube, and adjacent PIN diode single tube shares circular N-type outer base area negative electrode, forms array structure.
6. the manufacture method of PIN diode array structure according to claim 5, it is characterized in that, after step 3, P type ion implantation is carried out below circular isolated area between disc-shaped p type anode and circular N-type outer base area negative electrode, form circular P type isolated area, simultaneously carry out P type ion implantation at epitaxial loayer away from below the circular isolated area between the periphery of disc-shaped N-type cathode terminal and circular N-type outer base area negative electrode, form circular P type isolated area, and then carry out step 4.
7. the manufacture method of PIN diode array structure according to claim 5, is characterized in that, the injection ion of described disc-shaped N-type negative electrode is arsenic, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 50keV ~ 100keV; Described epitaxial loayer is that non-impurity-doped or N-type are low-doped, and doping content is 10
14cm
-3~ 10
16cm
-3; The injection ion of described circular N-type outer base area negative electrode is phosphorus, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 50keV ~ 100keV; The injection ion of disc-shaped p type anode is boron, and implantation dosage is 10
15cm
-2~ 10
16cm
-2, Implantation Energy is 5keV ~ 50keV.
8. the manufacture method of PIN diode array structure according to claim 6, is characterized in that, the ion implantation dosage of described circular P type isolated area is 10
14cm
-2~ 5x10
15cm
-2, Implantation Energy is 50keV ~ 200keV.
9. the manufacture method of PIN diode array structure according to claim 5, it is characterized in that, described N-type negative electrode is octagon disc-shaped, and described N-type outer base area negative electrode is that octagon is circular, described isolated area is that octagon is circular, and described p type anode is octagon disc-shaped.
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|---|---|---|---|
| CN201110316107.3A CN103066072B (en) | 2011-10-18 | 2011-10-18 | Positive-intrinsic-negative (PIN) diode array structure and manufacturing method thereof |
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| US7242071B1 (en) * | 2006-07-06 | 2007-07-10 | International Business Machine Corporation | Semiconductor structure |
| CN101140955A (en) * | 2006-09-06 | 2008-03-12 | 中国科学院微电子研究所 | Gallium arsenide PIN diode and preparation method thereof |
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| US6794734B2 (en) * | 2002-05-03 | 2004-09-21 | Mia-Com | Heterojunction P-I-N diode and method of making the same |
| US7821097B2 (en) * | 2006-06-05 | 2010-10-26 | International Business Machines Corporation | Lateral passive device having dual annular electrodes |
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| US7242071B1 (en) * | 2006-07-06 | 2007-07-10 | International Business Machine Corporation | Semiconductor structure |
| CN101140955A (en) * | 2006-09-06 | 2008-03-12 | 中国科学院微电子研究所 | Gallium arsenide PIN diode and preparation method thereof |
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