CN103065668A - Memory and reading method thereof - Google Patents
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- CN103065668A CN103065668A CN2012105679950A CN201210567995A CN103065668A CN 103065668 A CN103065668 A CN 103065668A CN 2012105679950 A CN2012105679950 A CN 2012105679950A CN 201210567995 A CN201210567995 A CN 201210567995A CN 103065668 A CN103065668 A CN 103065668A
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Abstract
Disclosed are a memory and a reading method of the memory. The memory comprises a memory cell area, a plurality of word lines and a plurality of bit lines and a read-out unit. The memory cell area is divided into a main memory area and a reference value memory area which comprise a plurality of memory bits. The plurality of word lines and the plurality of bit lines are crossed with each other. A memory bit is connected at each crossed position. The plurality of word lines are divided into main memory word lines and reference value word lines, wherein the main memory word lines are used for memory of external write signals into the memory bits of the main memory area, and the reference value word lines are used for memory of reference signals into the reference value memory area. The read-out unit is used for measurement of memory values of the memory bits of the main memory area, measurement of the mean value of memory values of the memory bits of the reference value memory area corresponding to the memory bits of the main memory area, comparison of the memory values and the mean value, and read-out of the memory values of the memory bits of the main memory area. Therefore, the main memory area and the reference value memory area change with the same tendency along with a process and temperature, characters of the main memory area and the reference value memory area can be kept uniform, and meanwhile the requirement for the process and the complexity of circuit design can be greatly reduced.
Description
Technical field
The invention belongs to semiconductor applications, relate in particular to a kind of in-line memory and read method thereof.
Background technology
Storage cell minimum in the semiconductor memory is by a bistable state semiconductor circuit or the bank bit that MOS transistor consists of, and can store a binary code in the bank bit.Form a memory cell region by several bank bits, and then form a storer by many memory cell region and other engagement unit.Described engagement unit comprises bit line and word line, and the address decoder of bit line and word line.Choose certain bank bit to carry out read-write operation by address decoder control word line and bit line, to read or to deposit in data.Wherein, the word line provides write signal, and bit line provides selected signal.
Take common flash memory (FLASH) storer as example, comprise the grid that is formed by several rows word line and some row bit lines in flash memory (FLASH) storer, wherein all there is the bank bit that a flash memory storage transistor consists of in the intersection of every word line and bit line.Concrete, each flash memory storage transistor be in the grid with the MOS transistor of floating boom, the threshold voltage of this MOS transistor can be by applying electric field at its grid and repeatedly being changed.Corresponding to the difference of the quantity of electric charge that exists in the floating boom, the transistorized threshold voltage of flash memory storage is different.When the electronics in the floating boom was assembled, the transistorized threshold voltage of flash memory storage will raise, and thought that traditionally the value of flash memory storage transistor storage this moment is " 1 ".After electronics was released in the floating boom, the transistorized threshold voltage of flash memory storage can reduce, and the value that this moment, memory cell region was considered to store is " 0 ".The situation that more flash memories are relevant can the referenced patent publication number be the Chinese patent of CN101771074A.
For the data reading with the storage in the bank bit of flash memories comes, can judge by the size of curtage by detecting in the transistorized floating boom of flash memory storage.Take electric current as example, such as: if the peak value of the electric current that passes through in the floating boom floats about 15 μ A ~ 20 μ A, valley floats about 0 μ A ~ 5 μ A.Can set 10 μ A is reference value, then when electric current during less than 10 μ A, judges that the value that writes in the bank bit is " 0 ", when electric current during greater than 10 μ A, judges that the value that writes in the bank bit is for writing " 1 ".
In order to support the judgement of this mode, except the primary memory area as real storage external data function, also can comprise sense amplifier and reference value zone in the flash memories.Primary memory area connective word line is written into external signal, and the reference value zone provides fixed reference signal (it typically is curtage).The quantity of electric charge that passes through in the bank bit of sense amplifier sensing primary memory area, and convert it into the output signal of curtage, curtage with the output of reference value zone compares again, if the signal of primary memory area is greater than reference signal, then the value of the bank bit storage of the primary memory area of being compared is read to be " 1 ", otherwise then the value of storing is read be " 0 ".In above-mentioned read method, if the reference value zone directly provides fixing curtage as reference current or reference voltage, the curtage that then needs all bank bits to produce must (comprise temperature, technique change and voltage) in all cases all on the fixing curtage or under.This is very harsh to the technological requirement of making storer.Especially when memory capacity surpasses 1 megabit, because the high-capacity flash memory element characteristics changes greatly the benchmark (reference current or reference voltage) that needs an energy and memory cell region to change simultaneously.Reference current or reference voltage when having following several way that the storing value in reading cells zone is provided in the prior art:
A kind of way is to adopt a certain proportion of NMOS or PMOS to come the attribute of analog storage position, and the curtage that is produced by described NMOS or PMOS compares judgement as reference value and bank bit.But because the bank bit processing technology is different from common NMOS or PMOS, such simulation has significant limitation.
Another kind of way is to provide a part of bank bit to come generation current and voltage as reference current or reference voltage as the reference value storage area in storer.In the prior art, the framework that mainly contains two kinds of storeies is applicable to this mode:
A kind of framework of storer is that reference value storage area and primary memory area are set in storer, and both have the bank bit of same structure, but is the storage area that separates separately.In this mode, because reference value storage area and primary memory area separate, in technology controlling and process, be difficult to guarantee that the structure in two zones is identical, just be difficult to also guarantee in by electric current that both are consistent to the unsteady factor of electric current.In other words, the size that is difficult to guarantee reference value is constant with respect to reset current.
The framework of another kind of storer is in the primary memory area, chooses the bank bit of the bit line by the fixed position (Bit Line) control on each root word line as the reference value storage area.In this mode, with respect to upper a kind of mode, can guarantee that the structure in two zones is identical.And, in the bank bit that each root word line links to each other, the bank bit that puts the reference value storage area under can both be arranged.When each write operation can be guaranteed like this, relatively constant reference value is arranged as the criterion of write signal.But in this mode, because each write operation all relates to the reference value storage area, may cause the change of reference value, thereby affect the performance of chip, such as aspects such as reading speed, reliabilities.
A kind of solution of read memory need to be provided, the relatively constant reference value criterion as write signal can be provided, better improve simultaneously efficient and the stability that storer reads.
Summary of the invention
The problem that the present invention solves is in the existing storer, can not take into account the reference value that provides constant as the criterion of write signal and have the problem of higher reading efficiency and stability.
For addressing the above problem, the invention provides a kind of storer, comprising:
Memory cell region is divided into primary memory area and reference value storage area, and primary memory area and reference value storage area include some bank bits;
Some word line and the bit lines that cross one another, described every word line be connected the infall of bit lines and connect a bank bit, described word line is divided into primary storage word line and reference value word line, described primary storage word line deposits external write enable signal the bank bit of primary memory area in, and described reference value word line deposits reference signal in the bank bit of reference value storage area;
Sensing element, described sensing element is measured the mean value of storing value of the bank bit of the storing value of bank bit of described primary memory area and the reference value storage area corresponding with the bank bit of measured described primary memory area, and compare and measure the size of mean value of storing value of the bank bit of the storing value of bank bit of the described primary memory area that obtains and described reference value storage area, thereby read the storing value of the bank bit of primary memory area.
Optionally, described storer is flash memories, and each bank bit is made of flash memory transistor.
Optionally, comprising:
Described flash memory transistor has floating boom, and described storing value is the quantity of electric charge that passes through in the floating boom;
Described sensing element comprises sense amplifier and converting unit, and described sense amplifier is measured the quantity of electric charge that passes through in the described floating boom, and described converting unit is converted into voltage signal or current signal with the described quantity of electric charge.
Optionally, described reference value word line is 2 ~ 8.
Optionally, described reference value word line is the most at least two continuous word lines of close sensing element.
Optionally, described storer also comprises the control circuit unit.
Technical scheme of the present invention also provides a kind of read method of aforesaid storer, comprising:
Described sensing element judges that the storing value of bank bit of described primary memory area greater than the storing value of the bank bit of reference value storage area, judges that then the value of the bank bit of described primary memory area is " 1 ";
Described sensing element judges that the storing value of bank bit of described primary memory area less than the storing value of the bank bit of reference value storage area, judges that then the value of the bank bit of described primary memory area is " 0 ".
Optionally, described reference value word line is the even number bar;
When judging the bank bit of the described primary storage word of even number bar line connection, the reference value that the bank bit that uses the described reference value word of even number bar line to connect is exported;
When judging the described primary storage word of odd number bar line connected bank bit, use the mean value of reference value of bank bit output of the connection of odd number bar reference value word line.
Optionally, described reference value word line is a bar, and described a is more than or equal to 2, corresponding, described primary storage word line is divided into a continuous unduplicated part, the primary storage word line of every corresponding part of reference value word line;
When judging the value of the bank bit that certain bar primary storage word line connects, the mean value of the reference value that the bank bit that uses its corresponding reference value word line to connect is exported.
Compared with prior art, the present invention has the following advantages:
The invention provides a kind of structure of storer and the read method of storer, comprise the primary memory area in the described storer and for generation of the reference value storage area of reading circuit reference point, wherein the reference value storage area adopts and primary memory area together reference sector independently, the variation of same trend is done with flow-route and temperature in described like this reference value storage area and primary memory area, and characteristic can be consistent.And because described reference value storage area is independently, it can not rewritten in actual use repeatedly, therefore the circuit reference point that produces can not change in time, is based upon the work that memory reading method on this storage area dividing mode can guarantee the storer accurate stable.And described circuit reference point is that the mean value of getting a plurality of reference cells produces, and the size of circuit reference point can be in the centre of high-capacity flash memory element characteristics variation range all the time like this, can greatly reduce the requirement of technique and the complicacy of circuit design.
Description of drawings
Fig. 1 is the structural representation of a kind of storer of providing in the embodiments of the invention;
Fig. 2 is the structural representation of a kind of memory transistor of providing in the embodiments of the invention;
Fig. 3 is that sensing element in a kind of storer that provides in the embodiments of the invention is to the synoptic diagram of the processing procedure of storing value;
Fig. 4 is that provide in the embodiments of the invention a kind of converts storing value to circuit diagram that current signal compares;
Fig. 5 is that provide in the embodiments of the invention a kind of converts storing value to circuit diagram that voltage signal compares.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
The structure of a kind of storer provided by the invention as shown in Figure 1, it comprises: the bit line of memory cell region (indicate), memory cell region periphery (indicating) and word line, control circuit unit and sensing element.
Wherein memory cell region comprises primary memory area and reference value storage area, and described memory cell region is made of some bank bits (not shown).The periphery of described memory cell region has n bar word line and m bit lines, the word line be WL1, WL2, WL3 ..., WLn, bit line be BL1, BL2, BL3 ..., BLm.Word line and bit line cross one another, every word line be connected the infall of bit lines and connect a bank bit.Described word line is divided into primary storage word line and reference value word line, sets in the word line 2 to 8 as reference value word line, other be primary storage word line.Primary storage word line is connected the bank bit that the place connects and consists of the primary memory area with bit line, reference value word line is connected the bank bit formation reference value storage area that the place connects with bit line.Described primary storage word line deposits external write enable signal in primary memory area, and described reference value word line deposits reference signal in the reference value storage area.
Memory cell region comprises several quickflashings (Flash) memory transistor that is arrayed in the present embodiment.Concrete, described memory transistor as shown in Figure 2, it comprises drain electrode 2 and the source electrode 3 that is arranged in semiconductor base 100, and the stacked gate structure 4 that is positioned at semiconductor base 100 surfaces, from semiconductor base 100 surfaces, from bottom to up, described stacked gate structure 4 is followed successively by gate dielectric layer 40, floating boom 41, thin oxide layer 42 and control gate 43.Described drain electrode 2 connective word line WL, the control gate 43 in the described stacked gate structure 4 is connected to bit line BL, and described source electrode 3 is by a capacity earth, and described source electrode also can be to connect to drive.Described word line WL provides high pressure, and described bit line BL provides low pressure.When external signal is passed through word line WL data writing, the charge injection floating boom.Generally speaking, think in the floating boom not have iunjected charge or inject more electric charge and represent to write " 1 " iunjected charge or to inject less electric charge to represent " 0 ".Because the size that how much has determined store M OS threshold voltage of the electric charge in the floating boom, under fixing bias current or voltage, the quantity of electric charge of described floating boom is different, and meeting is so that described bank bit can show different voltage or electric current.For the storage data in the bank bit (" 0 " and " 1 ") are read out, general employing sense amplifier comes the curtage in the sensing bank bit, and judges that according to the relativeness of the curtage in the bank bit that senses and reference current or reference voltage what (" 0 " or " 1 ") is the storage data in the bank bit are.
Described sensing element is measured the mean value of storing value in the bank bit of the storing value of bank bit of described primary memory area and corresponding reference value storage area, and both sizes relatively.Wherein, the bank bit of described measured primary memory area and the bank bit of reference value storage area have corresponding relation, when reading the value of the bank bit that certain bar primary storage word line connects, read the mean value of the reference value of bank bit (the being generally a plurality of bank bits) output that its corresponding reference value word line connects.Such as: if described reference value word line is a bar, described a is more than or equal to 2, corresponding, described primary storage word line is divided into a continuous unduplicated part, the primary storage word line of every corresponding part of reference value word line; When judging the value of the bank bit that certain bar primary storage word line connects, the mean value of the reference value that the bank bit that uses its corresponding reference value word line to connect is exported.
Perhaps, described reference value word line is the even number bar; When judging the bank bit of the described primary storage word of even number bar line connection, the mean value of the reference value that all bank bits that use the described reference value word of even number bar line to connect are exported; When judging the described primary storage word of odd number bar line connected bank bit, use the mean value of reference value of all bank bits output of the connection of odd number bar reference value word line.
In the present embodiment, described sensing element comprises sense amplifier and converting unit, described sensing element to the processing procedure of storing value as shown in Figure 3, it comprises that the quantity of electric charge obtains, quantity of electric charge conversion, conversion value comparison and the value of reading output, detailed process is: the mean value of the storing value of the storing value of the bank bit that acquires the primary memory area by sense amplifier in the described quantity of electric charge stage of obtaining and the bank bit of corresponding reference value storage area, by converting unit two values are converted to electric current or voltage again, then compare the electric current of two zone correspondences or the size of voltage, obtain the value of reading and the output value of reading according to comparative result.In the present embodiment, described storing value is the quantity of electric charge in the floating boom of flash memory transistor.After getting access to the quantity of electric charge, respectively the quantity of electric charge in the floating boom of the flash memory transistor of primary memory area and reference value storage area is changed into electric current or voltage signal, then with both relatively, according to fiducial value output value of reading (" 0 " or " 1 ").
Wherein, a kind of realization converts storing value to compare behind the current signal circuit as shown in Figure 4, and it comprises: PMOS transistor M11, PMOS transistor M12, nmos pass transistor M13, current comparator 100, and current source Iref.The quantity of electric charge in the floating boom of the quantity of electric charge in the floating boom of the flash memory transistor CL1 of primary memory area and the flash memory transistor of reference value storage area shows as respectively the electric current I cell of the flash memory transistor CL1 that flows through and the reference current Iref of current source.Wherein, the electric current of reference value storage area is the mean value of the electric current of the bank bit in the reference value storage area that reads, and can regard reference current for changeless as, so show as current source Iref.PMOS transistor M11, PMOS transistor M12 consist of a current mirror, and its input and output are than being 1:1, and namely electric current I cell equals I2.Wherein, acting as of current mirror comes the current mirror of flash memory transistor CL1 to compare with reference current.The grid of nmos pass transistor M13 is used for input offset voltage, and its effect is equivalent to be fixed voltage with generation current in the drain electrode of flash memory transistor CL1.100 couples of electric current I cell(of current comparator equal I2) and the reference current Iref of current source compare.The electric current I cell(of flash memory transistor CL1 equals I2 if flow through) greater than the reference current Iref of current source, judge that then the data value that flash memory transistor CL1 preserves is 1, output voltage VO UT1 is output as 1; The electric current I cell(of flash memory transistor CL1 equals I2 if flow through) less than the reference current Iref of current source, judge that then the data value of the preservation of flash memory transistor CL1 is 0, output voltage VO UT1 is output as 0.
A kind of circuit of realizing converting storing value to voltage signal comprises: resistance R 11, resistance R 12, voltage comparator 200, and current source Iref as shown in Figure 5.Like the same Noodles, the quantity of electric charge in the floating boom of the quantity of electric charge in the floating boom of the flash memory transistor CL2 of primary memory area and the flash memory transistor of reference value storage area shows as respectively the electric current I cell of the flash memory transistor CL2 that flows through and the reference current Iref of current source.The resistance of described resistance R 11 and resistance R 12 equates.The reference current Iref of 200 couples of electric current I cell of voltage comparator and current source compares.Specifically, the electric current I cell of flash memory transistor CL2 is greater than the reference current Iref of current source if flow through, the negative input voltage of voltage comparator 200 judges then that less than electrode input end voltage the data value that flash memory transistor CL2 preserves is 1, and output voltage VO UT2 is output as 1; The electric current I cell of flash memory transistor CL2 is less than the reference current Iref of current source if flow through, the negative input voltage of voltage comparator is greater than electrode input end voltage, the data value of then judging the preservation of flash memory transistor CL2 is 0, and output voltage VO UT2 is output as 1.
Described control circuit unit provides the power supply signal that needs for the storer various piece.Continue with reference to shown in Figure 2, described control circuit unit provides power supply signal to reference value word line, primary storage word line, bit line and sensing element respectively.Concrete, it is realized by the functional circuit module in the storer, can be that in the memory inside structure one or multi-blocked structure are realized jointly.
The present invention also provides a kind of read method to above-mentioned storer, and it comprises:
Memory cell region is divided into primary memory area and reference value storage area, and described division is to be that primary storage word line and reference value word line carry out by the word line of dividing storer.Described primary memory area is deposited in external write enable signal by primary storage word line, and described reference value storage area is deposited in reference signal by reference value word line.Setting described reference value word line is a bar, and described a is the natural number more than or equal to 2, corresponding, described primary storage word line is divided into a continuous unduplicated zone, every corresponding primary storage word line part of reference value word line; Select a bar word line of the most close described sense amplifier as reference value word line, like this Time Created fast, can improve the chip read rate.
When judging the value of the bank bit that certain regional primary storage word line connects, the mean value of the reference value that the bank bit that uses its corresponding reference value word line to connect is exported is as the circuit reference point.
Concrete, in the present embodiment, described primary storage word line is divided into the zone of odd number bar and the zone of even number bar according to putting in order.Setting described reference value word line is the even number bar, is 2 in the present embodiment;
When judging the described primary storage word of odd number bar line connected bank bit, the mean value of the reference value of the bank bit output that the 1st row of use reference value word line connects;
When judging the bank bit that the described primary storage word of even number bar line connects, use the mean value of the reference value of the bank bit output that the 2nd row of described reference value word line connects.
The described bank bit that connects according to the different reference value word line of different primary storage word line options comes the setting of comparison to be undertaken by control circuit.
Described sensing element judges that the storing value of bank bit of described primary memory area greater than the mean value of the storing value of the bank bit of corresponding reference value storage area, judges that then the value of the bank bit of described primary memory area is " 1 ";
Described sensing element judges that the storing value of bank bit of described primary memory area less than the mean value of the storing value of the bank bit of corresponding reference value storage area, judges that then the value of the bank bit of described primary memory area is " 0 ".
The high-capacity flash memory element characteristics changes greatly, the benchmark that needs the memory transistor of an energy and primary memory area to change simultaneously.The present invention provides a kind of structure of storer and the read method of storer in the above-described embodiments, comprise the primary memory area in the described storer and for generation of the reference value storage area of reading circuit reference point, wherein the reference value storage area adopts and primary memory area together reference sector independently, the memory transistor of described like this reference value storage area and primary memory area is done the variation of same trend with flow-route and temperature, and characteristic can be consistent.Because described reference value storage area is again independently, it can not rewritten in actual use repeatedly, therefore the circuit reference point that produces can not change in time, is based upon the work that memory reading method on this storage area dividing mode can guarantee the storer accurate stable.And described circuit reference point is that the mean value of getting a plurality of reference cells produces, and the size of circuit reference point can be in the centre of high-capacity flash memory element characteristics variation range all the time like this, can greatly reduce the requirement of technique and the complicacy of circuit design.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. a storer is characterized in that, comprising:
Memory cell region is divided into primary memory area and reference value storage area, and primary memory area and reference value storage area include some bank bits;
Some word line and the bit lines that cross one another, every word line be connected the infall of bit lines and connect a bank bit, described word line is divided into primary storage word line and reference value word line, described primary storage word line deposits external write enable signal the bank bit of primary memory area in, and described reference value word line deposits reference signal in the bank bit of reference value storage area;
Sensing element, described sensing element is measured the mean value of storing value of the bank bit of the storing value of bank bit of described primary memory area and the reference value storage area corresponding with the bank bit of measured described primary memory area, and compare and measure the storing value of bank bit of the described primary memory area that obtains and the size of described mean value, thereby the value of reading the bank bit of primary memory area.
2. storer as claimed in claim 1 is characterized in that, described storer is flash memories, and each bank bit is made of flash memory transistor.
3. storer as claimed in claim 2 is characterized in that, comprising:
Described flash memory transistor has floating boom, and described storing value is the quantity of electric charge that passes through in the floating boom;
Described sensing element comprises sense amplifier and converting unit, and described sense amplifier is measured the quantity of electric charge that passes through in the described floating boom, and described converting unit is converted into voltage signal or current signal with the described quantity of electric charge.
4. storer as claimed in claim 1 is characterized in that, described reference value word line is 2 ~ 8.
5. storer as claimed in claim 1 is characterized in that, described reference value word line is the most at least two continuous word lines of close sensing element.
6. storer as claimed in claim 1 is characterized in that, described storer also comprises the control circuit unit.
7. the read method of a storer, described storer is such as each described storer in the claim 1 to 6, it is characterized in that described read method comprises:
If described sensing element is judged the storing value of bank bit of described primary memory area and greater than described mean value, is judged that then the value of the bank bit of described primary memory area is " 1 ";
If described sensing element is judged the storing value of bank bit of described primary memory area and less than described mean value, is judged that then the value of the bank bit of described primary memory area is " 0 ".
8. read method as claimed in claim 7 is characterized in that, described reference value word line is the even number bar;
When judging the bank bit of the described primary storage word of even number bar line connection, the mean value of the reference value that all bank bits that use the described reference value word of even number bar line to connect are exported;
When judging the described primary storage word of odd number bar line connected bank bit, use the mean value of reference value of all bank bits output of the connection of odd number bar reference value word line.
9. read method as claimed in claim 7 is characterized in that, described reference value word line is a bar, described a is more than or equal to 2, corresponding, described primary storage word line is divided into a continuous unduplicated part, the primary storage word line of every corresponding part of reference value word line;
When judging the value of the bank bit that certain bar primary storage word line connects, the mean value of the reference value that all bank bits that use its corresponding reference value word line to connect are exported.
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| CN111489777A (en) * | 2020-04-15 | 2020-08-04 | 上海新微技术研发中心有限公司 | Magnetic memory structure, array, read-write control method and preparation method |
| WO2022110636A1 (en) * | 2020-11-30 | 2022-06-02 | 无锡华润上华科技有限公司 | Semiconductor memory |
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| CN102738244A (en) * | 2011-04-08 | 2012-10-17 | 北京大学 | SONOS flash memory, preparation method thereof, and operation method thereof |
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| CN111489777A (en) * | 2020-04-15 | 2020-08-04 | 上海新微技术研发中心有限公司 | Magnetic memory structure, array, read-write control method and preparation method |
| CN111489777B (en) * | 2020-04-15 | 2023-11-10 | 上海新微技术研发中心有限公司 | Magnetic memory structure, array, read-write control method and preparation method |
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