CN103064316A - Synchronous denoising multichannel ultrasonic signal acquisition system - Google Patents
Synchronous denoising multichannel ultrasonic signal acquisition system Download PDFInfo
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- CN103064316A CN103064316A CN2012105664902A CN201210566490A CN103064316A CN 103064316 A CN103064316 A CN 103064316A CN 2012105664902 A CN2012105664902 A CN 2012105664902A CN 201210566490 A CN201210566490 A CN 201210566490A CN 103064316 A CN103064316 A CN 103064316A
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Abstract
The invention relates to a synchronous denoising multichannel ultrasonic signal acquisition system. The synchronous denoising multichannel ultrasonic signal acquisition system comprises a channel acquisition module, a flat cable, a universal serial bus (USB) transmission module and an upper computer. The channel acquisition module is used for receiving ultrasonic signals, analyzing and denoising, and then data transmission is carried out between the channel acquisition module and the upper computer. The flat cable is used for connecting the channel acquisition module and the USB transmission module. The USB transmission module is used for the USB communication between the upper computer and a complex programmable logic device (CPLD) of the channel acquisition module. The synchronous denoising multichannel ultrasonic signal acquisition system solves the problems that interference data is widely common in the existing ultrasonic signal acquisition system and the acquisition channel numbers are not easy to change. The synchronous denoising multichannel ultrasonic signal acquisition system has the advantages that the interference data is little and the hardware is convenient to dismantle. The synchronous denoising multichannel ultrasonic signal acquisition system is particularly suitable for being used on the occasions of multichannel ultrasonic signal synchronous acquisition.
Description
Technical field
The present invention relates to the ultrasonic signal acquisition system, specifically a kind of synchronous denoising multichannel ultrasonic signal acquisition system belongs to electronic circuit field.
Background technology
Along with improving constantly that product quality is required, effectively quality detection device and method more and more receive publicity, and ultrasound examination more and more is applied in the detection system as a kind of green, harmless, efficient method.At present the ultrasonic signal acquisition system is many processes not treated directly being transferred in the host computer of the data that collect, and each acquisition channel module and transport module are produced on the same circuit board.Have like this some shortcomings: (1) data are not treated directly to be sent in the host computer, can have some random interfering datas, the impact analysis result; (2) each acquisition channel module and transport module are produced on the same circuit board, make the fixing difficult change of port number of collection signal, cause system's versatility poor.
Summary of the invention
In order to overcome the deficiencies in the prior art, the invention provides a kind of synchronous denoising multichannel ultrasonic signal acquisition system, according to synchronizing signal data sectional is stored in the storer, then take out successively each segment data and carry out analyzing and processing, the reduce disturbance data cause the error of analysis result.
Technical scheme of the present invention is as follows:
Denoising multichannel ultrasonic signal acquisition system comprises passage acquisition module, winding displacement, USB transport module and host computer synchronously;
Described passage acquisition module comprises:
The signal condition module, amplitude and filtering interference signals for conditioning signal are transferred to AD converter with output signal;
AD converter, being used for analog signal conversion is digital signal, and samples according to the clock that CPLD provides;
Twoport FIFO buffer module is for the data of storage of collected;
CPLD is used for the data that reception synchronous triggering signal and AD converter are exported, and stores data into twoport FIFO buffer module; Comprise
Frequency division module be used for to receive the sample frequency coding of host computer, with the system clock frequency division, and the clock behind the frequency division is exported to AD converter, controls the sample frequency of AD converter with this;
The amplitude control module be used for to receive the gain control coding of host computer, and according to this coding outputing gain control signal in signal conditioning circuit, simultaneously gain parameter is outputed to the amplitude computing module;
The amplitude computing module carries out computing according to the gain parameter that receives to the output data of AD converter, and the data after the computing is outputed to the finite state machine module;
The finite state machine module, constantly the output data sectional of amplitude computing module is outputed to the FIFO buffer module according to synchronous triggering signal, when passage was carried out the transmission of data order, finite state machine outputed to data processing module with the data sectional in the FIFO buffer module;
Data processing module after the logic analysis denoising, is transferred to the usb data port after valid data are averaged;
Described winding displacement is used for interface channel acquisition module and USB transport module;
Described USB transport module is used for carrying out usb communication between host computer and the CPLD.
Aforesaid signal condition module turns single-end circuit, controllable gain amplifying circuit, filtering circuit and single-ended transfer difference the electric circuit constitute by difference.
Aforesaid controllable gain amplifying circuit is comprised of MUX, resistance network and operational amplifier.
Aforesaid AD converter adopts the high-speed AD chip with difference input form.
Aforesaid twoport FIFO buffer module is used has two groups of independently storeies of data and address interface.
Aforesaid USB transport module adopts the USB dedicated processes chip with 51 kernels of enhancement mode, and described USB dedicated processes chip configuration becomes the mode of operation of Slave FIFO.
Aforesaid USB transport module comprises
Clock circuit is used for providing work clock to USB dedicated processes chip;
Reset circuit is used for USB dedicated processes chip power being resetted and carrying out hand-reset by button;
The firmware loads circuit is used for the storing firmware program;
The CPLD control circuit, the FPDP of USB dedicated processes chip directly links to each other with CPLD with control port, is used for carrying out data transmission with CPLD;
Usb circuit, the transmit port of USB dedicated processes chip links to each other with USB interface, is used for carrying out data transmission with host computer.
Aforesaid passage acquisition module is produced on the separate circuit board, and is connected with the USB transport module by winding displacement.
The interface of aforesaid winding displacement is detachable, can change as required the number of acquisition channel module.
In view of technique scheme, the present invention has following advantages:
(1) CPLD stores data sectional among the twoport FIFO into according to synchronizing signal, and is transferred to host computer through after the denoising, reduces random data to the impact of analysis result.
(2) each passage acquisition module is produced on the separate circuit board and by the winding displacement that customizes and is connected with the USB transport module, makes according to demand selector channel number of system, strengthens versatility.
(3) sampling twoport FIFO buffer module is carried out data storage, guarantees synchronism and the real-time of each paths sampling.
(4) adopt the mode of usb communication to carry out data transfer, compare the mode of serial ports transmission, improved the transfer rate of system.
(5) data communication device of each acquisition channel is crossed the CPLD port is realized data in the switching of high resistant and conducting state wheel flow transmission, so that syndeton is simple between the module, reliability is high.
Description of drawings
Fig. 1 is overall construction drawing of the present invention;
Fig. 2 is the schematic diagram that concerns of synchronizing signal of the present invention and ultrasonic signal;
Fig. 3 is the circuit theory diagrams of signal condition module of the present invention;
Fig. 4 is the circuit structure diagram of AD chip of the present invention;
Fig. 5 is the cut-away view of twoport FIFO storer of the present invention;
Fig. 6 is the cut-away view of USB process chip of the present invention;
Fig. 7 is the cut-away view of USB transport module of the present invention;
Fig. 8 is the high-level schematic functional block diagram of CPLD internal processes of the present invention;
Fig. 9 is the schematic flow sheet of firmware program of the present invention;
Figure 10 is hardware connection diagram of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is explained in detail:
As shown in Figure 1, based on synchronous denoising multichannel ultrasonic signal acquisition system of the present invention, comprising: passage acquisition module, winding displacement, USB transport module and host computer.The passage acquisition module has one at least, comprising: the signal condition module, and amplitude and filtering interference signals for regulating ultrasonic signal are transferred to AD converter with output signal; AD converter, being used for analog signal conversion is digital signal, and samples according to the clock that CPLD provides; Twoport FIFO buffer module is used for the data that storage of collected arrives; CPLD is used for the data that reception synchronous triggering signal and AD converter are exported, and stores data sectional into twoport FIFO buffer module.Winding displacement is used for interface channel acquisition module and USB transport module; The USB transport module is used for carrying out usb communication between host computer and the CPLD.
As shown in Figure 8, the functional module of CPLD comprises: frequency division module, be used for to receive the sample frequency coding of host computer, and with the system clock frequency division, and the clock behind the frequency division exported to AD converter, control the sample frequency of AD converter with this;
The amplitude control module be used for to receive the gain control coding of host computer, and according to this coding outputing gain control signal in signal conditioning circuit, simultaneously gain parameter is outputed to the amplitude computing module;
The amplitude computing module carries out computing according to the gain parameter that receives to the output data of AD converter, and the data after the computing is outputed to the finite state machine module;
The finite state machine module, constantly the output data sectional of amplitude computing module is outputed to the FIFO buffer module according to synchronous triggering signal, when passage was carried out the transmission of data order, finite state machine outputed to data processing module with the data sectional in the FIFO buffer module;
Data processing module is removed interfering data by logical process, is transferred to the usb data port after valid data are averaged.
As shown in Figure 2, synchronizing signal of the present invention is the negative edge signal of continuous trigger, CPLD stores in the twoport FIFO buffer module according to the data sectional that this signal will collect ultrasonic signal, then successively each segment data is read, with averaging after each segment data alignment, to reduce neighbourhood noise to systematic analysis result's impact.
As shown in Figure 3, signal condition module of the present invention turns single-end circuit by difference, the controllable gain amplifying circuit, filtering circuit and single-ended transfer difference the electric circuit constitute, difference turns single-end circuit the ultrasonic signal of difference form input is converted to the single-ended signal that gain is easy to control, operational amplifier U1, MUX and resistor network form the adjustable reverse operational amplification circuit of gain, CPLD controls MUX and then changes the resistance of feedback resistance in the reverse operational amplification circuit, thereby the gain of control circuit, signal after the amplification is behind the filtering circuit filtering clutter, by operational amplifier U2, resistance R 3, in the same way voltage follower and operational amplifier U3 that resistance R 4 forms, resistance R 5, the reverse voltage follower that resistance R 6 forms is converted to differential signal with single-ended signal, because the amplifier of gain control adopts sign-changing amplifier, final differential signal also will oppositely access AD converter.
As shown in Figure 4, AD converter of the present invention adopts the high-speed AD chip with difference input form, the signal of signal condition module output is directly inputted to VINA and the VINB end carries out analog to digital conversion, capacitor C 1, capacitor C 2, capacitor C 3 and capacitor C 5 consist of decoupling circuit, the stability of intensifier circuit, resistance R 7, resistance R 8, resistance R 9, capacitor C 4 and TLV431 voltage reference chip U4 form mu balanced circuit, for AD converter provides reference voltage, the ratio of adjusting resistance R7 and resistance R 8, can between 1.24V-6V, change the value of reference voltage, the clock port CLK of AD converter directly links to each other with the port of CPLD with FPDP BIT1-BITn, AD converter is sampled according to the clock that CPLD provides, and stores the digital signal that is collected into twoport FIFO buffer module by CPLD.
As shown in Figure 5, twoport FIFO buffer module of the present invention is used has two groups of independently storeies of data and address interface, and two groups of ports shared about storer can be, and the left and right sides processing unit of two groups of ports is shared a storer.The CPLD of each acquisition module with the output data of AD converter from wherein constantly being stored in the storer one group of port, and according to sequential with data from storer another the group port be transferred in turn the usb communication module, because two groups of ports can carry out read-write operation to storer simultaneously, the sequential of strict control system, just can realize the synchronously continuous sampling of each road signal, and each road transfers data to host computer in turn by a USB transport module.
As shown in Figure 6, USB processing module of the present invention adopts the USB dedicated processes chip with 51 kernels of enhancement mode, 8051 single-chip microcomputers of its instruction set and standard are compatible, the serial interface engine SIE of chip internal is responsible for finishing the work for the treatment of of most of usb protocol, thereby has alleviated the workload of USB protocol processes, chip internal adopts Slave FIFO mode of operation, the transmission of assurance data high-speed, kernel is not participated in control and the transmission work of FIFO directly, has improved the speed of bus transfer.
As shown in Figure 7, the USB transport module is by clock circuit, reset circuit, the firmware loads circuit, CPLD control circuit and usb circuit form, capacitor C 6, capacitor C 7 and crystal oscillator Y1 form clock circuit, be used for providing work clock to USB dedicated processes chip, resistance R 13, resistance R 14, capacitor C 8 and button KEY1 form reset circuit, be used for USB dedicated processes chip power is resetted, and can carry out hand-reset by button KEY1, eeprom chip U5 and resistance R 10, resistance R 11, resistance R 12 forms the firmware loads circuit, be used for the storing firmware program, the FPDP of USB dedicated processes chip directly links to each other with CPLD with control port, be used for carrying out data transmission with CPLD, the transmit port of USB dedicated processes chip links to each other with USB interface, is used for carrying out data transmission with host computer.
As shown in Figure 9, the groundwork flow process of firmware program of the present invention is as follows:
(1) carry out the initialization of program, configuration USB dedicated processes chip is the mode of operation of Slave FIFO, and initialization is carried out in register and the interruption of USB transmission, then carries out for the 2nd step;
(2) need to judge whether re-enumeration, if need to carry out the re-enumeration operation, again be USB process chip configuration trading company of factory and production number according to describing, then carried out for the 3rd step, otherwise directly carried out for the 3rd step;
(3) then connection device carried out for the 4th step;
(4) judge whether the standard request of USB, if having, then the operative norm request carried out for the 5th step, otherwise directly carried out for the 5th step;
(5) judged whether the host computer command request, if having, command code has been decoded, and carried out the command request of host computer according to decoded result, then entered for the 6th step, otherwise directly carried out for the 6th step;
(6) judge whether to finish communication, if then finish, otherwise returned for the 4th step.
Be hardware connection diagram of the present invention as shown in figure 10, PC and synchronous triggering signal are connected on the circuit board of USB transport module, wherein synchronous signal line and data line, control line and power lead interconnect by the circuit board of winding displacement and each passage acquisition module, the passage acquisition module is produced on the separate circuit board, winding displacement is the dismountable winding displacement of interface of customization, can according to actual needs, change easily the number of acquisition channel module.
The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.
Claims (9)
1. synchronous denoising multichannel ultrasonic signal acquisition system is characterized in that: comprise
Passage acquisition module, winding displacement, USB transport module and host computer;
Described passage acquisition module comprises:
The signal condition module, amplitude and filtering interference signals for conditioning signal are transferred to AD converter with output signal;
AD converter, being used for analog signal conversion is digital signal, and samples according to the clock that CPLD provides;
Twoport FIFO buffer module is for the data of storage of collected;
CPLD is used for the data that reception synchronous triggering signal and AD converter are exported, and stores data into twoport FIFO buffer module; Functional module comprises
Frequency division module be used for to receive the sample frequency coding of host computer, with the system clock frequency division, and the clock behind the frequency division is exported to AD converter, controls the sample frequency of AD converter with this;
The amplitude control module is used for receiving the gain control coding of host computer, and according to encoding outputing gain control signal in signal conditioning circuit, simultaneously gain parameter is outputed to the amplitude computing module;
The amplitude computing module carries out computing according to the gain parameter that receives to the output data of AD converter, and the data after the computing is outputed to the finite state machine module;
The finite state machine module, constantly the output data sectional of amplitude computing module is outputed to the FIFO buffer module according to synchronous triggering signal, when passage was carried out the transmission of data order, finite state machine outputed to data processing module with the data sectional in the FIFO buffer module;
Data processing module after the logic analysis denoising, is transferred to the usb data port after valid data are averaged;
Described winding displacement is used for interface channel acquisition module and USB transport module;
Described USB transport module is used for carrying out usb communication between host computer and the CPLD.
2. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 1, it is characterized in that: described signal condition module turns single-end circuit, controllable gain amplifying circuit, filtering circuit and single-ended transfer difference the electric circuit constitute by difference.
3. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 2, it is characterized in that: described controllable gain amplifying circuit is comprised of MUX, resistance network and operational amplifier.
4. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 1 is characterized in that: the high-speed AD chip that described AD converter employing has the difference input form.
5. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 1 is characterized in that: described twoport FIFO buffer module is used has two groups of independently storeies of data and address interface.
6. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 1, it is characterized in that: described USB transport module adopts the USB dedicated processes chip with 51 kernels of enhancement mode, and described USB dedicated processes chip configuration becomes the mode of operation of Slave FIFO.
7. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 6, it is characterized in that: described USB transport module comprises
Clock circuit is used for providing work clock to USB dedicated processes chip;
Reset circuit is used for USB dedicated processes chip power being resetted and carrying out hand-reset by button;
The firmware loads circuit is used for the storing firmware program;
The CPLD control circuit, the FPDP of USB dedicated processes chip directly links to each other with CPLD with control port, is used for carrying out data transmission with CPLD;
Usb circuit, the transmit port of USB dedicated processes chip links to each other with USB interface, is used for carrying out data transmission with host computer.
8. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 1, it is characterized in that: described passage acquisition module is produced on the separate circuit board, and is connected with the USB transport module by winding displacement.
9. synchronous denoising multichannel ultrasonic signal acquisition system according to claim 1, it is characterized in that: the interface of described winding displacement is detachable, can change as required the number of acquisition channel module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108056777A (en) * | 2017-10-31 | 2018-05-22 | 北京心灵方舟科技发展有限公司 | Measure the device of oxygen-containing hemoglobin and deoxyhemoglobin and Brian Imaging equipment |
| CN114218139A (en) * | 2021-12-15 | 2022-03-22 | 北京航天控制仪器研究所 | Simulation turntable high-speed synchronous acquisition method based on real-time operating system and FPGA |
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Patent Citations (5)
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| CN101493438A (en) * | 2009-02-18 | 2009-07-29 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
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| CN114218139A (en) * | 2021-12-15 | 2022-03-22 | 北京航天控制仪器研究所 | Simulation turntable high-speed synchronous acquisition method based on real-time operating system and FPGA |
| CN114218139B (en) * | 2021-12-15 | 2024-05-31 | 北京航天控制仪器研究所 | Simulation turntable high-speed synchronous acquisition method based on real-time operating system and FPGA |
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