CN103052268B - The manufacture method of line construction - Google Patents
The manufacture method of line construction Download PDFInfo
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- CN103052268B CN103052268B CN201110305613.2A CN201110305613A CN103052268B CN 103052268 B CN103052268 B CN 103052268B CN 201110305613 A CN201110305613 A CN 201110305613A CN 103052268 B CN103052268 B CN 103052268B
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- layer
- area
- blind hole
- intaglio pattern
- manufacture method
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Abstract
The present invention discloses a kind of manufacture method of line construction.It comprises pressing one and has the dielectric layer of second surface on the first surface and the first patterned line layer of a circuit base plate.Form blind hole and an intaglio pattern that at least one second surface extends to the first patterned line layer.Form one and there is at least one patterning photoresist oxidant layer exposing the opening of blind hole and intaglio pattern on second surface.The region at patterning photoresist oxidant layer place is defined as first area, and the region beyond first area is defined as second area.Form an active layer in first and second region.Remove patterning photoresist oxidant layer and be positioned at the active layer of first area, to leave the active layer being positioned at second area.Form an electric conducting material on the active layer being positioned at second area.Remove partially conductive material and the partial activation layer being positioned at second area.
Description
Technical field
The present invention relates to a kind of manufacture method of line construction, and particularly relate to a kind of manufacture method with the line construction on fine rule road.
Background technology
In general, the line construction of wiring board is all formed respectively by photoetching and etching process or laser ablation mode usually.For the manufacture craft of the existing embedded type circuit structure utilizing laser ablation mode to be formed, it comprises the following steps.First, a dielectric layer is provided.Then, to surface irradiation one laser beam of dielectric layer, to form the blind hole that an intaglio pattern and is connected to line layer.Then, carry out a pre-treatment with by after laser the glue slag that remains or legacy remove (especially blind via bottom come out line layer surface).Then, comprehensive formation one palladium layers is on dielectric layer surface and in the intaglio pattern formed and blind hole.Afterwards, carry out a wireless plating technology (ElectrolessPlating), to be formed, a chemical layers of copper is comprehensive to be covered in the palladium layers of dielectric layer surface, and is positioned in the palladium layers of intaglio pattern and blind hole., then carry out one and have electric galvanoplastic (ElectricalPlating) to make layers of copper fill up intaglio pattern and blind hole then.Finally, then after removing the conductive copper layer on dielectric layer surface, so far, embedded type circuit structure roughly completes.
But, when forming conductive copper layer by electric plating of whole board, because the degree of depth of blind hole is different with the degree of depth of intaglio pattern, therefore for really to fill up blind hole and intaglio pattern, just must extend electroplating time.Thus, dielectric layer surface also relatively forms thicker conductive copper layer, and follow-uply must remove layers of copper on dielectric layer surface to form embedded type circuit structure.Therefore, need longer electroplating time to form the Material Cost of thicker conductive copper layer and time cost, the Material Cost of the conductive copper layer removed on dielectric layer surface and time cost, and for the aforementioned too much and unnecessary manufacturing conditions of process the cost of manufacture of the accessory substance that derive and discarded object and time cost be all that one is wasted.Moreover, extend the conductive copper layer that electroplating time increases, also the phenomenon that thickness distribution is uneven may be had, to be unfavorable for that the follow-up build-up circuit layer that carries out thereon is again when making, the low manufacture craft yield issues that more leisure opinion is manufactured with the design of folded hole or higher wiring density wiring board produces and the line construction of low reliability.In addition, form line construction according to photoetching and etching process, then can face a large amount of use chemical liquid and cause environmental pollution and increase into the problems such as product cost.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of line construction, manufacture craft yield can be promoted and reduce cost of manufacture.
The present invention proposes a kind of manufacture method of line construction, and it comprises the following steps.Pressing one dielectric layer is on a circuit base plate, and wherein circuit base plate has a first surface and one first patterned line layer, and dielectric layer has a second surface, and dielectric layer covers first surface and first patterned line layer of circuit base plate.Form blind hole and an intaglio pattern that at least one second surface from dielectric layer extends to the first patterned line layer.Form a patterning photoresist oxidant layer on the second surface of dielectric layer, wherein patterning photoresist oxidant layer has at least one opening exposing blind hole and intaglio pattern, and the edge of at least one opening of patterning photoresist oxidant layer is away from more than surrounding's certain distance of blind hole or intaglio pattern.The region at patterning photoresist oxidant layer place is defined as a first area, and the region beyond first area is defined as a second area.Form an active layer in first area and second area, active layer is covered in patterning photoresist oxidant layer and is positioned in the second surface of dielectric layer of second area, intaglio pattern and blind hole.Remove patterning photoresist oxidant layer and be positioned at the active layer of first area, to leave the active layer being positioned at second area.Form an electric conducting material on the active layer being positioned at second area, wherein electric conducting material fills up intaglio pattern and blind hole, and covers the active layer being positioned at second area.Remove partially conductive material and the partial activation layer being positioned at second area, trim to make the second surface of electric conducting material and dielectric layer.
Based on above-mentioned, because the present invention is after formation intaglio pattern and blind hole, first cover the portion second surface of dielectric layer by patterning photoresist oxidant layer, then sequentially forming active layer and electric conducting material in intaglio pattern and blind hole, wherein electric conducting material flushes with the second surface of dielectric layer.Therefore, be compared to the making of existing line structure, the waste of the cost of manufacture that the making of line construction of the present invention can effectively avoid existing electric plating of whole board conductive copper layer to produce and time cost and conductive copper layer have thickness distribution problem that is uneven and surface irregularity to produce, and the situation also can avoided using etching solution in a large number and cause environmental pollution.Thus, the manufacture method of line construction of the present invention can have preferably reliability and manufacture craft yield and can reduce production cost.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 G is the schematic top plan view of the manufacture method of a kind of line construction of one embodiment of the invention;
Fig. 2 A to Fig. 2 G illustrates the generalized section of the line I-I along Figure 1A to Fig. 1 G respectively.
Main element symbol description
100: line construction
110: circuit base plate
112: core dielectric layer
113: first surface
114: the first patterned line layer
115: the three surfaces
116: the second patterned line layer
120: dielectric layer
122: intaglio pattern
122a: circuit intaglio pattern
122b: connection pad intaglio pattern
123: second surface
124: blind hole
130: patterning photoresist oxidant layer
132: opening
140: active layer
150: Seed Layer
160: electric conducting material
D: certain distance
L: laser beam
A1: first area
A2: second area
Embodiment
Figure 1A to Fig. 1 G is the schematic top plan view of the manufacture method of a kind of line construction of one of the present invention embodiment.Fig. 2 A to Fig. 2 G illustrates the generalized section of the line I-I along Figure 1A to Fig. 1 G respectively.Please also refer to Figure 1A and Fig. 2 A, according to the manufacture method of the line construction of the present embodiment, first, there is provided a circuit base plate 110, wherein circuit base plate 110 has first surface 113 and one the 3rd surface 115,1 first patterned line layer 114 and one second patterned line layer 116 respect to one another.In the present embodiment, the first patterned line layer 114 is configured on first surface 113, and the second patterned line layer 116 is configured on second surface 115.
It should be noted that, in the embodiment that other do not illustrate, first patterned line layer 114 and the second patterned line layer 116 also can in be embedded in circuit base plate 110, that is, the first patterned line layer 114 and the second patterned line layer 116 also can be a kind of embedded line layer.In addition, the structure of the circuit base plate 110 of the present embodiment also can only have uniline layer, or has multilayer line layer.That is, circuit base plate 110 can be single-layer wire base board (singlelayercircuitboard), double-deck circuit base plate (doublelayercircuitboard) or multilayer wiring board (multi-layercircuitboard).At this, Fig. 2 A only with circuit base plate 110 for pair of lamina circuit base plate is described.
Then, refer again to Figure 1A and Fig. 2 A, pressing one dielectric layer 120 is on circuit base plate 110, and its dielectric layer 120 has a second surface 123, and dielectric layer 120 covers first surface 113 and first patterned line layer 114 of circuit base plate 110.
Then, please refer to Figure 1B and Fig. 2 B, form blind hole 124 and an intaglio pattern 122 that at least one second surface 123 from dielectric layer 120 extends to the first patterned line layer 114 of circuit base plate 110.In the present embodiment, forming blind hole 124 with the method for intaglio pattern 122 is such as irradiate a laser beam L to the second surface 123 of dielectric layer 120, and wherein irradiating light beam L is such as infrared laser light source, ultraviolet laser light source or quasi-molecule laser source.Should be noted that in this, in the present embodiment, intaglio pattern 122 is made up of at least one circuit intaglio pattern 122a and at least one connection pad intaglio pattern 122b, and wherein the width of circuit intaglio pattern 122a is less than the width of connection pad intaglio pattern 122b.
Then, please refer to Fig. 1 C and Fig. 2 C, form a patterning photoresist oxidant layer 130 on the second surface 123 of dielectric layer 120, wherein patterning photoresist oxidant layer 130 covers a part for the second surface 123 of dielectric layer 120, but patterning photoresist oxidant layer 130 do not cover blind hole 124, intaglio pattern 122 and part first patterned line layer 114 that exposes by blind hole 124.Specifically, the region at patterning photoresist oxidant layer 130 place is defined as a first area A1, and the region beyond the A1 of first area is defined as a second area A2.Patterning photoresist oxidant layer 130 has at least one opening 132 exposing blind hole 124 and intaglio pattern 122, and the edge of the opening 132 of patterning photoresist oxidant layer 130 is away from surrounding more than the certain distance D of blind hole 124 or intaglio pattern 122, wherein certain distance D is such as 1 micron.
Then, please refer to Fig. 1 D and Fig. 2 D, form an active layer 140 in first area A1 and second area A2, wherein active layer 140 coverage diagram patterning photoresist layer 130, the second surface 123 being positioned at the dielectric layer 120 of second area A2, intaglio pattern 122, blind hole 124 and part first patterned line layer 114 that exposes by blind hole 124.In addition, the material of active layer 140 is such as palladium.
Then, please refer to Fig. 1 E and Fig. 2 E, remove patterning photoresist oxidant layer 130 and be positioned at the active layer 140 of first area A1, to expose the part of the second surface 123 of the dielectric layer 120 be positioned at below patterning photoresist oxidant layer 130, and leave the active layer 130 being positioned at second area A2.
Afterwards, please refer to Fig. 1 F and Fig. 2 F, form a Seed Layer 150 on active layer 140, namely Seed Layer 150 is formed in second area A2, and wherein Seed Layer 150 covers active layer 140, and the material of Seed Layer 150 is such as copper.Then, an electric conducting material 160 is formed on the active layer 130 being positioned at second area A2.Specifically, with Seed Layer 150 for electrode, plating (plating) electric conducting material 160 is in Seed Layer 150, wherein electric conducting material 160 be the dielectric layer 120 being positioned at second area A2 second surface 123 on and in Seed Layer 150 above intaglio pattern 122 and the active layer 140 of blind hole 124, and electric conducting material 160 covers the Some Species sublayer 150 above the second surface 123 being positioned at the dielectric layer 120 of second area A2, and fill up intaglio pattern 122 and blind hole 124.In this, be filled in the electric conducting material 160 in circuit intaglio pattern 122a, then can form circuit (trace), and be filled in the electric conducting material 160 in connection pad intaglio pattern 122b, then can form connection pad (pad).In addition, the material of electric conducting material 160 is such as copper.
Finally, please refer to Fig. 1 G and Fig. 2 G, one grinding steps is carried out to electric conducting material 160, to remove partially conductive material 160 and the partial activation layer 140 and the Seed Layer 150 that are positioned at second area A2, to the second surface 123 exposing dielectric layer 120, wherein electric conducting material 160 trims in fact with the second surface 123 of dielectric layer 120.In addition, the grinding steps of the present embodiment is such as cmp (chemicalmechanicalpolish, CMP).So far, the making of line construction 100 has been completed.
Because the present embodiment is after formation intaglio pattern 122 with blind hole 124, first covered the portion second surface 123 of dielectric layer 120 by patterning photoresist oxidant layer 130, then sequentially to form active layer 140 and adopting galvanoplastic on active layer, form electric conducting material 160.Therefore, conductive copper layer is formed by electric plating of whole board compared to existing, the making of the line construction 100 of the present embodiment is only partially formed electric conducting material 160 in specific local (and place of non-coverage diagram patterning photoresist layer 130), effectively can avoid the waste of the existing cost of manufacture that produces in manufacture craft and time cost.In addition, the making of the line construction 100 of the present embodiment also can be avoided existing because extending electroplating time and produce the uneven phenomenon of conductive copper layer thickness distribution.Moreover, because the electric conducting material 160 of the present embodiment flushes in fact with the second surface 123 of dielectric layer 120, therefore follow-up when carrying out the making of build-up circuit again on this line construction 100, be suitable for making the design in folded hole and there is preferably manufacture craft yield.In addition, because the present embodiment only forms electric conducting material 160 in the place of active layer 140, not carry out comprehensive electroplating manufacturing process, and etching solution need not be used in a large number to remove unnecessary electric conducting material, therefore can reduce production cost.In addition, because the present embodiment adopts the mode of irradiating laser light beam L to form intaglio pattern 124, then form electric conducting material 160 again in intaglio pattern 124, therefore the line construction 100 of the present embodiment can have the fine rule road of better reliability.
In sum, because the present invention is after formation intaglio pattern and blind hole, the portion second surface of dielectric layer is first covered by patterning photoresist oxidant layer, then sequentially forming active layer, Seed Layer and electric conducting material in intaglio pattern and blind hole, wherein electric conducting material flushes with the second surface of dielectric layer.Therefore, be compared to the making of existing line structure, the manufacture method of line construction of the present invention can have preferably reliability and manufacture craft yield and can reduce production cost.
Although disclose the present invention in conjunction with above embodiment; but itself and be not used to limit the present invention; this operator is familiar with in any art; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining with appended claim of protection scope of the present invention.
Claims (9)
1. a manufacture method for line construction, comprising:
Pressing one dielectric layer is on a circuit base plate, and wherein this circuit base plate has first surface and the first patterned line layer, and this dielectric layer has second surface, and this dielectric layer covers this first surface and this first patterned line layer of this circuit base plate;
Form blind hole and an intaglio pattern that at least one this second surface from this dielectric layer extends to this first patterned line layer;
Form a patterning photoresist oxidant layer on this second surface of this dielectric layer, wherein this patterning photoresist oxidant layer has at least one opening exposing this blind hole and this intaglio pattern, and the edge of this at least one opening of this patterning photoresist oxidant layer is away from more than surrounding's certain distance of this blind hole or this intaglio pattern, the region at this patterning photoresist oxidant layer place is defined as a first area, and the region beyond this first area is defined as a second area;
Form an active layer in this first area and this second area, this active layer is covered in this patterning photoresist oxidant layer and is positioned in this second surface of this dielectric layer of this second area, this intaglio pattern and this blind hole;
Remove this patterning photoresist oxidant layer and be positioned at this active layer of this first area, to leave this active layer being positioned at this second area;
Form an electric conducting material on this active layer being positioned at this second area, wherein this electric conducting material fills up this intaglio pattern and this blind hole, and covers this active layer being positioned at this second area; And
Remove this electric conducting material of part and this active layer of part being positioned at this second area, trim to make this second surface of this electric conducting material and this dielectric layer.
2. the manufacture method of line construction as claimed in claim 1, wherein forms the method for this blind hole and this intaglio pattern, comprising:
One laser beam is irradiated to this second surface of this dielectric layer.
3. the manufacture method of line construction as claimed in claim 1, wherein this certain distance is 1 micron.
4. the manufacture method of line construction as claimed in claim 1, also comprises:
Formed this electric conducting material in this intaglio pattern and this blind hole before, form a Seed Layer on this active layer.
5. the manufacture method of line construction as claimed in claim 1, wherein the method for this electric conducting material comprises galvanoplastic.
6. the manufacture method of line construction as claimed in claim 1, wherein remove this electric conducting material of part and the method for this active layer of part being positioned at this second area, comprise and a grinding steps is carried out to this electric conducting material, to this second surface exposing this dielectric layer.
7. the manufacture method of line construction as claimed in claim 6, wherein this grinding steps comprises cmp (chemicalmechanicalpolish, CMP).
8. the manufacture method of line construction as claimed in claim 1, wherein this first patterned line layer be configured at this circuit base plate this first surface on or in be embedded in this circuit base plate.
9. the manufacture method of line construction as claimed in claim 1, wherein this circuit base plate also has one and to be positioned at the second patterned line layer on the 3rd surface relative to one the 3rd surface and of this first surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110305613.2A CN103052268B (en) | 2011-10-11 | 2011-10-11 | The manufacture method of line construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110305613.2A CN103052268B (en) | 2011-10-11 | 2011-10-11 | The manufacture method of line construction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103052268A CN103052268A (en) | 2013-04-17 |
| CN103052268B true CN103052268B (en) | 2016-03-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110305613.2A Expired - Fee Related CN103052268B (en) | 2011-10-11 | 2011-10-11 | The manufacture method of line construction |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150049515A (en) * | 2013-10-30 | 2015-05-08 | 삼성전기주식회사 | Printed Circuit Board and The Method of Manufacturing the same |
| TWI595820B (en) * | 2016-03-17 | 2017-08-11 | 頎邦科技股份有限公司 | Pattering process of circuit substrate and circuit substrate |
| CN106158811B (en) * | 2016-08-23 | 2019-05-14 | 江阴芯智联电子科技有限公司 | A kind of multi-layer support structure and its manufacturing method |
| CN114269065B (en) * | 2020-09-16 | 2023-08-04 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board with embedded conductive circuit and manufacturing method thereof |
| CN114885525A (en) * | 2022-03-25 | 2022-08-09 | 深圳市大族数控科技股份有限公司 | Circuit board manufacturing method and circuit board |
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|---|---|---|---|---|
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| CN102083280A (en) * | 2009-11-30 | 2011-06-01 | Lg伊诺特有限公司 | Embedded printed circuit board, multi-layer printed circuit board and manufacturing method thereof |
| CN102131346A (en) * | 2010-01-15 | 2011-07-20 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4541753B2 (en) * | 2004-05-10 | 2010-09-08 | 新光電気工業株式会社 | Manufacturing method of electronic component mounting structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101351087A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| CN102083280A (en) * | 2009-11-30 | 2011-06-01 | Lg伊诺特有限公司 | Embedded printed circuit board, multi-layer printed circuit board and manufacturing method thereof |
| CN102131346A (en) * | 2010-01-15 | 2011-07-20 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
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| CN103052268A (en) | 2013-04-17 |
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Granted publication date: 20160302 Termination date: 20171011 |