CN103051336B - Frequency synthesizer and frequency combining method - Google Patents

Abstract

A kind of frequency synthesizer, including one in order to provide the agitator of a radio frequency clock, one provides the phase shifter of a translation reference clock in order to a frequency reference clock is carried out phase change, and a time-to-digit converter, a numeral conversion output is produced in order to the time difference between this radio frequency clock and this translation reference clock to be quantified；Wherein, the scope contained needed for this time-to-digit converter is less than a complete cycle of this radio frequency clock.The present invention also provides for a kind of frequency combining method.The present invention can effectively reduce hardware complexity.

Description

Frequency synthesizer and frequency combining method

[technical field]

The present invention is about a kind of frequency synthesizer and frequency combining method, and includes time number especially in regard to one The frequency synthesizer supporting periphery mechanism of word conversion and frequency combining method.

[background technology]

Communication system miscellaneous, seems radio frequency (RF, Radio Frequency) wireless communication system, Extensively used by advanced information society, and play an important role.One of core technology of Modern Communication System Being frequency (and/or clock) synthesis, it produces one based on a frequency reference clock and has desired frequency Variable clock, so that the stability of this variable clock, degree of accuracy and frequency spectrum purity level are all associated with frequency ginseng Examine the performance of clock.In the emitter of communication system, a local frequency synthesizer variable clock provided Can as a local oscillations carrier wave, in order to fundamental frequency (baseband) or intermediate frequency (IF, Intermediate-Frequency) signal carries out rising the frequency translation turning (up-conversion), right to be formed The radiofrequency signal answered.On the other hand, in the receiver, a local frequency synthesizer variable clock provided Can be intermediate frequency/fundamental frequency signal in order to radiofrequency signal fall is turned (down-convert) as a local oscillations carrier wave.

[summary of the invention]

In view of this, it is necessary to a kind of frequency synthesizer and frequency combining method are provided.

One embodiment of the invention provides a frequency synthesizer, including one in order to receive a frequency reference clock Frequency reference input, one in order to provide the trimmed agitator of a radio frequency clock, one is coupled to this Frequency reference input, in order to change the phase shifter of the phase place of frequency reference clock, and time Digital converter, is coupled to phase shifter and trimmed agitator, in order to produce a numeral conversion output； Wherein, the scope contained needed for time-to-digit converter is less than a complete cycle of radio frequency clock.

In one embodiment, phase shifter be one digit time transducer, digital control in order to respond a conversion And postpone frequency reference clock.In one embodiment, change digital control being in response to the tired of a frequency instruction character Evaluation and be set, phase shifter is then in response to the aggregate-value (such as its decimal part) of frequency instruction character And change the phase place of frequency reference clock.

In one embodiment, frequency synthesizer further includes a translational controller, variable phase accumulation device and a ginseng Examine phase accumulation device.Variable phase accumulation device couples trimmed agitator, in order to the cycle of accumulative radio frequency clock Number also provides a variable phase signal according to this.Fixed phase integrating instrument is in order to each week of response frequency reference clock Phase and cumulative frequency instruction character, and the aggregate-value of frequency instruction character is provided according to this.Translational controller couples Phase shifter, provides a translational control signal (such as institute in order to the aggregate-value of response frequency instruction character The conversion stated is digital control) assist decimal error correction signal with one.Phase shifter is in order to respond translation control Signal processed and change the phase place of frequency reference clock, and trimmed agitator in order to according to numeral conversion output, When assisting the aggregate-value of decimal error correction signal, variable phase signal and frequency instruction character to adjust radio frequency The cycle of clock.

In one embodiment, phase shifter changes the phase place of frequency reference clock and provides a translation reference according to this Clock, make at a transition of translation reference clock with the previous transition of radio frequency clock between time difference be less than One complete cycle of radio frequency clock.In one embodiment, for the scope of time figure conversion, time figure Transducer is at the transition of radio frequency clock and when occurring at the proximity of this scope at the transition of translation reference clock Respond, and do not occur in this scope with at the transition of translation reference clock at the transition of radio frequency clock Then it is not responding to time at proximity.

One embodiment of the invention provides a frequency synthesizer, including an agitator, a phase shifter, one Time-to-digit converter, a translational controller, a fixed phase integrating instrument and a variable phase accumulation device.Shake Swing device in order to provide a variable clock.Phase shifter is in order to provide a translation reference clock so that it is phase place with The phase one phase shift amount of one frequency reference clock, this phase shift amount makes the one of translation reference clock Time difference at transition and between the previous transition of variable clock is less than a cycle of variable clock.Time Digital converter then couples phase shifter, in order to quantify described time difference to provide one first decimal error to repair Positive signal.

Fixed phase integrating instrument for each cycle of response frequency reference clock with an accumulative frequency instruction character, And a reference phase signal is provided according to this；Variable phase accumulation device then couples agitator, during in order to cumulative variations The periodicity of clock is to provide a variable phase signal.Translational controller couples phase shifter, in order to respond ginseng Examine phase signal and a translational control signal and one second decimal error correction signal are provided, make phase shifter Respond translational control signal and set phase shift amount, agitator then foundation the first decimal error correction signal, Second decimal error correction signal, reference phase signal and variable phase signal and adjust the cycle of variable clock.

One embodiment of the invention provides a frequency synthesizer, including an agitator, a time-to-digit converter, One translational controller, a phase shifter, a fixed phase integrating instrument and a variable phase accumulation device.Vibration Device in order to provide variable clock, and according to time-to-digit converter provide one first decimal error correction signal, The variable phase that one second decimal error correction signal of translational controller offer, variable phase accumulation device provide A reference phase signal that position signal and fixed phase integrating instrument provide and adjust the cycle of variable clock.Time Digital converter, in order to the time difference quantified between a translation reference clock and this variable clock and provide one according to this First decimal error correction signal, the wherein phase place of this translation reference clock and the phase place of a frequency reference clock Differ a phase shift amount.Translational controller, provides one in order to respond an aggregate-value of a frequency instruction Two decimal error correction signals.

One embodiment of the invention provides a kind of method to provide a variable clock to synthesize a frequency, including: Respond an agitator to adjust signal and produce variable clock；By phase offset one phase place of a frequency reference clock Translational movement is to obtain a translation reference clock；And, by the time difference between variable clock and translation reference clock Digitized, the scope that this digitized is contained is less than a complete cycle of variable clock.

In one embodiment, the inventive method further includes: adjusts phase shift amount, makes the one of translation reference clock Time difference between at transition and at the previous transition of variable clock less than or equal to a transition of frequency reference clock at With the time difference between the previous transition of variable clock.

In one embodiment, the inventive method further includes: add up a frequency according to each cycle of frequency reference clock Instruction character is to obtain the aggregate-value of frequency instruction character, and the decimal of the aggregate-value according to frequency instruction character Part adjusts phase shift amount；One first decimal error correction signal, foundation is obtained according to described digitized Phase shift measures to obtain one second decimal error correction signal, and believes according to first and second decimal error correction Number adjust agitator adjust signal.

Said frequencies synthesizer and frequency combining method can effectively reduce hardware complexity.

[accompanying drawing explanation]

Fig. 1 illustrates that the phase place to a variable clock and a frequency reference clock carries out the enforcement of numeral tracking Example.

Fig. 2 illustrates the embodiment of a time-to-digit converter.

Fig. 3 Yu Fig. 4 illustrates the frequency synthesizer of one embodiment of the invention and running thereof respectively.

Fig. 5 Yu Fig. 6 illustrates the frequency synthesizer of one embodiment of the invention and operation principles thereof respectively.

The frequency synthesizer of Fig. 7 Yu Fig. 8 one embodiment of the invention respectively and running thereof.

Fig. 9 illustrates that the frequency synthesizer according to one embodiment of the invention.

Figure 10 illustrates that an embodiment of management circuit of the present invention in Fig. 9.

Figure 11 illustrates that an embodiment of management circuit of the present invention in Fig. 9.

In Figure 12 example schematic 11, management circuit is according to the various runnings of one embodiment of the invention.

What Figure 13 illustrated be based on one embodiment of the invention realizes the schematic diagram of level sensor circuit in Figure 11.

[detailed description of the invention]

Refer to Fig. 1, it is illustrated that the phase place to two clock CKV Yu FREF carries out numeral tracking Conceptual embodiment, so that the frequency that the frequency of clock CKV is clock FREF is multiplied by a frequency instruction word Symbol FCW.That is, by setting a corresponding frequency instruction character FCW, so that it may based on clock FREF Produce a clock CKV with expected frequence.Clock FREF is when cycle being the frequency reference of Tr Clock.Clock CKV is then cycle to be the variable clock of Tv, and it is produced by an agitator 10, such as one Numerically-controlled oscillator (DCO, Digitally Controlled Oscillator).For carrying out frequency synthesis, vibration Device 10 can be trimmed off so that clock CKV locks a clock CKR, allows the frequency approach clock of clock CKV The product of FREF and frequency instruction character FCW, namely makes average cycle T v equal to Tr/FCW.Frequently Rate instruction character FCW can refer to a real number, has an integer part and a decimal part；Example at Fig. 1 In son, frequency instruction character FCW is 9/4, and its integer part is 2, and decimal part is then equal to 1/4.

In order to will the phase place of digitally measurement clock CKV, it is possible to provide a signal (such as a numerical character) PHV [i]. Signal PHV [i] can be considered a variable phase signal, its be at each emphasis transition of clock CKV (such as Rise edge) an accumulative unit count；That is, PHV [i+1]=PHV [i]+1, subscript i is a gomma, Represent at the i-th emphasis transition of clock CKV.It is to say, elapse over time, variable phase signal The periodicity of PHV [i] meeting accumulative clock CKV, reflects the phase place of clock CKV in units of cycle T v. The value of signal PHV [i] is integer, because it is to be added up by integer and obtain.

In order to will the phase place of digitally measurement clock FREF, the phase information of clock FREF can be at clock CKV Emphasis transition at synchronize to present so that the phase information of clock FREF can with signal PHV [i] mutually than Relatively, because signal PHV [i] is also to update at the emphasis transition of clock CKV.Therefore, clock FREF meeting It is clock CKR when being reset by a retimer 12 (such as a trigger).Retimer 12 is in order at clock When clock FREF being reset at each emphasis transition of CKV, provide clock CKR (i.e. one weight according to this Timing reference clock), make to align at an emphasis transition of clock CKV at each transition of clock CKR. The triggering of response clock CKR, it is possible to provide a signal PHR [k] is digitally to reflect the phase place of clock FREF. Signal PHR [k] is a reference phase signal, and it is cumulative frequency instruction at each emphasis transition of clock CKR Character FCW, that is PHR [k+1]=PHR [k]+FCW, subscript k is gomma, represents clock CKR Kth emphasis transition at.

According to the expection relation of frequency synthesis, cycle T r of clock FREF should be cycle T v of clock CKV It is multiplied by frequency instruction character FCW, therefore, at each cycle cumulative frequency instruction character FCW of clock CKR, It it is the phase place for reflecting clock FREF in units of cycle T v.Owing to frequency instruction character FCW can There to be a decimal part, signal PHR [k] can also have a decimal part.

During because clock CKR is reset by clock CKV, meeting and clock at each emphasis transition of clock CKR Align at an emphasis transition in CKV, and signal PHV [k], namely signal PHV [i] is at clock CKR Kth emphasis transition at value, can be compared to each other with signal PHR [k].In the example in fig 1, letter Number PHV [i0] and signal PHR [k0] aligns, and signal PHV [i0+3]=PHV [k0+1] i.e. can be synchronized with signal PHR [k0+1], by that analogy.As it is shown in figure 1, clock FREF is reset under the triggering of clock CKV Time be that clock CKR can cause an error e [k], represent at an emphasis transition of clock FREF to clock CKV A time emphasis transition at (immediate clock CKV weight after i.e. at this emphasis transition of clock FREF Point transition at) between time difference (phase error).

In the example in fig 1, when clock CKV according to anticipated relation Tv=Tr/FCW locked clock During FREF, every four cycle T r can be alignd nine cycle T v, because FCW=9/4.That is, by frequency Instruction character FCW adds up to be equal to for four times add up unit count nine times, because FCW*4=(9/4) * 4=1*9. Assume the emphasis transition of clock FREF Yu CKV be in time labelling k0 be aligned so that signal PHR [k0] with PHV [i0] is equal, then after four circulations of clock CKR, at the emphasis transition of clock FREF Yu CKV Can align once again, and the value of signal PHR [k0+4] also can meet signal PHV [i0+9] (i.e. PHV [k0+4]) Value because PHR [k0+4]=PHR [k0]+FCW*4, and PHV [i0+9]=PHV [i0]+1*9.Separately On the one hand, owing to frequency instruction character FCW has decimal part, even if clock CKV is locked clock FREF, But under each time labelling k between time labelling k0 to (k0+4), an emphasis transition of clock FREF Place can be still non-zero to the time difference between at time emphasis transition of clock CKV；This time difference can be reflected Numerical difference for signal PHV [k] Yu PHR [k].For example, as clock CKV locked clock FREF, When can lead over the time difference of (3/4) * Tv at time labelling (k0+1), the emphasis transition of clock FREF At a time emphasis transition of clock CKV, and the numerical difference between signal PHV [k0+1] and PHR [k0+1] It is poor that (PHV [k0+1]-PHR [k0+1])=(3-9/4)=3/4 i.e. reflects this time.Similarly, time Between under labelling (k0+2), at the emphasis transition of clock FREF and CKV between unjustified time difference (1/2) * Tv (PHV [k0+2]-PHR [k0+2])=(5-18/4)=2/4=1/2 can be reflected as.

Labelling k grows with each passing hour over time, the difference (PHV [k]-PHR [k]) of signal PHV [k] and PHR [k] Can change on periodic regularity ground, in units of cycle T v, reflect that the definitiveness between clock FREF and CKV is (non- Time difference (i.e. two clocks time difference between emphasis transition) (phase error) at random).Therefore, poor Different (PHV [k]-PHR [k]) becomes the definitiveness part of error e [k], and what it was reflected is by frequency instruction word The rule phase contrast that the decimal part of symbol FCW is caused.That is, as clock CKV locked clock FREF, Error e [k] can be equal to (PHV [k]-PHR [k]), or equally, PHR [k]+e [k]-PHV [k]=0.

At the emphasis transition of clock FREF the most right to the regularity between at time emphasis transition of clock CKV Neat difference can fall in the range of cycle T v；For equivalence, difference (PHV [k]-PHR [k]), i.e. error The definitiveness part of e [k], can be a decimal (or equal to zero).Since signal PHV [k] is integer, error The definitiveness part of e [k] can be associated with the decimal part of signal PHR [k].For actual application, error e [k] Also include the variation part of a random nature, the random phase that reflection noise (such as the noise of agitator 10) causes Position error.

More generally, it is assumed that frequency instruction character is represented by Nv/Nr, Nv and Nr and is integer but Nv The not integral multiple of Nr, then the definitiveness part of error e [k] can be at every Nr periodic law of clock CKR Property ground repeat, that is, error e [k] and the definitiveness of e [k+Nr] are the most equal, and can be according to frequency instruction word The decimal part of the aggregate-value (i.e. signal PHR [k]) of symbol FCW is predicted with signal PHV [k].Assume When time labelling k0, signal PHV [k0] is equal with PHR [k0], if adjusting agitator 10 so that signal The integer part of PHR [k] at interval of Nr cycle of clock CKR (i.e. at time labelling k0, (k0+Nr) Etc.) be just consistent with integer signal PHV [k], i.e. imply that the reaching of frequency lock.But, due to clock Nr the cycle of CKR can contain the cycle of many clock CKV, if can not be at every Nr of clock CKR Complete monitoring error e [k] in the individual cycle, cycle T v of clock CKV will floating drift.Fine for reaching PGC demodulation, a time-to-digit converter can be used, digitally detect with each cycle at clock CKR Error e [k], makes agitator 10 can be adjusted according to the numeral conversion output of time-to-digit converter, with really Protecting (PHR [k]+e [k]-PHV [k]) can be at each time labelling k equal convergence zero.

Refer to Fig. 2, it is illustrated that the embodiment of a time-to-digit converter 20.Time figure is changed Device 20 is coupled to two input 22a and 22b, receives two signal TDC_in and REF_in respectively；Time number Word transducer 20 also exports a signal et [k] using as a numeral conversion output.When time-to-digit converter 20 When being used to detect error e [k] in Fig. 1, clock FREF Yu CKV is received as signal REF_in respectively With TDC_in.It is preferred that time-to-digit converter 20 is in order to by 16b at an emphasis transition of signal REF_in And time difference dt digitized (quantization) between 16c at time emphasis transition of signal TDC_in, makes error e [k] Can be represented by digital signal et [k].In one embodiment, time-to-digit converter 20 is one to meet cause and effect (causal) System；Therefore it can not predict time one liter of edge 16c of signal TDC_in at the liter edge 16b of signal REF_in. Therefore, desired error measures is to deduct time tr from cycle T v and indirectly reach.In one embodiment, Upper between 16b at the follow-up emphasis transition of 16a and signal REF_in at the emphasis transition of signal TDC_in Rise time tr to be measured and quantify；Since dt=(Tv-tr), error e [k] can be derived as: e [k]=(dt/Tv) =(1-(tr/Tv)).In this embodiment, time-to-digit converter 20 the most directly produces error e [k], But the quantized value of time tr, it can be divided by cycle T v, or be multiplied by 1/Tv_avg, wherein, averagely all Phase Tv_avg is the long-term average of cycle T v of variable clock CKV.Therefore, time figure conversion is direct Output is the quantized value of tr/Tv, corresponding to the negative value of error e [k].As those skilled in the art can be appreciated that , in the input (discussing in Fig. 3) of adder 50, change sign, negative value can be easily achieved Computing.So, the difference time tr between two input signals REF_in and TDC_in is minimized, in equivalence It is exactly that error e [k] is maximized (but its value is not more than 1).In formula (1-e [k]), due to constant 1 Can be absorbed easily in phase-lock loop system (PLL system), therefore (1-e [k]) can be easily It is designated as (-e [k]).That is, biphase for 16b at the emphasis transition of signal REF_in and signal TDC_in 16a and 16c at adjacent emphasis transition, time difference between 16c at 16b and follow-up emphasis transition at emphasis transition Available error e [k] represents, and at emphasis transition, at 16b and previous emphasis transition, time difference between 16a then can use Error (-e [k]) represents, and both all can be used to the time difference (phase place between trace signals REF_in and TDC_in Difference), therefore convenient selection of visual application is used.

One embodiment of time-to-digit converter 20 includes the delay cell 18 (example that multiple (L) concatenates Such as phase inverter), multiple triggers 24 triggered by signal REF_in, and one yard of edge detector (code edge detector)26.Each delay cell 18 can introduce a unit delay time t_inv in signal TDC_in, and Export the trigger 24 to a correspondence and a time delay cell 18.Touch at the emphasis transition of signal REF_in Send out trigger 24 each and obtain one by bit Q (1), Q (2) ... Q (L) formed digital time, at emphasis transition The code edge (code edge) that the generation of 16a can be reflected as between bit Q (1) to Q (L)；Accordingly, code edge detecting Device 26 will quantify rise time tr in units of unit delay time t_inv, and is output as signal et [k]. That is, the time quantization resolution of time-to-digit converter 20 depends on the unit delay of each delay cell 18 Time t_inv.The total L of delay cell 18 then determines the measuring range of time-to-digit converter 20, this Time figure conversion range can be estimated as L*t_inv.The time interval being shorter than this time numeral conversion range is permissible It is detected, and the time interval being longer than this time numeral conversion range just cannot be detectd by time-to-digit converter 20 Measure.When time-to-digit converter 20 is used to detect the error e [k] in Fig. 1, time figure conversion Scope should completely contain cycle T v.

In order to will with finer resolution detecting error e [k] so that the characteristic of clock CKV more preferably, unit is prolonged Time t_inv should be much smaller than cycle T v late.Jointly, the delay cell 18 that time-to-digit converter 20 needs Total L will become the most, so that time figure conversion range be enough to contain cycle T v.For example, To contain the cycle of 2.4GHz with 7ps (1ps as microsecond 1/1000000th), take around 60 delay cells 18 are to realize time-to-digit converter 20.Delay cell more than 18 used, consumption Power is the biggest, and its Interference from current caused (such as supplying variation and/or the reduction of voltage) is the most serious. Serious Interference from current is settled out, just need to use large-area decoupling capacitor, effective for realizing one The area taken needed for time-to-digit converter also will thus increase.Furthermore, serious Interference from current also can The linearity making time figure change reduces, because unit delay time t_inv can float with supply variation in voltage Move.It is therefore desirable to have the delay cell number that the neighboring technology supported is needed for reducing, and promote time number The linearity of word conversion.

Refer to Fig. 3, what it was illustrated is based on the frequency synthesizer 30 of one embodiment of the invention.Frequency is closed Grow up to be a useful person 30 include one in order to receive a frequency instruction character FCW frequency instruction character input 32a, One in order to receive the frequency reference input 32b of a frequency reference clock FREF, a fixed phase integrating instrument 34, a variable phase accumulation device 36, loop filter 38, agitator 10, phase shifter 46, One translational controller 42, time-to-digit converter 40, adder 50 and a retimer 12.Vibration Device 10 provides a variable clock CKV, such as during a radio frequency in order to adjust character OTW according to an agitator Clock, so that the frequency of variable clock CKV can be when variable clock CKV locking frequency reference clock FREF It is multiplied by frequency reference clock FREF equal to frequency instruction character FCW.

Retimer 12 couples agitator 10 and frequency reference clock FREF, in order at variable clock CKV Emphasis transition at (such as rising edge) time frequency reference clock FREF is reset, to provide a weight timing reference Clock CKR.Fixed phase integrating instrument 34 couples frequency reference clock via frequency reference input 32b FREF, (such as says the reference clock CKR when resetting in order to each cycle according to frequency reference clock FREF Each emphasis transition at) cumulative frequency instruction character FCW, reference phase signal PHR [k] is provided according to this. In figure 3, reference phase signal PHR [k] can be analyzed to a decimal part PHRf [k] and an integer part PHRi[k].Variable phase accumulation device 36 couples agitator 10, in order to the periodicity of cumulative variations clock CKV, One variable phase signal PHV [k] is provided according to this.

Phase shifter 46 is coupled to agitator 10 and translational controller 42, in order to control letter according to a translation Number SEL and change the phase place of variable clock CKV, a translation variable clock CKV ' is provided according to this.Or, Phase shifter 46 can be by selecting one to carry out phase change in multiple phase places of variable clock CKV.Should Multiple phase places can be in the internal generation of phase shifter 46.Time-to-digit converter 40 be functionally similar to Fig. 2 Shown time-to-digit converter 20；Time-to-digit converter 40 couples phase shifter 46 and frequency reference Input 32b, in order to be received as letter by frequency reference clock FREF respectively with translation variable clock CKV ' Number REF_in and TDC_in, and according to frequency reference clock FREF with translate between variable clock CKV ' Time difference provides decimal error correction signal PHF1 [k].That is, time-to-digit converter 40 is to detect Survey (quantization) frequency reference clock FREF an emphasis transition at translate variable clock CKV ' previous Time difference between at emphasis transition, and the time difference detected is reflected with a signal et [k]；And decimal error is repaiied Positive signal PHF1 [k] is then to measure this time difference in units of cycle T v of variable clock CKV, its be by Signal et [k] normalization to one average period Tv_avg and obtain；Wherein, when average period, Tv_avg was variable Cycle T v of clock CKV long-term average, because cycle T v can refer to a variations per hour.

For with phase shifter 46 Collaboration, translational controller 42 couples phase shifter 46, in order to carry For translational control signal SEL and another decimal error correction signal PHF2 [k].Adder 50 couples variable phase Position integrating instrument 36, fixed phase integrating instrument 34, translational controller 42 and time-to-digit converter 40, in order to According to reference phase signal PHR [k], variable phase signal PHV [k] and decimal error correction signal PHF1 [k] A signal is provided with the combinations of values (PHR [k]+PHF1 [k]+PHF2 [k]-PHV [k]) of PHF2 [k] PHE[k].Loop filter 38 is coupled between agitator 10 and adder 50, in order to basis signal PHE [k] Agitator is provided to adjust character OTW.Adjust character OTW via agitator, agitator 10 equivalence is i.e. According to reference phase signal PHR [k], variable phase signal PHV [k] and decimal error correction signal PHF1 [k] The cycle length of variable clock CKV is adjusted with PHF2 [k].

Refer to Fig. 4, its illustrated that frequency synthesizer 30 is according to the time figure of one embodiment of the invention Transition operation.Phase shifter 46 (Fig. 3) is in order at variable clock CKV and translation variable clock CKV ' Between introduce phase shift amount PHoffset.Due to this phase shift amount PHoffset, frequency reference clock Error (1-e [k]) between FREF and previous variable clock CKV can be reduced to less error (1-e ' [k]), Namely reduce the difference time between frequency reference clock FREF and translation variable clock CKV '；Wherein, -e [k]=-e ' [k]+PHoffset.In other words, phase shift amount PHoffset is to make frequency reference clock At the emphasis transition of FREF and translation variable clock CKV ' previous emphasis transition between time difference the least Cycle T v in variable clock CKV；That is, make one of error-e ' [k] not more than cycle T v Point.Owing to translation variable clock CKV ' and frequency reference clock FREF is received as signal TDC_in respectively With REF_in, therefore time-to-digit converter requirementization one is significantly less than the error-e ' [k] of cycle T v.Also That is, the time figure conversion range of time-to-digit converter 40 only need to contain the some of single cycle Tv, It is not required to completely contain whole cycle T v.For equivalence, time-to-digit converter 40 is when translation variable clock Time number is all betided with at an emphasis transition of frequency reference clock FREF at the one emphasis transition of CKV ' Just respond time at the proximity of word conversion range；When translation variable clock CKV ' an emphasis transition at When not betiding at the one emphasis transition of frequency reference clock FREF at the proximity of time figure conversion range, time Between digital converter be not required to respond.Since time figure conversion range can be contracted by, time figure is changed 40 small numbers of delay cells of need of device；Therefore, it is not required to sacrifice the resolution of time figure conversion, time The hardware complexity of digital converter 40, power consumption, the layout area taken, Interference from current are with non-linear Degree also can be can be effectively reduced.

As discussed in fig. 1, error e [k] includes a time-varying but predictable definitiveness part, corresponds to (PHR[k]-PHV[k]).Based on the definitiveness part of rule change, translational controller 42 meeting in error-e [k] Dynamically set phase shift amount PHoffset with translational control signal SEL, make the phase shift amount can be from error The definitiveness part of-e [k] reduces and forms error-e ' [k].For example, when the definitiveness portion of error-e [k] When part estimates will fall in the range of 1/4 (being equivalent to the phase place of 90 degree) to 1/2 (180 degree), phase place is put down Shifting amount PHoffset can be set to 90 degree (being equivalent to 1/4), makes error-e ' [k] can maintain 0 to 1/4 In the range of.Similarly, elapse in time, when the definitiveness part of error-e [k] will enter 1/2 to 3/4 In the range of time, phase shift amount PHoffset is set to 180 degree (namely 1/2 of cycle T v) the most therewith, Error-e ' [k] is made to be still maintained in the scope of 0 to 1/4.Phase shift amount PHoffset reduced for compensation, Translational controller 42 can inject decimal error correction signal PHF2 [k] to adder 50, to reflect phase shift Amount PHoffset；Error-the e ' [k] quantified due to decimal error correction signal PHF1 [k] representative, therefore error-e [k] Can be calculated as :-e [k]=(PHF1 [k]+PHF2 [k]), corresponding to-e [k]=(-e ' [k]+PHoffset). So, when agitator 10 adjust the cycle of variable clock CKV so that signal PHE [k] is minimized time (the most just It is that (PHR [k]-PHV [k]+e [k])=(PHR [k]-PHV [k]+PHF1 [k]+PHF2 [k]) is minimized Time, it is assumed herein that be Equations of The Second Kind phase-lock loop), frequency synthesis can be reached.In other words, frequency synthesis Device 30 is than being intended to be a digital phase-lock loop (ADPLL, All-Digital Phase Lock Loop).

In one embodiment, variable phase signal PHV [k] of integer is a fixed point (fixed point) numerical character, Formed by WI bit.Reference phase signal PHR [k] is also certain point number word character, individual by (WI+WF) Bit is formed, including a WI bit integer partly with the decimal part of a WF bit.Two decimals are by mistake Difference is revised signal PHF1 [k] and can be represented little with the fixed-point mathematics character of WF bit respectively with PHF2 [k] Number.Signal PHE [k] be one with the fixed-point mathematics character of sign (signed), there is (WI+WF) Individual bit, including integer part and the decimal part of a WF bit of a WI bit.

Refer to Fig. 5, the phase shifter 46 of its citing signal one embodiment of the invention.In Figure 5, phase Position translation device 46 includes frequency divider 44 and a phase selector 48.Frequency divider 44 couples agitator 10, In order to variable clock CKV is divided, with the time different according to the multiple phase places of variable clock CKV offer Choosing translation clock CKVp (1), CKVp (2) ..., CKVp (n) to CKVp (Np).For example, candidate The phase place of translation clock CKVp (n) can differ (n-1) * 360/Np with the phase place of candidate displacement clock CKVp (1) Degree.Phase selector 48 couples frequency divider 44 and translational controller 42, in order to according to translational controller 42 Translational control signal SEL and select from candidate displacement clock CKVp (1) to CKVp (Np) one using as Translation variable clock CKV '.

In one embodiment, frequency divider 44 in order to by the frequency of variable clock CKV divided by two, provide four according to this Candidate displacement clock CKVp (1) of individual quadrature phase (quadrature phase) is to CKVp (4)；That is, wait Choosing translation clock CKVp (n) differs the phase shift amount that 90* (n-1) spends, for n with between variable clock CKV =1 to 4.Refer to Fig. 6, it is illustrated that time figure transition operation based on quadrature phase.Originally, The complete distribution of error-e [k] be 360 degree (i.e. a cycle T v) of variable clock CKV, but due to One of them of four quadrature phases can be chosen as translating variable clock CKV ', therefore the scope of error-e [k] can be reflected Being incident upon the smaller range of error-e ' [k], it is only 90 degree, i.e. 1/4th of cycle T v.

For example, error-e [k] is being predicted according to the decimal part PHRf [k] of reference phase signal PHR [k] By when entering scope S0 by 0 to 90 degree, candidate displacement clock CKVp (1) can be selected by translational controller 42 For translation variable clock, make error-e ' [k] also can 0 to 90 degree scope in；Translational controller 42 is also Decimal error correction signal PHF2 [k] that can will be equivalent to 0 degree is injected into adder 50.When error-e [k] is pre- When meter enters scope S1 of 90 degree to 180 degree, translational controller 42 can change puts down the candidate of 90 degree of phase places Move clock CKVp (2) and elect translation variable clock CKV ' as, make error-e ' [k] still be restricted to 0 to 90 degree In the range of.Accordingly, translational controller 42 also can be equivalent to 90 degree (during with cycle T v for unit by one I.e. 1/4) decimal error correction signal PHF2 [k] is injected into adder 50.

Similarly, when error-e [k] will enter to scope S2 of 180 degree to 270 degree, and candidate displacement Clock CKVp (1) differs candidate displacement clock CKVp (3) of 180 degree and can be selected, and makes error-e ' [k] still It is maintained at the scope of 0 to 90 degree；It is equivalent to decimal error correction signal PHF2 [k] of 180 degree (numerical value 1/2) Also adder 50 can be injected into.When anticipated scope S3 that will enter to 270 degree to 360 degree of error-e [k] Time, candidate displacement clock CKVp (4) differing 270 degree with candidate displacement clock CKVp (1) can be selected, Allow error-e ' [k] still can be maintained at the scope of 0 to 90 degree；270 reduced from error-e [k] for compensation Degree phase shift amount, decimal error correction signal PHF2 [k] being equivalent to 270 degree can be injected into adder 50。

As it is shown in figure 5, because time-to-digit converter 40 is in order to detect error-e ' [k] rather than error-e [k], Therefore the time figure conversion range of time-to-digit converter 40 only needs to contain 0 to 90 degree, i.e. variable clock CKV Cycle T v 1/4th, and incomplete cycle T v.

From the embodiment of Fig. 3 to Fig. 6, the present invention can be that time-to-digit converter 40 provides support periphery, Including phase shifter 46 and translational controller 42.Owing to the definitiveness part of rule time-varying in error-e [k] can Decimal part based on reference phase signal PHR [k] and predicted, therefore dynamically set the phase of a correspondence Position translational movement PHoffset, and it is reduced to provide another error-e ' [k] from error-e [k], make error-e ' The distribution of [k] is less than complete cycle T v.Therefore, the time needed for time-to-digit converter 40 Numeral conversion range just can reduce, and makes time-to-digit converter 40 can benefit from relatively low hardware complexity (example Such as less delay cell and/or decoupling capacitor), relatively low power consumption, less layout area, relatively low Interference from current, and the linearity of time figure conversion can be promoted, without the parsing sacrificing time figure conversion Degree.Translational controller 42 available digital logic circuit realizes.

Refer to Fig. 7, what it was illustrated is based on the frequency synthesizer 60 of one embodiment of the invention.It is similar to Frequency synthesizer 30 shown in Fig. 3, the frequency synthesizer 60 in Fig. 7 includes one in order to receive a frequency The frequency instruction character input 32a of instruction character FCW, one in order to receive a frequency reference clock FREF Frequency reference input 32b, fixed phase integrating instrument 34, variable phase accumulation device 36, primary Ioops Wave filter 38, one agitator 10, translational controller 62, phase shifter 66, time figure turns Parallel operation 40, one adder 50 and a retimer 12.Agitator 10 adjusts character OTW according to an agitator Thering is provided a variable clock CKV, such as one radio frequency clock, with when variable clock CKV locking frequency reference The frequency making variable clock CKV during clock FREF is multiplied by frequency reference clock equal to frequency instruction character FCW The frequency of FREF.In frequency synthesizer 60, fixed phase integrating instrument 34, variable phase accumulation device 36, The running of time-to-digit converter 40, adder 50 and retimer 12 can be by Fig. 3 frequency synthesis with function Similar elements inference in device 30 is learnt.Variable phase accumulation device 36 couples agitator 10, in order at variable Add up a unit count at each emphasis transition of clock CKV, variable phase signal PHV [k] is provided according to this. According to reference clock CKR when resetting of retimer 12, fixed phase integrating instrument 34 response weight timing reference Cumulative frequency instruction character FCW at the emphasis transition of clock CKR, to provide a reference phase signal PHR[k]。

Phase shifter 66, such as one transducer digit time (DTC, digital-to-time Converter), It is coupled to frequency reference input 32b and time-to-digit converter 40, in order to according to a translational control signal SEL Postpone frequency reference clock FREF (or changing its phase place), a translation reference clock FREF ' is provided according to this. Variable clock CKV inputs respectively as signal TDC_in with REF_in with translation reference clock FREF ' To time-to-digit converter 40, therefore time-to-digit converter 40 detects (quantization) is in time translating reference Error-e ' [k] at the one emphasis transition of clock FREF ' and between the previous emphasis transition of variable clock CKV (time difference), and provide decimal error correction signal PHF1 [k] as response according to this.For with phase shift Device 66 Collaboration, translational controller 62 (such as a digit time conversion compensator) is coupled to phase shift Device 66 and adder 50, provide one in order to the decimal part PHRf [k] according to reference phase signal PHR [k] Translational control signal (as digital control in a conversion) SEL and another decimal error correction signal PHF2 [k].? Translational controller 62 is with under the support of phase shifter 66, and the time figure of time-to-digit converter 40 is changed Scope can be less than a part for variable clock CKV cycle T v.

Refer to Fig. 8, its illustrated that phase shifter 66, translational controller 62 are changed with time figure The Collaboration situation of device 40.With variable clock CKV at an emphasis transition of frequency reference clock FREF Previous emphasis transition between have error-e [k], and PGC demodulation i.e. needs the relevant information of this error-e [k]；Right This, translational controller 62 can dynamically adjust translation control according to the decimal part of reference phase signal PHR [k] Signal SEL and decimal error correction signal PHF2 [k], make translational control signal SEL and decimal error correction Signal PHF2 [k] can follow the definitiveness part of error-e [k] and update.Phase shifter 66 is in order to make frequency Phase change (i.e. postponing in equivalence) phase shift amount PHdelay of reference clock FREF；This phase place is put down Shifting amount PHdelay is based on set by translational control signal SEL, and it is to make translation reference clock FREF ' An emphasis transition at and the previous emphasis transition of variable clock CKV between error-e ' [k] less than the cycle A part of Tv, is also smaller than equal to error-e [k].Equally, phase shift amount PHdelay can error-e [k] Middle subduction and form error-e ' [k].Because the error-e ' that time-to-digit converter 40 only requirementization is less [k] rather than error-e [k], therefore time-to-digit converter 40 can benefit from less time figure conversion range.Little Number error correction signal PHF2 [k] is in order to compensate phase shift amount PHdelay of subduction, such as Fig. 7 Yu Fig. 8 institute Show.

For example, when error-e [k] is in the scope of 1/4 to 1/2, and phase place can be put down by translational controller 62 Shifting amount PHdelay is preferably set as (1/4) * Tv, makes the required error-e ' measured of time-to-digit converter 40 [k] can be between the scope of 0 to 1/4.When error-e [k] is in the scope of 1/2 to 3/4, translational controller 62 Can change and phase shift amount PHdelay is preferably set as (1/2) * Tv, needed for making time-to-digit converter 40 Measure error-e ' [k] be still maintained at 0 to 1/4 scope, and non-zero to 1 full breadth.Because the time Digital converter 40 is the transition at a transition of variable clock CKV with translation reference clock FREF ' Place responds, at a transition of variable clock CKV when occurring at the proximity of time figure conversion range When not occurring at the proximity of time figure conversion range at the transition with translation reference clock FREF ' the most not Respond, therefore the hardware complexity of time-to-digit converter 40 (delay cell number as required) can have Effect reduces, and contributes to the minimizing of power consumption, the reduction of Interference from current and the improvement of the linearity.

In one embodiment, the frequency of the frequency reference clock FREF frequency far below radio frequency variable clock CKV, Therefore phase shifter 66 only need to operate in low speed.In one embodiment, phase shifter 66 is with a digit time Transducer realizes, in order to the translational control signal SEL (i.e. changing digital control) of numeral is converted to phase place Translational movement PHdelay (i.e. one time delay).This digit time transducer available digital programmable delay line (digitally programmable delay line) realizes.For guaranteeing that suitable vulnerability to jamming (immunity) is with right Anti-processing procedure, supply voltage and temperature variations, frequency synthesizer 60 can include the relevant school of transducer digit time Positive mechanism and/or program.

In Fig. 3, Fig. 5 embodiment with Fig. 7, agitator 10 is trimmed agitator；It is adjusted So that variable clock CKV is able to track frequency reference clock FREF.The signal provided by adder 50 PHE [k] can be fed back to agitator 10 via loop filter 38, makes variable clock CKV be able to by further Preferably finely tune.In one embodiment, loop filter 38 is a wave digital lowpass filter.Loop filter 38 Available finite impulse response (FIR) (FIR, Finite Impulse Response) wave filter and infinite impulse response (IIR, Infinite Impulse Response) filter combination framework forms.For example, in an embodiment, loop The aggregate-value of wave filter 38 composite signal PHE linearly and signal PHE and provide agitator to adjust character, Making frequency synthesizer is Equations of The Second Kind loop.

In Fig. 3, Fig. 5 embodiment with Fig. 7, time-to-digit converter 40 receives translation variable at a high speed Clock CKV ' (Fig. 3 and Fig. 5) or variable clock CKV (Fig. 7) are as signal TDC_in, and receive low The frequency reference clock FREF (Fig. 3 and Fig. 5) of speed or translation reference clock FREF ' (Fig. 7) are as signal REF_in.Time difference between time-to-digit converter 40 quantized signal TDC_in and REF_in, and Decimal error correction signal PHF1 [k] is updated at each emphasis transition of signal REF_in.But, no matter decimal Whether error correction signal PHF1 [k] is triggered renewal, and time-to-digit converter 40 all can receive height constantly The signal TDC_in of speed thixotroping (toggling).High speed thixotroping can consume much power, causes serious power supply Interference, and the related linearity deterioration making time figure change.For solving this difficult point, the present invention is with a power Administrative mechanism suppresses non-essential pulse in signal TDC_in, only retains and leads over the secondary of signal REF_in Immediate Sing plus at one emphasis transition, reduces power consumption and Interference from current accordingly, and time normal Between numeral conversion be also unaffected.

Refer to Fig. 9, what it was illustrated is based on the frequency synthesizer 70 of one embodiment of the invention.It is similar to Frequency synthesizer 30 and 60, frequency synthesizer 70 includes the frequency receiving a frequency instruction character FCW Instruction character input 32a, in order to receive a frequency reference clock FREF frequency reference input 32b, In order to produce the agitator 10 of a variable clock CKV, in order at each emphasis transition of variable clock CKV The retimer of reference clock CKR time when frequency reference clock FREF is reset to provide one to reset 12, according to reference clock CKR cumulative frequency instruction character FCW when resetting to provide a reference phase signal The fixed phase integrating instrument 34 of PHR [k], at each emphasis transition of variable clock CKV accumulative units counting With provide variable phase signal PHV [k] variable phase accumulation device 36, in order to quantized signal TDC_in with Time difference between REF_in also provides the time-to-digit converter of decimal error correction signal PHF1 [k] according to this 80, in order to provide the adder 50 of signal PHE [k], and loop filter 38, in order to respond signal PHE [k] And provide an agitator to adjust character OTW to agitator 10.

Furthermore, frequency synthesizer 70 further includes one and inputs in order to receive the variable clock of a signal TDC_in0 End 78a, one in order to receive the frequency reference input 78b of a signal REF_in0, a translational controller 72, One phase shifter 76 and a management circuit 74.Translational controller 72 is in order to according to reference phase signal The decimal part PHRf [k] of PHR [k] and provide another decimal error correction signal PHF2 [k] to control with a translation Signal SEL, make adder 50 can by numerical difference (PHR [k]-PHV [k]) and numerical value and (PHF1 [k]+ PHF2 [k]) it is added and signal PHE [k] is provided.Phase shifter 76 couples translational controller 72, in order to change Change variable clock CKV or the phase place of frequency reference clock FREF, and signal TDC_in0 and REF_in0 There is provided according to variable clock CKV and frequency reference clock FREF the most respectively.Management circuit 74 coupling Meet variable input end of clock 78a and frequency reference input 78b, and output signal REF_in and TDC_in； Wherein, signal TDC_in is provided as the Sing plus in signal TDC_in0, and it leads over signal REF_in A time emphasis transition at.

In one embodiment, translational controller 72 is similar to translate control with the Collaboration of phase shifter 76 Device 42 and the Collaboration of phase shifter 46 (Fig. 3)；Phase shifter 76 responds translational control signal SEL and by phase change one phase shift amount PHoffset of variable clock CKV, and accordingly provide translation become Clock CKV ' is as signal TDC_in0 for amount.Translational controller 72 injects decimal error correction signal PHF2 [k] To compensate phase shift amount PHoffset, frequency reference clock FREF is then provided to management circuit 74 using as signal REF_in0.

In another embodiment, translational controller 72 is then similar to translation with the Collaboration of phase shifter 76 Controller 62 and the Collaboration of phase shifter 66 (Fig. 7)；Phase shifter 76 is according to translation control Signal SEL and frequency reference clock FREF is postponed phase shift amount PHdelay, accordingly provide one translation Reference clock FREF ' is using as signal REF_in0.Translational controller 72 injects decimal error correction signal PHF2 [k] is to compensate phase shift amount PHdelay, and variable clock CKV is then provided to management circuit 74 using as signal TDC_in0.

Via the Collaboration of translational controller 72 with phase shifter 76, signal TDC_in0 and REF_in0 Between time difference (i.e. error-e ' [k]) one will be distributed in less than in the range of complete cycle Tv.

Refer to Figure 10, what it was illustrated is based on management circuit 74A of one embodiment of the invention, its May be used to the management circuit 74 realized shown in Fig. 9.Management circuit 74A includes two gates 82a With 82b, an and delayer (delay element) 82c.Gate 82a couples signal REF_in0 in two inputs With REF_in, in order to logical operations between basis signal REF_in0 and REF_in (as to signal REF_in0 Anti-phase work and computing with signal REF_in) result one bolt (gating) signal CON is provided.Postpone Device 82c couples signal REF_in0 and gate 82a, in order to signal REF_in0 is postponed a time delay Tdelay and signal REF_in is provided.Gate 82b is respectively coupled to latch signal CON in its two input With signal TDC_in0, in order between basis signal TDC_in0 and latch signal CON and the result of computing and carry For signal TDC_in.

When signal REF_in0 84a at an emphasis transition is used by logical zero transition to logic 1, gate 82a So that latch signal CON is set as logic 1；When signal REF_in at emphasis transition 84b by logical zero Transition is to logic 1, and gate 82a is in order to set back logical zero by latch signal CON.So, bolt letter Number CON time delay between 84a and 84b will maintain a logic 1 at emphasis transition in Tdelay Window.When latch signal CON is logical zero, gate 82b is in order to suppress in signal TDC_in0 Pulse；When latch signal CON is logic 1, gate 82b is letter in order to follow signal TDC_in0 Number TDC_in provides Sing plus 86a, and it can lead over 84b at a time emphasis transition.In other words, when depending on When the number of it is believed that TDC_in0 provides signal TDC_in, only Sing plus 86a can be retained in signal TDC_in In, other the inessential pulses in signal TDC_in0, such as pulse 86b and 86c, all can be believed by bolt Number CON suppression.Signal REF_in Yu TDC_in can be transferred to time-to-digit converter 80, and at that time Between digital converter 80 turn for time emphasis of 84c at the emphasis transition of pulse 86a and signal REF_in At state between 84b time interval THA detecting (quantization) correspondence time difference time, error-e ' can be obtained [k]。

By suppress inessential pulse and at time emphasis transition of signal REF_in before retain single arteries and veins Punching, can avoid the high speed thixotroping to time-to-digit converter 80, also not interfere with time-to-digit converter 80 Normal function；Therefore, power consumption can effectively reduce, and the linearity of time figure conversion also can be because supplying Electrical interference is suppressed and improves therewith.At the emphasis transition of signal REF_in after 84b, no matter signal Whether TDC_in occurs another (or several) other pulses (such as pulse 86d), time-to-digit converter 80 correctly operate all without impacted because time interval THA can at emphasis transition before 86d just by Measure (renewal).But, other pulses in signal TDC_in, the running of voltage supply network can be made Become negative effect, therefore these pulses are non-ideal and lock of should trying one's best removes.

Due to the Collaboration of translational controller 72 with phase shifter 76, signal TDC_in0 and REF_in0 Between the length of error-e ' [k] can fall in the time figure conversion range shorter than cycle T v, and when postponing Between Tdelay can be set to be less than cycle T v.Otherwise, if the length of error-e ' [k] is distributed in one completely In cycle T v, time delay, Tdelay was necessary for longer than cycle T v, to guarantee Tdelay's time delay Window still can capture at least one under the duration aspect that error-e ' [k] is longer in signal TDC_in At individual emphasis transition.But, if time delay, Tdelay was longer than cycle T v, its window can tend at signal TDC_in catches multiple pulse, and the most therefore the linearity of time figure conversion reduces, because attaching most importance to At transition, the many after pulses before 84b can cause higher Interference from current when measuring time interval THA.

For the suitable setting value of Tdelay time delay, time delay, the lower limit of Tdelay was that time figure turns Changing scope, the setting of its upper limit is then intended at emphasis transition avoid multiple-pulse before 84b.Therefore, Time delay, the tolerable variation of Tdelay was positive and negative (Tv/2-Tc)/2, and wherein Tc i.e. represents time figure conversion Scope.

Refer to Figure 11 and Figure 12；Figure 11 illustrates that another power management according to one embodiment of the invention Circuit 74B, Figure 12 signal is then the running in its two different states of management circuit 74B.Merit Rate management circuit 74B may be used to the management circuit 74 realized shown in Fig. 9.Management circuit 74B bag Include two gates 82a and 82b, a delayer 82c and a level sensor circuit 82d.Gate 82a Two inputs are respectively coupled to signal REF_in0 and REF_in, in order to basis signal REF_in0 and REF_in Between the result of logical operations one latch signal CON is provided.Delayer 82c couples signal REF_in0 and logic Door 82a, in order to signal REF_in0 is postponed one time delay Tdelay and signal REF_in is provided.Level Two inputs of sensing circuit 82d couple signal TDC_in0 and latch signal CON, in order to basis signal TDC_in0 and latch signal CON and another latch signal CON ' is provided.Two inputs of gate 82b Couple latch signal CON ' and signal TDC_in0, in order to basis signal TDC_in0 and latch signal CON ' Between provide signal TDC_in with the result of computing.

As shown in figure 12, when signal REF_in0 84a at emphasis transition is logic 1 by logical zero transition, Gate 82a is in order to be set as logic 1 by latch signal CON；When signal REF_in is at emphasis transition 84b is logic 1 by logical zero transition, and gate 82a is in order to set back logical zero by latch signal CON.As Shown in the situation 1 of Figure 12, when at transition, 90a is logic 1 by logical zero transition to latch signal CON, If signal TDC_in0 is logical zero, then level sensor circuit 82d in order to 90b at transition by latch signal CON ' is set as logic 1.On the other hand, as shown in the situation 2 of Figure 12, when latch signal CON exists When at transition, 90a is logic 1 by logical zero transition, if signal TDC_in0 is logic 1, then level sensing Circuit 82d can wait signal TDC_in0 when logical zero is returned in transition after a while just at transition 90c by latch signal CON ' is set as logic 1.Level sensor circuit 82d is more in order to return logical zero in latch signal CON transition Time latch signal CON ' is set back logical zero.In other words, at latch signal CON at Tdelay time delay In the window opened, when signal TDC_in0 is logical zero, level sensor circuit 82d can be at latch signal CON ' opens one second window.

When latch signal CON ' is logical zero, gate 82b in order to suppress the pulse in signal TDC_in0, Such as pulse 88a and 88b.When latch signal CON ' is logic 1, and gate 82b is then in order to follow signal TDC_in0 and be that signal TDC_in provides a Sing plus 86a, make signal TDC_in at signal REF_in Emphasis transition at only have 84c at the single emphasis transition of pulse 86a before 84b.Time-to-digit converter 80 can measure at emphasis transition the period between 84c and 84b and detect error-e ' [k].At signal TDC_in In, because of only Sing plus 86a before 84b at transition of attaching most importance to, therefore time-to-digit converter 80 can be avoided Inessential thixotroping, and promote the linearity of time-to-digit converter 80.

As shown in the situation 2 of Figure 12, if with latch signal CON grid except the arteries and veins in (gate) signal TDC_in0 Punching, has after pulse more than between 90d at 90a and fall edge transition at emphasis transition and is included in signal In TDC_in, and these many after pulses will reduce the linearity of time-to-digit converter 80.But, due to Level sensor circuit 82d can avoid the period that signal TDC_in0 is logic 1 adaptively, therefore can use bolt Many after pulses got rid of by the narrower window of signal CON '；So, only just can ensure that at emphasis transition before 84b There is Sing plus, to safeguard the linearity.Under the running of level sensor circuit 82d, management circuit 74B Can be more strong, variation time delay to delayer 82c has preferably vulnerability to jamming, because Tdelay time delay Tolerable postpone variation can be exaggerated to positive and negative (Tv-Tc)/2.

Refer to Figure 13, an example of its illustrated that level sensor circuit 82d, it is anti-that it includes one Phase device 94 and a S/R latch, this S/R latch is formed with 92b by two NAND gate 92a.NAND gate Two inputs of 92a and an outfan are respectively coupled to signal TDC_in0, node n0 and node n1.NAND gate Two inputs of 92b and an outfan are then respectively coupled to latch signal CON, node n1 and node n0.Anti-phase Device 94 is coupled between NAND gate 92b and gate 82b.When signal TDC_in0 is logic 1, bolt Signal CON ' can be latched as logical zero, and when signal TDC_in0 is logical zero, latch signal CON ' Will be released and be followed latch signal CON.

For summary, the present invention is that the time-to-digit converter in digital frequency synthesizer provides relevant propping up Help periphery.When with the time difference (phase between digital frequency synthesizer monitoring variable clock with frequency reference clock Position error) time, one of them phase place of variable clock and frequency reference clock can be according to frequency instruction character Aggregate-value translates adaptively, so that within described time difference can be maintained at the partial periodicity of variable clock, Time figure conversion range the most just can be set to the complete cycle being shorter than variable clock.Furthermore, feedback is to the time The inessential high frequency thixotroping pulse of digital converter also can be removed by lock, and not influence time numeral conversion normal Function.It can be that frequency synthesizer brings many advantages that less time figure conversion range and the lock of thixotroping remove, Such as make linearity improvement that time figure changes, reduce hardware complexity, reduce power consumption, reduction cloth Situation is long-pending, reduce the demand of decoupling capacitor, and can suppress Interference from current.

Claims (26)

1. a frequency synthesizer, it is characterised in that this frequency synthesizer comprises:

One frequency reference input, in order to receive a frequency reference clock；

One trimmed agitator, in order to provide a radio frequency clock；

One phase shifter, couples this frequency reference input, in order to change the phase place of this frequency reference clock； And

One time-to-digit converter, in order to produce a numeral conversion output, this time-to-digit converter is coupled to This phase shifter and this trimmed agitator；

Wherein, a time figure conversion range of this time-to-digit converter is complete less than the one of this radio frequency clock Cycle.

2. frequency synthesizer as claimed in claim 1, it is characterised in that wherein this time-to-digit converter In order to the frequency reference clock after receiving this change phase place with this radio frequency clock to produce the conversion output of this numeral, And the conversion output of this numeral is at a transition of the frequency reference clock after quantifying this change phase place and this radio frequency A time difference between the previous transition of clock and obtain.

3. frequency synthesizer as claimed in claim 1, it is characterised in that wherein this phase shifter is Digit time, transducer, digital control and postpone this frequency reference clock in order to respond a conversion.

4. frequency synthesizer as claimed in claim 3, it is characterised in that wherein this conversion is digital control is Respond the aggregate-value of a frequency instruction character and be set.

5. frequency synthesizer as claimed in claim 3, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, in order to responding the aggregate-value of a frequency instruction character and There is provided this conversion digital control.

6. frequency synthesizer as claimed in claim 5, it is characterised in that wherein this translational controller is more used There is provided an auxiliary decimal error correction signal to respond the aggregate-value of this frequency instruction character, and this is trimmed When agitator more adjusts this radio frequency in order to respond the conversion output of this numeral and this auxiliary decimal error correction signal The cycle of clock.

7. frequency synthesizer as claimed in claim 1, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, in order to responding the aggregate-value of a frequency instruction character and One auxiliary decimal error correction signal is provided；

Wherein, this trimmed agitator is more in order to according to the conversion output of this numeral and this auxiliary decimal error correction Signal and adjust the cycle of this radio frequency clock.

8. frequency synthesizer as claimed in claim 7, it is characterised in that wherein this translational controller is more used There is provided a conversion digital control to respond the aggregate-value of this frequency instruction character, and this phase shifter in order to Respond this conversion digital control and change the phase place of this frequency reference clock.

9. frequency synthesizer as claimed in claim 1, it is characterised in that this frequency synthesizer further includes:

One variable phase accumulation device, couples this trimmed agitator, in order to the periodicity of this radio frequency clock accumulative And a variable phase signal is provided according to this；And

One fixed phase integrating instrument, adds up a frequency instruction in order to respond each cycle of this frequency reference clock Character also provides the aggregate-value of this frequency instruction character according to this；

Wherein, this phase shifter changes this frequency reference in order to respond the aggregate-value of this frequency instruction character The phase place of clock, and this trimmed agitator in order to according to this numeral conversion output, this variable phase signal and The aggregate-value of this frequency instruction character and adjust the cycle of this radio frequency clock.

10. frequency synthesizer as claimed in claim 9, it is characterised in that this frequency synthesizer further includes:

One retimer, in order to retime to carry to this frequency reference clock at the transition of this radio frequency clock Reference clock when resetting for one；

Wherein, add up this frequency at this fixed phase integrating instrument transition in order to the reference clock when this resets to refer to Make character.

11. frequency synthesizers as claimed in claim 9, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, in order to responding the aggregate-value of this frequency instruction character and One auxiliary decimal error correction signal is provided；

Wherein, this trimmed agitator more adjusts this radio frequency clock according to this auxiliary decimal error correction signal Cycle.

12. frequency synthesizers as claimed in claim 1, it is characterised in that wherein this phase shifter changes The phase place of this frequency reference clock offer according to this translation reference clock, make one turn of this translation reference clock Time difference at state and between the previous transition of this radio frequency clock is less than a complete week of this radio frequency clock Phase.

13. frequency synthesizers as claimed in claim 1, it is characterised in that wherein this phase shifter is used for The phase place changing this frequency reference clock translates reference clock with offer one, and this time-to-digit converter is to work as Occur at this time figure conversion range with at the transition of this translation reference clock at the transition of this radio frequency clock Respond time at proximity, and do not send out at the transition of this translation reference clock at the transition of this radio frequency clock Then it is not responding to when life is at the proximity of this time figure conversion range.

14. frequency synthesizers as claimed in claim 1, it is characterised in that wherein this phase shifter in order to Respond the decimal part of the aggregate-value of a frequency instruction character and offset the phase place of this frequency reference clock.

15. 1 frequency synthesizers, it is characterised in that this frequency synthesizer comprises:

One agitator, in order to provide a variable clock；

One phase shifter, in order to provide a translation reference clock, makes the phase place and of this translation reference clock The phase one phase shift amount of frequency reference clock, wherein this phase shift amount makes this translation reference clock A transition at and the previous transition of this variable clock between a time difference less than of this variable clock Cycle；

One time-to-digit converter, couples this phase shifter, in order to quantify this time difference to provide one first Decimal error correction signal；And

One variable phase accumulation device, couples this agitator, in order to add up the periodicity of this variable clock to provide One variable phase signal；

Wherein, this agitator adjusts the cycle of this variable clock according to this variable phase signal.

16. frequency synthesizers as claimed in claim 15, it is characterised in that this frequency synthesizer further includes:

One fixed phase integrating instrument, for responding each cycle of this frequency reference clock with an accumulative frequency instruction Character, and a reference phase signal is provided according to this；

Wherein, this phase shifter is in order to respond this reference phase signal to set this phase shift amount, and this shakes Swing device and more adjust the cycle of this variable clock according to this reference phase signal.

17. frequency synthesizers as claimed in claim 16, it is characterised in that this frequency synthesizer further includes:

One translational controller, couples this phase shifter, provides one in order to respond this reference phase signal Two decimal error correction signals；

Wherein, this agitator is more in order to repair with this second decimal error according to this first decimal error correction signal Positive signal and adjust the cycle of this variable clock.

18. 1 frequency synthesizers, it is characterised in that this frequency synthesizer comprises:

One agitator, in order to provide a variable clock；

One time-to-digit converter, in order to quantify time difference between a translation reference clock and this variable clock also One first decimal error correction signal, the wherein phase place of this translation reference clock and a frequency reference are provided according to this The phase one phase shift amount of clock；One translational controller, in order to respond a frequency instruction character Aggregate-value and one second decimal error correction signal is provided；And

One variable phase accumulation device, couples this agitator, in order to the periodicity according to this of this variable clock accumulative One variable phase signal is provided；

Wherein this agitator is more in order to according to this first decimal error correction signal and this second decimal error correction The aggregate-value of signal, this variable phase signal and this frequency instruction character adjusts the cycle of this variable clock.

19. frequency synthesizers as claimed in claim 18, it is characterised in that this frequency synthesizer further includes:

One phase shifter, couples this frequency reference clock, in order to change the phase place of this frequency reference clock with This translation reference clock is provided.

20. frequency synthesizers as claimed in claim 18, it is characterised in that this frequency synthesizer further includes:

One fixed phase integrating instrument, adds up this frequency instruction in order to respond each cycle of this frequency reference clock Character, and the aggregate-value of this frequency instruction character is provided according to this.

21. 1 kinds of frequency combining methods, it is characterised in that this frequency combining method comprises:

Respond an agitator to adjust signal and produce a variable clock；

By the phase offset one phase shift amount of a frequency reference clock to obtain a translation reference clock；And

By the time difference digitized between this variable clock and this translation reference clock, this time difference digitized One scope is less than a cycle of this variable clock.

22. frequency combining methods as claimed in claim 21, it is characterised in that this time difference is this translation Time difference at reference clock one transition and between the previous transition of this variable clock.

23. frequency combining methods as claimed in claim 22, it is characterised in that this frequency combining method is more Comprise:

Adjust this phase shift amount, make this time difference be less than or equal at a transition of this frequency reference clock and be somebody's turn to do Time difference between the previous transition of variable clock.

24. frequency combining methods as claimed in claim 23, it is characterised in that this frequency combining method is more Comprise:

A frequency instruction character is added up to obtain this frequency instruction character according to each cycle of this frequency reference clock Aggregate-value；And

This phase shift amount is adjusted according to the decimal part of the aggregate-value of this frequency instruction character.

25. frequency combining methods as claimed in claim 24, it is characterised in that this frequency combining method is more Comprise:

One first decimal error correction signal is obtained according to this digitized；And

Adjust this agitator according to this first decimal error correction signal and adjust signal.

26. frequency combining methods as claimed in claim 25, it is characterised in that this frequency combining method is more Comprise:

One second decimal error correction signal is measured to obtain according to this phase shift；

More adjust this agitator according to this second decimal error correction signal and adjust signal.