CN103051304A - RC (resistance-capacitance) filter circuit with shorter establishing time delay - Google Patents
RC (resistance-capacitance) filter circuit with shorter establishing time delay Download PDFInfo
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- CN103051304A CN103051304A CN2012105488281A CN201210548828A CN103051304A CN 103051304 A CN103051304 A CN 103051304A CN 2012105488281 A CN2012105488281 A CN 2012105488281A CN 201210548828 A CN201210548828 A CN 201210548828A CN 103051304 A CN103051304 A CN 103051304A
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Abstract
The invention provides an RC (resistance-capacitance) filter circuit with shorter establishing time delay. The RC filter circuit comprises an RC filter (2), and an RC time delay reducing module Bst (3); in the process of establishing voltage on an output node Nout of the RC filter, one current not from a signal source is provided; when the difference between the output node and an input signal is less than a some given value, the current is cut off, and the stabilized value to the output signal node is not affected. The circuit has shorter establishing time delay.
Description
Technical field
The present invention relates to a kind of RC filter circuit with shorter foundation time-delay.The invention still further relates to various analog integrated circuit or various electronic device, or electronic unit.
Background technology
In circuit, filter has a wide range of applications, as shown in Figure 1 RC filter particularly, and simple in structure, range of application is very extensive.But because its build-in attribute, i.e. RC time-delay also can be introduced certain time-delay when forming filter action.Concrete, under the application conditions that filters step large-signal waveform, what circuit needed is, signal is when stable state, and filter is to the filtration of signal noise; And in the process of the foundation of step large-signal, this time-delay is not expected often.
In order to reduce this RC filtering delay-time of not expecting, existing technology mainly solves from the following aspect, but can have certain shortcoming:
1. reduce the time constant of RC filtering, this method can make filter cutoff frequency uprise, and the inhibitory action of HF noise signal is weakened;
2. when reducing the time constant of RC filtering, reduce the high frequency composition of input signal, but this proposes too high requirement to design, might lose the meaning of RC filter.
Summary of the invention
The problem to be solved in the present invention is existing RC filter long problem output settling time.
The time-delay of RC filter is because in the process that signal direct current composition is set up, because the inhibition of resistance R, the electric current of signal source can not very fast flowing on the output capacitance, or capacitor C is relatively excessive, needs to absorb more electric charge, just can reach required current potential.Therefore at the initial stage that signal is set up, with input signal as a reference, provide electric charge to output capacitance by other path, and when output potential and DC potential are very approaching, cut off this branch road, just well overcome this problem.Based on this, can obtain solution of the present invention.
The invention provides a kind of RC filter circuit with shorter foundation time-delay, as shown in Figure 2, comprising: RC filter (2), the RC time-delay reduces module Bst (3).Wherein RC filter (2) is by resistance R, and capacitor C is in series by node Nsout; The RC time-delay reduces module Bst (3), comprises at least two ports: input in and output out, and input in links to each other with node Nsin, and output out links to each other with node Nsout; Signal source sig accesses by Nsig, and as an example, the reference edge of signal source sig and capacitor C be totally one node Ngnd.
The circuit working process is as follows: the RC time-delay reduces module Bst (3), in the process of Voltage Establishment, provides one not to be the electric current that derives from signal source to it on RC filter output node Sout; When the difference of output node and input signal during less than a certain specified value, this electric current will be cut off, and can not affect the stationary value to the output signal node.
Above-mentioned Bst (3) module is used according to concrete, has at least one of following feature:
A) when the absolute value of difference between the voltage of out and in during greater than a certain set point, out will have very low impedance, namely load will be equivalent to a voltage source, and deviation excessive between the voltage of out and the in is diminished; When the absolute value of difference between the voltage of out and in during less than this set point, out will have very high impedance, not have or only have minimum current loading effect.
B) when difference between the voltage of out and in greater than a certain setting on the occasion of the time, out will have very low impedance, namely load will be equivalent to a voltage source, and deviation excessive between the voltage of out and the in is diminished; When difference between the voltage of out and in less than this setting on the occasion of the time, out will have very high impedance, not have or only have minimum current loading effect.
C) when difference between the voltage of out and in during less than a certain setting negative value, out will have very low impedance, namely load will be equivalent to a voltage source, and deviation excessive between the voltage of out and the in is diminished; When difference between the voltage of out and in during greater than the negative value of this setting, out will have very high impedance, not have or only have minimum current loading effect.
Module Bst (3) may have multiple way of realization, can but be not must following a kind of form
A) pmos, its grid meet the input in of Bst, and source electrode meets the output out of Bst, and drain electrode connects the only Low ESR node of Absorption Current;
B) nmos, its grid meet the input in of Bst, and source electrode meets the output out of Bst, and drain electrode connects the only Low ESR node of output current;
C) other satisfies device or the circuit module of aforementioned Bst feature.
A kind of RC filter circuit (1) with shorter foundation time-delay disclosed by the invention has multiple application form:
A) can but must not be to occur with the form of cascade, the form of cascade herein refers to the input that rear one-level is received in the output of a plurality of circuit (1) previous stage;
C) can but must not be to occur with the form of parallel connection, form in parallel refers to that a plurality of circuit (1) input receives same node herein.
C) can but must not be take aforementioned (A) (B) application form use as the mixing of unit
Compared with prior art, above-mentioned disclosed RC filter circuit with shorter foundation time-delay has the following advantages: even the RC time constant is very large, can guarantee also that output node reaches in a short period of time with steady-state value differs very little value, even can reach and satisfy the required required precision of circuit performance.
Circuit disclosed by the invention has characteristics to be, the electronic device that adopts can realize with kinds of processes, such as CMOS, and BiCOMS, SOI.
Description of drawings
Fig. 1 is RC filter circuit commonly used at present;
Fig. 2 is a kind of schematic diagram with RC filter circuit of shorter foundation time-delay disclosed by the invention;
Fig. 3 is the embodiment that employing NMOS disclosed by the invention realizes the Bst module;
Fig. 4 is the embodiment that employing PMOS disclosed by the invention realizes the Bst module;
Fig. 5 is a kind of embodiment that employing amplifier control NMOS disclosed by the invention realizes the Bst module;
Embodiment
Fig. 3 has provided the embodiment that employing NMOS disclosed by the invention realizes the Bst module: wherein RC filter (2) is by resistance R, and capacitor C is in series by node Nsout; The RC time-delay reduces module Bst (3) and is realized by NMOS, and grid links to each other with node Nsin, and source links to each other with node Nsout, and drain terminal links to each other with power junctions Nvdda; Signal source sig accesses by Nsin, and as an example, the reference edge of signal source sig and capacitor C be totally one node Ngnd.
Fig. 4 has provided the embodiment that employing PMOS disclosed by the invention realizes the Bst module; Wherein RC filter (2) is by resistance R, and capacitor C is in series by node Nsout; The RC time-delay reduces module Bst (3) and is realized by PMOS, and grid links to each other with node Nsin, and source links to each other with node Nsout, and drain terminal links to each other with power supply ground node Ngnd; Signal source sig accesses by Nsin, and as an example, the reference edge of signal source sig and capacitor C be totally one node vdda.
Fig. 5 has provided the embodiment that there is the amplifier realization Bst module of input deviation in employing disclosed by the invention; Wherein RC filtering (2) is by resistance R, and capacitor C is in series by node Nsout; The RC time-delay reduces module Bst (3) is had the NMOS of the amplifier control of default deviation to realize by a grid by an input, so that the judgment threshold of starting current when cutting off decided by the input deviation voltage of amplifier opamp, wherein the input deviation voltage of amplifier opamp represents with voltage source Vos, the negative pole of amplifier meets Nsout, and anodal Vos by the expression deviation voltage is concatenated into node Nsin; The NMOS drain terminal links to each other with power supply output node Nvdda, and source links to each other with Nsout; Signal source sig accesses by Nsin, and as an example, the reference edge of signal source sig and capacitor C be totally one node Ngnd.
Claims (10)
1. the RC filter circuit (1) with shorter foundation time-delay is characterized in that, comprises at least:
RC filter (2)
The RC time-delay reduces module Bst (3).
2. RC filter circuit as claimed in claim 1 (2) is characterized in that, comprises at least the resistance R by output node Nsout series connection, capacitor C; The non-Nsout end of resistance R is input Nsin, and the non-Nsout end of capacitor C will link to each other with a certain low impedance points, and this low-resistance point can earth point, also can be other low-resistance points.
3. RC time-delay as claimed in claim 1 reduces module Bst (3), it is characterized in that, comprises at least two ports:
Input in and output out, input in links to each other with node Nsin, and input out links to each other with node Nsout.
4. time-delay reduces the input in of module Bst (3) as claimed in claim 3, it is characterized in that, the in node has high impedance, namely to the voltage signal of access not or have a very little current loading effect.
5. delaying time as claimed in claim 3 reduces the output out of module Bst (3), it is characterized in that according to concrete application, having at least one of following feature:
A) when the absolute value of difference between the voltage of out and in during greater than a certain set point, out will have very low impedance, namely load will be equivalent to a voltage source, and deviation excessive between the voltage of out and the in is diminished; When the absolute value of difference between the voltage of out and in during less than this set point, out will have very high impedance, not have or only have minimum current loading effect.
B) when difference between the voltage of out and in greater than a certain setting on the occasion of the time, out will have very low impedance, namely load will be equivalent to a voltage source, and deviation excessive between the voltage of out and the in is diminished; When difference between the voltage of out and in less than this setting on the occasion of the time, out will have very high impedance, not have or only have minimum current loading effect.
C) when difference between the voltage of out and in during less than a certain setting negative value, out will have very low impedance, namely load will be equivalent to a voltage source, and deviation excessive between the voltage of out and the in is diminished; When difference between the voltage of out and in during greater than the negative value of this setting, out will have very high impedance, not have or only have minimum current loading effect.
As claimed in claim 3 time-delay reduce module Bst (3) can but be not must following a kind of form
A) pmos, its grid meet the input in of Bst, and source electrode meets the output out of Bst, and drain electrode connects the only Low ESR node of Absorption Current;
B) nmos, its grid meet the input in of Bst, and source electrode meets the output out of Bst, and drain electrode connects the only Low ESR node of output current;
C) other satisfies device or the circuit module of aforementioned claim 1 to 5 feature.
7. integrated circuit or electronic device that comprises the described circuit of claim 1 (1), electronic unit, it is characterized in that, comprise at least one or a plurality of circuit claimed in claim 1 (1), circuit (1) can but must not be to occur with the form of cascade, the form of cascade herein refers to the input that rear one-level is received in the output of a plurality of circuit (1) previous stage.
8. integrated circuit or electronic device that comprises the described circuit of claim 1 (1), electronic unit, it is characterized in that, comprise at least one or a plurality of circuit claimed in claim 1 (1) of wanting, circuit (1) can but must not be to occur with the form of parallel connection, form in parallel refers to that a plurality of circuit (1) input receives same node herein.
9. integrated circuit or electronic device that comprises the described circuit of claim 1 (1), electronic unit is characterized in that, comprises simultaneously claim 7 or 8 described integrated circuit or electronic devices, electronic unit.
10. any described circuit as in the aforementioned claim is characterized in that the electronic device that adopts can realize with kinds of processes, such as CMOS, and BiCOMS, SOI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105488281A CN103051304A (en) | 2012-12-13 | 2012-12-13 | RC (resistance-capacitance) filter circuit with shorter establishing time delay |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105488281A CN103051304A (en) | 2012-12-13 | 2012-12-13 | RC (resistance-capacitance) filter circuit with shorter establishing time delay |
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| CN103051304A true CN103051304A (en) | 2013-04-17 |
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| CN2012105488281A Pending CN103051304A (en) | 2012-12-13 | 2012-12-13 | RC (resistance-capacitance) filter circuit with shorter establishing time delay |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425822A (en) * | 2017-05-09 | 2017-12-01 | 广州慧智微电子有限公司 | A kind of filter circuit and method |
| CN109547181A (en) * | 2018-10-08 | 2019-03-29 | 华中科技大学 | A kind of short filter, single-carrier system and multicarrier system |
| CN112564664A (en) * | 2020-12-03 | 2021-03-26 | 成都海光微电子技术有限公司 | Filter circuit, integrated circuit and method for shortening filter response time |
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| US4050023A (en) * | 1976-03-30 | 1977-09-20 | Edgar Albert D | General purpose pole-zero single amplifier active filter |
| US4441066A (en) * | 1982-09-28 | 1984-04-03 | Mcgraw-Edison Company | Battery charger failure alarm circuit |
| CN102064764A (en) * | 2010-12-14 | 2011-05-18 | 西安工业大学 | Method and circuit for reducing starting time of microcomputer temperature compensation quartz crystal oscillator |
| CN302064764S (en) * | 2012-05-30 | 2012-09-05 | 岑万宝 | Plush toy (bear) |
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2012
- 2012-12-13 CN CN2012105488281A patent/CN103051304A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3652137A (en) * | 1969-03-01 | 1972-03-28 | Itt | Antiskid control circuit |
| US4050023A (en) * | 1976-03-30 | 1977-09-20 | Edgar Albert D | General purpose pole-zero single amplifier active filter |
| US4441066A (en) * | 1982-09-28 | 1984-04-03 | Mcgraw-Edison Company | Battery charger failure alarm circuit |
| CN102064764A (en) * | 2010-12-14 | 2011-05-18 | 西安工业大学 | Method and circuit for reducing starting time of microcomputer temperature compensation quartz crystal oscillator |
| CN302064764S (en) * | 2012-05-30 | 2012-09-05 | 岑万宝 | Plush toy (bear) |
Non-Patent Citations (1)
| Title |
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| 曾祥富: "《电工技术基础与技能-电类专业通用》", 30 June 2010, 科学出版社, article "电工技术基础与技能-电类专业通用", pages: 88-90 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425822A (en) * | 2017-05-09 | 2017-12-01 | 广州慧智微电子有限公司 | A kind of filter circuit and method |
| CN107425822B (en) * | 2017-05-09 | 2024-03-26 | 广州慧智微电子股份有限公司 | Filtering circuit and method |
| CN109547181A (en) * | 2018-10-08 | 2019-03-29 | 华中科技大学 | A kind of short filter, single-carrier system and multicarrier system |
| CN109547181B (en) * | 2018-10-08 | 2020-02-14 | 华中科技大学 | Short filter, single carrier system and multi-carrier system |
| CN112564664A (en) * | 2020-12-03 | 2021-03-26 | 成都海光微电子技术有限公司 | Filter circuit, integrated circuit and method for shortening filter response time |
| CN112564664B (en) * | 2020-12-03 | 2024-04-05 | 成都海光微电子技术有限公司 | Filter circuit, integrated circuit and method for shortening filter response time |
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Application publication date: 20130417 |