CN103050390A - Process for adjusting contact resistance value - Google Patents
Process for adjusting contact resistance value Download PDFInfo
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- CN103050390A CN103050390A CN2012104940178A CN201210494017A CN103050390A CN 103050390 A CN103050390 A CN 103050390A CN 2012104940178 A CN2012104940178 A CN 2012104940178A CN 201210494017 A CN201210494017 A CN 201210494017A CN 103050390 A CN103050390 A CN 103050390A
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- interlayer dielectric
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Abstract
The invention relates to the field of manufacturing semiconductors, in particular to a process for adjusting a contact resistance value. With the adoption of the process for adjusting the contact resistance value, a tungsten/copper bolt is formed by utilizing a tungsten etchback process; and the proportion of a tungsten layer and a copper layer formed in the tungsten/copper bolt is controlled through adjusting the etchback process time, so that the purpose of controlling the size of contact resistance value is achieved, and therefore the electrical properties of semiconductor devices and the yield of products can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of technique of regulating the contact resistance resistance.
Background technology
At present, in the semi-conductive standard processing procedure, the metal ohmic contact processing step partly for the COMS device mainly adopts chemical mechanical milling tech (Chemical Mechanical Polishing, be called for short CMP) tungsten in the through hole is carried out flatening process, and then it is tactile to form the tungsten bolt.
Fig. 1-6 is for forming the conventional process schematic flow sheet that the tungsten bolt touches in the background technology of the present invention; Shown in Fig. 1-6, at first, provide one to have the Semiconductor substrate structure 1 of source class (S), drain electrode (D) and grid (G), deposition interlayer dielectric layer (Inter Layer Dielectrics, abbreviation ILD) 2 covers the upper surface of Semiconductor substrate structures 1, utilize photoetching (Photo), etching (Etch) technique, part is removed interlayer dielectric layer 2 to the upper surface of source class (S), drain electrode (D) and grid (G), to form a plurality of through holes 3 in the remaining interlayer dielectric layer 21 after etching; Secondly, behind the bottom and sidewall thereof of the upper surface of remaining interlayer dielectric layer 21 and through hole 3, deposition tungsten layer 5 is full of the upper surface of through hole 3 and covering barrier layer 4 after the deposited barrier layer 4 covering etchings; At last, adopt CMP technique that tungsten layer 5 is carried out planarization, remove the upper surface of tungsten layer 5 and barrier layer 4 remaining interlayer dielectric layer 21 to the etching with part, so that remaining tungsten layer 51 and remaining barrier layer 41 all are arranged in through hole 3, and then form tungsten bolt contact hole.
Because large (the 0.053 Ω mm of the resistivity of tungsten
2/ m), cause contact resistance (tungsten bolt) larger, cause the semiconductor device electric property of preparation relatively poor, reduced the yield of product.
Summary of the invention
Problem for above-mentioned existence, the present invention has disclosed a kind of technique of regulating the contact resistance resistance, mainly utilize the tungsten etch-back technics to form tungsten/copper bolt, and control the ratio of tungsten layer and copper layer in the tungsten of formation/copper bolt by regulating the etch-back technics time, reaching the purpose of control contact resistance resistance university, and then improve the electric property of semiconductor device and the yield of product.
The objective of the invention is to be achieved through the following technical solutions:
A kind of technique of regulating the contact resistance resistance wherein, may further comprise the steps:
Deposit interlayer dielectric layer in a upper surface that the Semiconductor substrate structure of the active drain-gate utmost point is set;
Adopt photoetching, etching technics to remove the described interlayer dielectric layer of part, form and run through the residue interlayer dielectric layer to a plurality of contact through holes of described Semiconductor substrate body structure surface;
Deposited barrier layer covers bottom and the sidewall thereof of described residue interlayer dielectric layer and each described contact through hole;
The deposition tungsten layer is full of each described contact through hole and covers the upper surface of described residue interlayer dielectric layer;
Eat-back described tungsten layer, remove the tungsten layer that is arranged in described residue interlayer dielectric layer top and the described contact through hole of part;
Copper layer covers the upper surface on described barrier layer, and is full of described contact through hole;
Adopt flatening process to remove unnecessary copper layer and barrier layer, form tungsten/copper bolt;
Wherein, control the degree of depth of eat-backing tungsten layer in the described contact through hole by the control etch-back technics time.
The technique of above-mentioned adjusting contact resistance resistance wherein, adopts CMP technique to remove copper layer and barrier layer to described residue interlayer dielectric layer.
The technique of above-mentioned adjusting contact resistance resistance, wherein, the diameter of described contact through hole is 80-200nm.
The technique of above-mentioned adjusting contact resistance resistance, wherein, the material on described barrier layer is Ti/TiN.
The technique of above-mentioned adjusting contact resistance resistance, wherein, the thickness on described barrier layer is 10-30nm.
In sum, a kind of technique of regulating the contact resistance resistance of the present invention, mainly utilize the tungsten etch-back technics to form tungsten/copper bolt, and control the ratio of tungsten layer and copper layer in the tungsten of formation/copper bolt by regulating the etch-back technics time, reaching the purpose of control contact resistance resistance university, and then improve the electric property of semiconductor device and the yield of product.
Description of drawings
Fig. 1-6 is for forming the conventional process schematic flow sheet that the tungsten bolt touches in the background technology of the present invention;
Fig. 7-14 is for forming the process flow diagram of tungsten/copper stud structure among the present invention;
Figure 15 is the schematic diagram that concerns between device contacts resistance and the tungsten/copper bolt ratio, and transverse axis represents the ratio of copper and tungsten in tungsten/copper bolt, and the longitudinal axis represents the resistance size (normalization) of device contact resistance.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described:
Fig. 7-14 is for forming the process flow diagram of tungsten/copper stud structure among the present invention; At first, shown in Fig. 7-8, have the Semiconductor substrate structure 1 of source class (S), drain electrode (D) and grid (G) one, deposition interlayer dielectric layer (Inter Layer Dielectrics is called for short ILD) 2 covers the upper surface of Semiconductor substrate structure 1; Secondly, the spin coating photoresist covers the upper surface of interlayer dielectric layer 2, after exposure, the development, remove unnecessary photoresist, formation has the photoresistance of through-hole pattern, and take this photoresistance as mask etching interlayer dielectric layer 2 to the upper surface (upper surface of source, leakage, grid) of Semiconductor substrate structure 1, form the structure with a plurality of contact through holes 3 as shown in Figure 9 behind the removal photoresistance, and this contact through hole 3 runs through residue interlayer dielectric layer 21 to the upper surface of Semiconductor substrate structure 1; Wherein, the diameter of contact through hole 3 is 80-200nm, and is equivalent such as 80nm, 100nm, 150nm or 200nm.
As shown in figure 10, the deposition material is after the barrier layer 4 of Ti/TiN covers the bottom and sidewall thereof of the upper surface of remaining interlayer dielectric layer 21 after the etchings and all contact through holes 3, as shown in figure 11, continue the upper surface that deposition tungsten layer 5 is full of contact through hole 3 and covering barrier layer 4; Wherein, the thickness on barrier layer 4 is 10-30nm, and is equivalent such as 10nm, 20nm or 30nm.
Adopt etch-back technics (Etch Back), be arranged in the tungsten layer 5 of residue interlayer dielectric layer 21 upper surfaces and part contact through hole 3 with removal, because barrier layer 4 is higher with respect to the etching selection of tungsten layer 5 in etch-back technics, so barrier layer 4 is kept in etch-back technics, and then formation structure as shown in figure 12; Preferably, the thickness of remaining tungsten layer 52 is 2/3rds of contact through hole 3 degree of depth, namely is formed with the tungsten layer hole of 1/3rd degree of depth of contact through hole 3; Wherein, can by the time of control etch-back technics, control the degree of depth of the tungsten layer 5 that eat-backs in the contact through hole 3.
As shown in figure 13, adopt the standard copper depositing operation, the upper surface of copper layer 6 covering barrier layer 4 also is full of the tungsten layer hole, and adopts CMP technique copper layer 6 and barrier layer 4 to carry out flatening process to the upper surface that remains interlayer dielectric layer 21, forms structure as shown in figure 14; As shown in figure 14, the upper surface of Semiconductor substrate structure 1 is coated with residue interlayer dielectric layer 21, a plurality of contact through holes 3 are arranged in this residue interlayer dielectric layer 21, this contact through hole 3 runs through above-mentioned residue interlayer dielectric layer 21 to the upper surface of Semiconductor substrate structure 1, remaining barrier layer 42 covers bottom and the sidewall thereof of contact through hole 3, residue tungsten layer 52 is full of the bottom of contact through hole 3, residual copper layer 61 covers the upper surface of residue tungsten layers 52 and is full of the top of contact through hole 3, namely remains tungsten layer 52 and residual copper layer 61 has formed tungsten/copper stud structure jointly.
Because tungsten resistivity is 0.053 Ω mm
2/ m, the resistivity of copper then is 0.0185 Ω mm
2/ m, namely the formed tungsten/copper stud structure of the present embodiment has reduced by 27.7% with respect to the resistance of traditional pure tungsten stud structure, thereby greatly reduces contact resistance.
Figure 15 is the schematic diagram that concerns between device contacts resistance and the tungsten/copper bolt ratio, and transverse axis represents the ratio of copper and tungsten in tungsten/copper bolt, and the longitudinal axis represents the resistance size (normalization) of device contact resistance; The device contacts resistance is 1 when preseting the pure tungsten bolt, and namely the ratio of copper (Cu)/tungsten (W) is 0, and the device contacts resistance is 1; As shown in Figure 15, increase along with Cu/W ratio, be that the proportion of Cu is more in the contact resistance, the resistance of device contacts resistance is just less, it is 0 o'clock from Cu/W, the resistance of device contacts resistance is 1, it is 4/4 o'clock to Cu/W, the resistance of device contacts resistance will be 0.67, so ratio that as can be known can be by Cu in the control contact resistance is the size of control device contact resistance resistance effectively, namely the etch-back technics by the control tungsten layer such as etch period etc. are controlled the ratio of copper in tungsten/copper bolt, and then reach the control contact resistance, even the size of device contacts resistance, with the electric property of effective raising semiconductor device.
In sum, owing to having adopted technique scheme, the embodiment of the invention is regulated the technique of contact resistance resistance, mainly utilize the tungsten etch-back technics to form tungsten/copper bolt, and control the ratio of tungsten layer and copper layer in the tungsten of formation/copper bolt by regulating the etch-back technics time, reaching the purpose of control contact resistance resistance university, and then improve the electric property of semiconductor device and the yield of product.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (5)
1. a technique of regulating the contact resistance resistance is characterized in that, may further comprise the steps:
Deposit interlayer dielectric layer in a upper surface that the Semiconductor substrate structure of the active drain-gate utmost point is set;
Adopt photoetching, etching technics to remove the described interlayer dielectric layer of part, form and run through the residue interlayer dielectric layer to a plurality of contact through holes of described Semiconductor substrate body structure surface;
Deposited barrier layer covers bottom and the sidewall thereof of described residue interlayer dielectric layer and each described contact through hole;
The deposition tungsten layer is full of each described contact through hole and covers the upper surface of described residue interlayer dielectric layer;
Eat-back described tungsten layer, remove the tungsten layer that is arranged in described residue interlayer dielectric layer top and the described contact through hole of part;
Copper layer covers the upper surface on described barrier layer, and is full of described contact through hole;
Adopt flatening process to remove unnecessary copper layer and barrier layer, form tungsten/copper bolt;
Wherein, control the degree of depth of eat-backing tungsten layer in the described contact through hole by the control etch-back technics time.
2. the technique of adjusting contact resistance resistance according to claim 1 is characterized in that, adopts CMP technique to remove copper layer and barrier layer to described residue interlayer dielectric layer.
3. the technique of adjusting contact resistance resistance according to claim 1 is characterized in that, the diameter of described contact through hole is 80-200nm.
4. the technique of adjusting contact resistance resistance according to claim 1 is characterized in that, the material on described barrier layer is Ti/TiN.
5. the technique of adjusting contact resistance resistance according to claim 1 is characterized in that, the thickness on described barrier layer is 10-30nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104940178A CN103050390A (en) | 2012-11-28 | 2012-11-28 | Process for adjusting contact resistance value |
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| CN2012104940178A CN103050390A (en) | 2012-11-28 | 2012-11-28 | Process for adjusting contact resistance value |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020182856A1 (en) * | 2001-06-01 | 2002-12-05 | Ching-Yu Chang | Method for forming a contact window with low resistance |
| CN1485887A (en) * | 2002-09-25 | 2004-03-31 | 茂德科技股份有限公司 | Method for forming contact hole |
| EP0841690B1 (en) * | 1996-11-12 | 2006-03-01 | Samsung Electronics Co., Ltd. | Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method |
| CN101068018A (en) * | 2006-05-05 | 2007-11-07 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| CN102437098A (en) * | 2011-09-08 | 2012-05-02 | 上海华力微电子有限公司 | Forming method of contact hole for reducing contact resistance |
-
2012
- 2012-11-28 CN CN2012104940178A patent/CN103050390A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0841690B1 (en) * | 1996-11-12 | 2006-03-01 | Samsung Electronics Co., Ltd. | Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method |
| US20020182856A1 (en) * | 2001-06-01 | 2002-12-05 | Ching-Yu Chang | Method for forming a contact window with low resistance |
| CN1485887A (en) * | 2002-09-25 | 2004-03-31 | 茂德科技股份有限公司 | Method for forming contact hole |
| CN101068018A (en) * | 2006-05-05 | 2007-11-07 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| CN102437098A (en) * | 2011-09-08 | 2012-05-02 | 上海华力微电子有限公司 | Forming method of contact hole for reducing contact resistance |
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Application publication date: 20130417 |