CN103050146B - High duty ratio DDR2 digital delay chain circuit - Google Patents

High duty ratio DDR2 digital delay chain circuit Download PDF

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CN103050146B
CN103050146B CN201310010030.6A CN201310010030A CN103050146B CN 103050146 B CN103050146 B CN 103050146B CN 201310010030 A CN201310010030 A CN 201310010030A CN 103050146 B CN103050146 B CN 103050146B
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digital delay
port
stages
clock
selector
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CN103050146A (en
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吕新浩
孙翼
高鹏
马涛
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KUNSHAN HUINING ELECTRIC CO Ltd
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KUNSHAN HUINING ELECTRIC CO Ltd
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Abstract

The invention discloses a kind of high duty ratio DDR2 digital delay chain circuit, comprise digital delay elements, write operation clock digital delay chain and read-write operation DQS digital delay chain.Digital delay elements is made up of clocked inverter and clock selector, write operation clock digital delay chain and read-write operation DQS digital delay chain in series by digital delay elements.The present invention adopts full-digital circuit to realize, and not at dependence chip production process, can realize high duty ratio DDR2 and write clock and DQS signal, improve DDR2 stability and frequency of operation.

Description

High duty ratio DDR2 digital delay chain circuit
Technical field
The present invention relates to high duty ratio DDR2 digital delay chain circuit, belong to high speed DDR, DDR2, DDR3 Design of Digital Circuit field.
Background technology
Along with the development of integrated circuit and the continuous renewal of technology, the clock frequency of chip improves constantly, the continuous increase of chip data handling capacity, the dutycycle balance of synchronizing clock signals is most important for guarantee circuit sequence performance, make when current design chips, DDR2 needs more accurate clock accuracy and clock frequency faster.
Conventional digital delay chain circuits generally adopts numerical model analysis method for designing; under being confined to certain special process; flexible design degree is not high; particularly in Deep submicron chip technique, there is temperature Inversion Problem; the delayed latch circuit variation obvious effect of traditional numerical model analysis, there is larger change, if do not meet the timing requirements of DDR2 specification in the DQS signal obtained and write operation clock; in DDR2 read-write process, the situation of reading and writing data mistake may be produced.
Existing digital delay elements one is made up of accurate adjustment digital delay elements and coarse adjustment delay cell, and coarse adjustment unit have employed Sheffer stroke gate structure, and accurate adjustment unit have employed rejection gate structure, and another kind is by impact damper, form with door and selector switch.Because technology library device cell itself exists rising edge and negative edge deviation, existing digital delay elements output clock rising edge and negative edge have very large deviation, and this deviation is constantly accumulated along with the increase of cascade progression, have a strong impact on the dutycycle performance of clock signal, particularly in high speed DDR2 system, the requirement of DDR2 reservoir designs may not be met between DQS, DQ and DDR2 storer major clock that existing digital delay locked loop circuit produces, cause reading and writing data mistake, system cisco unity malfunction.
Summary of the invention
Technical matters: the present invention seeks to solve the technical matters mentioned in above-mentioned background, a kind of high duty ratio DDR2 digital delay chain circuit is provided, solves existing DDR2 digital delay chain clock duty cycle problem, improve the frequency of operation of DDR2.
Technical scheme: the object of the invention is to, for the clock duty cycle problem that existing DDR2 digital delay chain circuit produces, the problem that existing digital delay chain applying frequency is lower, proposes a kind of high duty ratio DDR2 digital delay chain circuit.This circuit builds digital delay chain based on the digital delay elements improved, improve clock duty cycle and system operating frequency, the solution proposed is digital design, not only can improve clock duty cycle and the frequency of operation of DDR2, reduce circuit complexity, and the design of this circuit is not at dependence special process.
The present invention includes digital delay elements, clock lock digital delay chain, write operation clock digital delay chain, write operation DQS digital delay chain and read operation DQS digital delay chain.
Described digital delay elements is by postponing minimum clocked inverter and the less clock selector of rising edge negative edge deviation is composed in series.The input clock of digital delay elements enters the port B of digital delay elements clock selector, and the output signal of next stage digital delay elements, after the clocked inverter of digital delay elements at the corresponding levels, is connected to clock selector port A at the corresponding levels; When clock selector selects signal to be 1, digital delay elements output clock selector switch port B signal at the corresponding levels, when the selection signal of digital delay elements at the corresponding levels is 0, digital delay elements output clock selector switch port A data at the corresponding levels are to upper level digital delay elements.
Described clock lock digital delay chain, adjusts digital delay elements by the digital delay elements that N level is identical with the phase place possessing digital delay elements same circuits structure and is composed in series.The input end of clock lock digital delay chain is the system clock of DDR2, adopts the digital delay elements quantity configuration register one_hot_clock_lock_delaycell_num of one-hot encoding to connect the selection sel port of the clock selector of digital delay elements.The 0th of one_hot_clock_lock_delaycell_num is connected to the selection sel port of the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to the 2nd stages of digital delay cell clock selector, by that analogy, N-1 position is connected to the selection sel port of N stages of digital delay cell clock selector, DDR2 system clock is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.The output of the 1st stages of digital delay cell is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when the binary value that one_hot_clock_lock_delaycell_num is corresponding is odd number, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described clock lock digital delay chain, when from M stages of digital delay units delay, namely one_hot_clock_lock_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell outputs to phase place adjustment digital delay elements, when the binary value that one_hot_clock_lock_delaycell_num is corresponding is odd number, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.When the retardation of M stages of digital delay cell is less than a DDR2 system clock cycle, digital delay elements quantity configuration register one_hot_clock_lock_delaycell_num increases, cumulative until a clock period of locking with this; Otherwise then reduce the quantity of digital delay elements, successively decrease with this until lock a clock period.
Described clock lock digital delay chain, is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
Described clock lock digital delay chain, is characterized in that, when M is even number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of clock lock digital chain and selector switch A port to exporting C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts clock lock digital chain clock selector B port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that clock lock digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
Described write operation clock digital delay chain, is characterized in that, adjusts digital delay elements be composed in series by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure.The input end of write operation clock digital delay chain receives the system clock of DDR2, one_hot_write_clk_delaycell_num writes clock to postpone digital delay elements quantity corresponding to 3/4 phase place relative to DDR2 system clock, the scale-of-two lowest order write_clk_delaycell_num_odd of its correspondence is connected to phase place adjustment digital delay elements, one_hot_write_clk_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_write_clk_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except first order digital delay elements clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Clock signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write_clk_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described write operation clock digital delay chain, it is characterized in that, when from M stages of digital delay units delay, namely one_hot_write_clk_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the high duty ratio write operation clock postponing 3/4 phase place relative to DDR2 system clock.
Described write operation clock digital delay chain, is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
Described write operation clock digital delay chain, is characterized in that, when M is even number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Write operation clock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of write operation clock digital chain and selector switch A port to exporting C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay elements M-1 stages of digital delay cell of having cancelled out each other produces clock selector A port to the rising edge of selector switch C port and negative edge deviation; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Write operation clock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts write operation clock digital chain clock selector B port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that write operation clock digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
Described write operation DQS digital delay chain, is characterized in that, adjusts digital delay elements be composed in series by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure.The input end of write operation DQS digital delay chain receives the system clock of DDR2, one_hot_write_dqs_delaycell_num writes clock to postpone digital delay elements quantity corresponding to 1 phase place relative to DDR2 system clock, the binary value lowest order write_dqs_delaycell_num_odd of its correspondence is connected to phase place adjustment digital delay elements, one_hot_write_dqs_delaycell_num is connected to the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_write_dqs_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Write operation DQS signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write_dqs_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described write operation DQS digital delay chain, it is characterized in that, when from M stages of digital delay units delay, namely one_hot_write_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the high duty ratio write operation DQS relative to DDR2 system clock 1 phase delay.
Described write operation DQS digital delay chain, is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
Described write operation DQS digital delay chain, is characterized in that, when M is even number, digital delay elements has cancelled out each other M-2 stages of digital delay cell clocked inverter and selector switch A port to exporting the rising edge and negative edge deviation that C port produces; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Write operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of write operation DQS digital chain and selector switch A port to exporting C port rising edge and negative edge deviation.After phase place adjustment, the write operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay elements has cancelled out each other M-1 stages of digital delay cell clocked inverter and selector switch A port to exporting the rising edge and negative edge deviation that C port produces; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Write operation DQS digital delay chain first order digital delay elements outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts write operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that write operation DQS digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
Described read operation DQS digital delay chain, is characterized in that, adjusts digital delay elements be composed in series by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure.The input end of read operation DQS digital delay chain receives the system clock of DDR2, one_hot_read_dqs_delaycell_num writes clock to postpone digital delay elements quantity corresponding to 1 phase place relative to DDR2 system clock, the binary value lowest order one_hot_read_dqs_delaycell_num of its correspondence is as the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_read_dqs_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Write operation DQS signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when read_dqs_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described read operation DQS digital delay chain, it is characterized in that, when from M stages of digital delay units delay, namely one_hot_read_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the high duty ratio read operation DQS relative to DDR2 system clock 1/4 phase delay.
Described read operation DQS digital delay chain, is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
Described read operation DQS digital delay chain, is characterized in that, when M is even number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of read operation DQS digital chain and selector switch A port to exporting C port rising edge and negative edge deviation.After phase place adjustment, the read operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts read operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that read operation DQS digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
Beneficial effect: compared with existing technical scheme, the invention has the advantages that:
1. relative to analog form, digital delay chain circuit described in the present invention be not confined to certain certain chip design technology, not being limited to technique-temperature-voltage impact, there is technique-temperature-voltage self-adaptative adjustment effect and definitely realize advantage flexibly.
2. digital delay chain element of the present invention adopts a clocked inverter and a clock selector to be composed in series, the minimum clocked inverter of delay and clock selector is selected to be composed in series basic digital delay elements, improve the precision of digital delay chain, the frequency of operation of system can be greatly improved.
3. because device itself also exists rising edge and negative edge delay distortion, if directly adopt traditional digital delay elements circuit, each impact damper, with door, Sheffer stroke gate, the rising edge of selector switch and negative edge delay distortion after N level is accumulated, the duty cycle deviations of output clock strengthens, and may cause output clock cisco unity malfunction.Digital delay chain is composed in series by several identical digital delay elements, and the clock after digital delay chain postpones, by phase place adjustment digital delay elements adjustment phase place, it is advantageous that:
A. when clock lock digital delay chain locks that clock period, numeral delay cell quantity clock_locked_delaycell_num was even number, duty cycle deviations is only the deviation of 1 clock selector A port to C port, when clock_locked_delaycell_num is odd number, duty cycle deviations is 0, at equal process conditions, clock duty cycle is close to 1:1.
B. when to lock binary value corresponding to 3/4 DDR2 system clock cycle digital delay elements quantity be even number to write operation clock digital delay chain input signal one_hot_write_clk_delaycell_num, duty cycle deviations is only the deviation of 1 clock selector A port to C port, during for odd number, duty cycle deviations is 0.At equal process conditions, clock duty cycle is close to 1:1.
C. when to lock binary value corresponding to 1 DDR2 system clock cycle digital delay elements quantity be even number to write operation DQS digital delay chain input signal one_hot_write_dqs_delaycell_num, duty cycle deviations is only the deviation of 1 clock selector A port to C port, during for odd number, duty cycle deviations is 0.At equal process conditions, clock duty cycle is close to 1:1.
D. when to lock binary value corresponding to 1/4 DDR2 system clock cycle digital delay elements quantity be even number to read operation DQS digital delay chain input signal one_hot_read_dqs_delaycell_num, duty cycle deviations is only the deviation of 1 clock selector A port to C port, during for odd number, duty cycle deviations is 0.At equal process conditions, clock duty cycle is close to 1:1.
Accompanying drawing explanation
Fig. 1 is digital delay elements of the present invention.
Fig. 2 is clock lock digital delay chain circuit of the present invention.
Fig. 3 is write operation clock of the present invention numeral delay chain circuits.
Fig. 4 is write operation DQS digital delay chain circuit of the present invention.
Fig. 5 is read operation DQS digital delay chain circuit of the present invention.
Embodiment
Below with reference to the drawings and specific embodiments, the present invention is described in detail.Herein with 128 stages of digital delay chains, DDR2 system clock cycle is 3.75ns, frequency is 266Mhz, DDR2 storer is 533Mhz, DDR2 system configurable phase offset register bit wide is 8, and every stages of digital delay units delay amount is 0.1ns, clock lock digital delay chain initial delay progression is 11, as embodiment, described embodiment is only a kind of embodiment of the present invention, is not whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The invention process discloses a kind of high duty ratio DDR2 digital delay chain circuit, comprising: digital delay elements, clock lock digital delay chain, write operation clock digital delay chain, write operation DQS digital delay chain and read operation DQS digital delay chain.
Described digital delay elements, please refer to accompanying drawing 1, by postponing minimum clocked inverter and the less clock selector of rising edge negative edge deviation is composed in series.The input clock of digital delay elements enters the port B of digital delay elements clock selector, and the output signal of next stage digital delay elements, after the clocked inverter of digital delay elements at the corresponding levels, is connected to clock selector port A at the corresponding levels; When clock selector selects signal to be 1, digital delay elements output clock selector switch port B signal at the corresponding levels, when the selection signal of digital delay elements at the corresponding levels is 0, digital delay elements output clock selector switch port A data at the corresponding levels are to upper level digital delay elements.
Described clock lock digital delay chain, please refer to accompanying drawing 2, adjusts digital delay elements be composed in series by 128 grades of identical digital delay elements and the first order phase that possesses digital delay elements same circuits structure.The input end of clock lock digital delay chain receives the system clock of DDR2, binary value clock_lock_delaycell_num_odd corresponding to the digital delay elements quantity configuration register one_hot_clock_lock_delaycell_num of one-hot encoding is adopted to be connected to phase place adjustment digital delay elements, digital delay elements quantity configuration register one_hot_clock_lock_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 1st of one_hot_clock_lock_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 2nd the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, 128th the selection sel port being connected to delay chain the 128th stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except the 128th stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of 127 stages of digital delay cells from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Clock signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, as clock_lock_delaycell_num_odd, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described clock lock digital delay chain, clock lock digital delay chain postpones from the 11st selected stages of digital delay cell, when the retardation of 11 stages of digital delay cells is less than a DDR2 system clock cycle, DDR22 system controller increases the quantity of selected digital delay elements, cumulative until a clock period of locking with this, the digital delay elements quantity that this example locks a clock period is round divided by digital delay elements retardation the clock period, i.e. 3.75/0.1=38, owing to there is the factors such as wire delay, digital delay elements quantity selects 37.
Described clock lock digital delay chain, when from the 37th stages of digital delay units delay, namely one_hot_clock_lock_delaycell_num the 36th is 1,36th stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to the 37th stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from the 36th stages of digital delay cell after clock selector postpones, be input to the 35th stages of digital delay cell clocked inverter, the 35th stages of digital delay cell clock selector A mouth is input to after phase inverter, 35th stages of digital delay cell output signal is connected to the 34th stages of digital delay cell clocked inverter, the 34th stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements.
Described clock lock digital delay chain, delayed clock outputs to selector switch C port from the 37th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 36th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 35th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 36 clocked inverters and clock selector A port to selector switch C port delay.
Described clock lock digital delay chain, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that 36 grades of clocked inverters and clock selector A port produce to selector switch C port number delay cell; Amounting to through 37 stages of digital delay cells the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts clock lock digital chain clock selector B port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that clock lock digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
Described write operation clock digital delay chain, please refer to accompanying drawing 3, adjusts digital delay elements be composed in series by 128 grades of identical digital delay elements and the first order phase that possesses digital delay elements same circuits structure.The input end of write operation clock digital delay chain receives the system clock of DDR2, write_clk_delaycell_num_odd is connected to phase place adjustment digital delay elements, one_hot_write_clk_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 1st of one_hot_write_clk_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 2nd the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, 128th the selection sel port being connected to delay chain the 128th stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except the 128th stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of 127 stages of digital delay cells from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Clock signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write_clk_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described write operation clock digital delay chain, when from the 28th stages of digital delay units delay, namely one_hot_write_clk_delaycell_num the 27th is 1,28th stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to the 27th stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from the 28th stages of digital delay cell after clock selector postpones, be input to the 27th stages of digital delay cell clocked inverter, the 27th stages of digital delay cell clock selector A mouth is input to after phase inverter, 27th stages of digital delay cell output signal is connected to the 26th stages of digital delay cell clocked inverter, the 26th stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the write operation clock of high duty ratio relative to DDR2 system clock 3/4 phase place.
Described write operation clock digital delay chain, delayed clock outputs to selector switch C port from the 28th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 27th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 26th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 27 clocked inverters and clock selector A port to selector switch C port delay.
Described write operation clock digital delay chain, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that 26 grades of clocked inverters and clock selector A port produce to selector switch C port number delay cell; Amounting to through 28 stages of digital delay cells the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Write operation clock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of write operation clock digital chain and selector switch A port to exporting C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.
Described write operation DQS digital delay chain, please refer to accompanying drawing 4, adjusts digital delay elements be composed in series by 128 grades of identical digital delay elements and the first order phase that possesses digital delay elements same circuits structure.The input end of write operation DQS digital delay chain receives the system clock of DDR2, one_hot_write_dqs_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 1st of one_hot_write_dqs_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 2nd the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the 128th is connected to the selection sel port of delay chain the 128th stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except the 128th stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of 127 stages of digital delay cells from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Write operation DQS signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write operation DQS digital number delay cell quantity is odd number, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described write operation DQS digital delay chain, one_hot_write_dqs_delaycell_num the 36th is 1,37th stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to the 36th stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from the 37th stages of digital delay cell after clock selector postpones, be input to the 36th stages of digital delay cell clocked inverter, the 36th stages of digital delay cell clock selector A mouth is input to after phase inverter, 36th stages of digital delay cell output signal is connected to the 35th stages of digital delay cell clocked inverter, the 35th stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export high duty ratio write operation DQS.
Described write operation DQS digital delay chain, delayed clock outputs to selector switch C port from the 37th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 36th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 35th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 36 clocked inverters and clock selector A port to selector switch C port delay.
Described write operation DQS digital delay chain, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that 36 stages of digital delay cell clock selector A ports produce to selector switch C port; Amounting to through 37 stages of digital delay cells the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Write operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts write operation DQS digital chain clock selector A port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that write operation DQS digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
Described read operation DQS digital delay chain, please refer to accompanying drawing 5, adjusts digital delay elements be composed in series by 128 grades of identical digital delay elements and the first order phase that possesses digital delay elements same circuits structure.The input end of read operation DQS digital delay chain receives the system clock of DDR2, one_hot_read_dqs_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_read_dqs_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the 127th is connected to the selection sel port of delay chain the 128th stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except the 128th stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of 127 stages of digital delay cells from the 1st stages of digital delay cell, output terminal except first order digital delay elements clock selector is received except phase place adjustment digital delay elements, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Write operation DQS signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write operation DQS digital number delay cell quantity is odd number, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
Described read operation DQS digital delay chain, one_hot_read_dqs_delaycell_num the 8th is 1,9th stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, be 0 from the first order to the clock selector sel port of the 8th stages of digital delay cell, select this stages of digital delay cell clock selector A port to output signal as this stages of digital delay cell.DDR2 system clock from the 9th stages of digital delay cell after clock selector postpones, be input to the 8th stages of digital delay cell clocked inverter, the 8th stages of digital delay cell clock selector A mouth is input to after phase inverter, 8th stages of digital delay cell output signal is connected to the 7th stages of digital delay cell clocked inverter, the 7th stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of first order digital delay elements, first order digital delay elements output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the read operation DQS of high duty ratio relative to 1/4 phase place of DDR2 system clock.
Described read operation DQS digital delay chain, its delayed clock outputs to selector switch C port from the 9th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 8th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 7th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 8 clocked inverters and clock selector A port to selector switch C port delay.
Described read operation DQS digital delay chain, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that 8 stages of digital delay cell clock selector A ports produce to selector switch C port; Amounting to through 9 stages of digital delay cells the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts read operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation.After phase place adjustment, the rising edge clock that read operation DQS digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.

Claims (18)

1. a high duty ratio DDR2 digital delay chain circuit, is characterized in that: comprise digital delay elements, clock lock digital delay chain, write operation clock digital delay chain, write operation DQS digital delay chain and read operation DQS digital delay chain;
Described digital delay elements is by postponing minimum clocked inverter and the less clock selector of rising edge negative edge deviation is composed in series; Described digital delay chain is in series by multiple digital delay elements;
Described clock lock digital delay chain, adjusts digital delay elements by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure and is composed in series;
Described write operation clock digital delay chain, adjusts digital delay elements by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure and is composed in series;
Described write operation DQS digital delay chain, adjusts digital delay elements by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure and is composed in series;
Described read operation DQS digital delay chain, adjusts digital delay elements by the digital delay elements that N level is identical with the first order phase possessing digital delay elements same circuits structure and is composed in series.
2. require described high duty ratio DDR2 digital delay chain circuit according to right 1, it is characterized in that, the input clock of digital delay elements at the corresponding levels enters the port B of digital delay elements clock selector, the output signal of next stage digital delay elements, after the clocked inverter of digital delay elements at the corresponding levels, is connected to clock selector port A at the corresponding levels; When clock selector selects signal to be 1, digital delay elements output clock selector switch port B signal at the corresponding levels, when the selection signal of digital delay elements at the corresponding levels is 0, digital delay elements output clock selector switch port A data at the corresponding levels are to upper level digital delay elements.
3. high duty ratio DDR2 digital delay chain circuit according to claim 1, it is characterized in that: the input end of described clock lock digital delay chain is the system clock of DDR2, binary value lowest order clock_lock_delaycell_num_odd corresponding to the digital delay elements quantity configuration register one_hot_clock_lock_delaycell_num of one-hot encoding is adopted to be connected to phase place adjustment digital delay elements, digital delay elements quantity configuration register one_hot_clock_lock_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_clock_lock_delaycell_num is connected to the selection sel port of the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to the 2nd stages of digital delay cell clock selector, by that analogy, N-1 position is connected to the selection sel port of N stages of digital delay cell clock selector, DDR2 system clock is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter, the output of the 1st stages of digital delay cell is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when clock_lock_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
4. high duty ratio DDR2 digital delay chain circuit according to claim 3, it is characterized in that: described clock lock digital delay chain, when from M stages of digital delay units delay, namely one_hot_clock_lock_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, this stages of digital delay cell clock selector A port is selected to output signal as this stages of digital delay cell, DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell outputs to phase place adjustment digital delay elements, when clock_lock_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data, when the retardation of M stages of digital delay cell is less than a DDR2 system clock cycle, clock lock phase detector and clock lock digital delay chain controller increase the quantity of selected digital delay elements, cumulative until a clock period of locking with this, otherwise then reduce the quantity of digital delay elements, successively decrease with this until lock a clock period.
5. high duty ratio DDR2 digital delay chain circuit according to claim 4, it is characterized in that: described clock lock digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
6. high duty ratio DDR2 digital delay chain circuit according to claim 4, it is characterized in that: described clock lock digital delay chain, when M is even number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of clock lock digital chain and selector switch A port to exporting C port rising edge and negative edge deviation; After phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts clock lock digital chain clock selector B port to output C port rising edge and negative edge deviation; After phase place adjustment, the rising edge clock that clock lock digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
7. high duty ratio DDR2 digital delay chain circuit according to claim 1, it is characterized in that: the input end of described write operation clock digital delay chain receives the system clock of DDR2, binary value lowest order write_clk_delaycell_num_odd corresponding to the digital delay elements quantity configuration register one_hot_write_clk_delaycell_num of one-hot encoding is adopted to be connected to phase place adjustment digital delay elements, one_hot_write_clk_delaycell_num is as the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_write_clk_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except first order digital delay elements clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter, clock signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write_clk_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
8. high duty ratio DDR2 digital delay chain circuit according to claim 7, it is characterized in that: described write operation clock digital delay chain, when from M stages of digital delay units delay, namely one_hot_write_clk_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, this stages of digital delay cell clock selector A port is selected to output signal as this stages of digital delay cell, DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the high duty ratio write operation clock postponing 3/4 phase place relative to DDR2 system clock.
9. high duty ratio DDR2 digital delay chain circuit according to claim 8, it is characterized in that: described write operation clock digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
10. high duty ratio DDR2 digital delay chain circuit according to claim 8, it is characterized in that: described write operation clock digital delay chain, when M is even number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Write operation clock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of write operation clock digital chain and selector switch A port to exporting C port rising edge and negative edge deviation; After phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay elements M-1 stages of digital delay cell of having cancelled out each other produces clock selector A port to the rising edge of selector switch C port and negative edge deviation; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Write operation clock digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts write operation clock digital chain clock selector B port to output C port rising edge and negative edge deviation; After phase place adjustment, the rising edge clock that write operation clock digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
11. high duty ratio DDR2 digital delay chain circuits according to claim 1, it is characterized in that: the input end of described write operation DQS digital delay chain receives the system clock of DDR2, binary value lowest order write_dqs_delaycell_num_odd corresponding to the digital delay elements quantity configuration register one_hot_write_dqs_delaycell_num of one-hot encoding is adopted to be connected to phase place adjustment digital delay elements, one_hot_write_dqs_delaycell_num is connected to the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_write_dqs_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter, write operation DQS signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when write_dqs_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
12. high duty ratio DDR2 digital delay chain circuits according to claim 11, it is characterized in that: described write operation DQS digital delay chain, when from M stages of digital delay units delay, namely one_hot_write_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, this stages of digital delay cell clock selector A port is selected to output signal as this stages of digital delay cell, DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the high duty ratio write operation DQS relative to DDR2 system clock 1 phase delay.
13. high duty ratio DDR2 digital delay chain circuits according to claim 12, it is characterized in that: described write operation DQS digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
14. high duty ratio DDR2 digital delay chain circuits according to claim 12, it is characterized in that: described write operation DQS digital delay chain, when M is even number, digital delay elements has cancelled out each other M-2 stages of digital delay cell clocked inverter and selector switch A port to exporting the rising edge and negative edge deviation that C port produces; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Write operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of write operation DQS digital chain and selector switch A port to exporting C port rising edge and negative edge deviation; After phase place adjustment, the write operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay elements has cancelled out each other M-1 stages of digital delay cell clocked inverter and selector switch A port to exporting the rising edge and negative edge deviation that C port produces; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Write operation DQS digital delay chain first order digital delay elements outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts write operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation; After phase place adjustment, the rising edge clock that write operation DQS digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
15. high duty ratio DDR2 digital delay chain circuits according to claim 1, it is characterized in that: the input end of described read operation DQS digital delay chain receives the system clock of DDR2, adopt binary value lowest order one_hot_read_dqs_delaycell_num that the digital delay elements quantity configuration register one_hot_read_dqs_delaycell_num of one-hot encoding is corresponding as the selection sel port of the clock selector of digital delay elements, the 0th of one_hot_read_dqs_delaycell_num is connected to the selection sel port of delay chain the 1st stages of digital delay cell clock selector, 1st the selection sel port being connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector, the DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, A port except N stages of digital delay cell clock selector is connected to fixes 0, be connected to the output of digital delay elements clocked inverter at the corresponding levels to the clock selector A port of N-1 stages of digital delay cell from the 1st stages of digital delay cell, output terminal except the 1st stages of digital delay cell clock selector is received except phase place adjustment digital delay elements, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter, write operation DQS signal after postponing is connected to clocked inverter input port and the clock selector A port of phase place adjustment digital delay elements, clock selector B port is connected to the output port of this grade of clocked inverter, when read_dqs_delaycell_num_odd is 1, phase place adjustment digital delay elements output clock selector switch B port data, otherwise outlet selector A port data.
16. high duty ratio DDR2 digital delay chain circuits according to claim 15, it is characterized in that: described read operation DQS digital delay chain, when from M stages of digital delay units delay, namely one_hot_read_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, this stages of digital delay cell clock selector B port is selected to output signal as this stages of digital delay cell, clock selector sel port from the 1st grade to M-1 stages of digital delay cell is 0, this stages of digital delay cell clock selector A port is selected to output signal as this stages of digital delay cell, DDR2 system clock from M stages of digital delay cell after clock selector postpones, be input to M-1 stages of digital delay cell clocked inverter, M-1 stages of digital delay cell clock selector A mouth is input to after phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, M-2 stages of digital delay cell clock selector A mouth is input to after phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, 1st stages of digital delay cell output clock is input to phase place adjustment digital delay elements, adjust through phase place, export the high duty ratio read operation DQS relative to DDR2 system clock 1/4 phase delay.
17. high duty ratio DDR2 digital delay chain circuits according to claim 16, it is characterized in that: described read operation DQS digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through M-1 clocked inverter and clock selector A port to selector switch C port delay.
18. high duty ratio DDR2 digital delay chain circuits according to claim 16, it is characterized in that: described read operation DQS digital delay chain, when M is even number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch A port data, counteracts the clocked inverter of read operation DQS digital chain and selector switch A port to exporting C port rising edge and negative edge deviation; After phase place adjustment, the read operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay elements has been cancelled out each other the rising edge and negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port; Amounting to through M stages of digital delay cell the deviation produced is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place adjustment digital delay elements clock selector B port and clocked inverter input port, phase place adjustment digital delay elements output clock selector switch B port data, counteracts read operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation; After phase place adjustment, the rising edge clock that read operation DQS digital delay chain postpones and negative edge deviation are 0, and output clock dutycycle reaches 1:1.
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