CN103036817A

CN103036817A - Server single-board, server single-board realization method and host processor

Info

Publication number: CN103036817A
Application number: CN2012105446005A
Authority: CN
Inventors: 彭华; 萧晓晖
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2012-12-14
Filing date: 2012-12-14
Publication date: 2013-04-10

Abstract

The invention provides a server single board and a realization method thereof, and relates to the field of communication. The server single board can reduce delaying inside a server, and improve quality of network service. The server single board comprises a personal computer Internet explorer (PCIe) exchanger, a host processor and a plurality of sub-processors, wherein the PCIe exchanger comprises an upstream port and a plurality of downstream ports, the host processor is connected with the upstream port, and the plurality of the sub-processors are respectively connected with the downstream ports of the PCIe exchanger. The host processor is used for receiving a first ethernet data packet sent by other single boards through an internet access, converting the first ethernet data packet to a first PCIe data packet, and transmitting the first PCIe data packet to one or more sub-processor through the PCIe exchanger. The host processor is further used for receiving a second PCIe data packet sent by one or more sub-processor, converting the second PCIe data packet into a second ethernet data packet, and transmitting the second PCIe data packet to other single boards through the internet access.

Description

A kind of server veneer, server veneer implementation method and primary processor

Technical field

The present invention relates to the communications field, relate in particular to a kind of server veneer, server veneer implementation method and primary processor.

Background technology

Along with the development of the communication technology, provide the quantity of telecommunication apparatus of the functions such as core calculations, the management of information resources, information resources service also in continuous growth to the user.Too high energy consumption not only affects the operation cost of operator, also will cause the serious waste of the energy, therefore, and the energy-conservation focus that becomes gradually the industry concern of telecommunication apparatus.

Telecommunications room generally is comprised of parts such as a large amount of servers, switching equipment, access device, memory device and the network equipments.Wherein, the server that presents with variform (such as rack, blade type, card insert type) is the highest parts of energy consumption in the telecommunications room often.In numerous server conservation measuress, the server that adopts the low power processor chip to make up low-power consumption is exactly a very effective measure.

Comprise the server that is consisted of by a plurality of low power processor chips in the prior art, in this system, in order to make data can between different processor chips, carry out reasonable disposition and scheduling, can interconnect by the Fast Ethernet interface between the processor chips.Because the Ethernet interface limited amount of each processor chips, usually adopt tree structure to interconnect between the processor chips, when processor chips quantity is more, then the degree of depth of tree structure needs very large totally interconnected between each processor chips of can realizing, but so, for the processor chips that are in leaf node, if the processor of two leaf nodes will be realized data interaction, must pass through multistage Ethernet exchanging, this incites somebody to action so that time-delay strengthens, thereby has a strong impact on the quality of network service.

Summary of the invention

Embodiments of the invention provide a kind of server veneer, server veneer implementation method and primary processor, and the server internal delay time that exists for the solution prior art is large, thereby have a strong impact on the problem of network service quality.

For achieving the above object, embodiments of the invention adopt following technical scheme:

First aspect, embodiment of the invention the first implementation provides a kind of server veneer, is applied to server system, and described server system also comprises at least one other veneer that is connected with described server veneer, and described server veneer comprises:

The PCIe interchanger, primary processor and a plurality of from processor, described PCIe interchanger comprises a uplink port and a plurality of downlink port;

Described primary processor links to each other with the uplink port of described PCIe interchanger, described a plurality ofly link to each other with the downlink port of described PCIe interchanger respectively from processor;

Described primary processor is used for receiving the first Ethernet data bag that described other veneers send by network interface, described the first Ethernet data bag is changed into a PCIe packet, described uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor with a described PCIe package forward;

Described primary processor also is used for receiving described the 2nd PCIe packet that sends from processor by described PCIe interchanger, described the 2nd PCIe packet is changed into the second Ethernet data bag, transmit described the second Ethernet data bag by described network interface to described other veneers.

In conjunction with first aspect the first possibility implementation, in the possible implementation of the second, described primary processor also is used for, receive one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger, and give another described from processor described the 3rd PCIe package forward by described PCIe interchanger.

In conjunction with first aspect the first or the possible implementation of the second, in the third possible implementation, described primary processor is used for that described the 2nd PCIe packet is changed into the second Ethernet data bag and is specially:

If the payload of described the 2nd PCIe packet comprises complete Ethernet data bag, described primary processor is used for directly extracting described Ethernet data bag to obtain the second Ethernet data bag; Or,

If the payload of described the 2nd PCIe packet comprises the payload of Ethernet data bag, described primary processor encapsulates to obtain the second Ethernet data bag for the payload that extracts described Ethernet data bag.

Arrive the third arbitrary possible implementation in conjunction with first aspect first, in the 4th kind of possible implementation, described primary processor also is used for, generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described primary processor is used for described the first Ethernet data bag is changed into a PCIe packet, described uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger from processor specifically is to link to each other with described downlink port described a described PCIe package forward:

Described primary processor is used for:

With in the payload of described the first Ethernet data bag overall package to the PCIe packet or described primary processor be used for extracting the payload of described the first Ethernet data bag, the payload in described the first Ethernet data bag is encapsulated in the payload of a PCIe packet; According to described path configuration table and described from the obtaining with described from the first routing iinformation corresponding to processor from processor flag of processor, described the first routing iinformation is added to the head of a described PCIe packet; Uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor according to described the first routing iinformation in the described PCIe packet head with a described PCIe package forward.

To the 4th kind of arbitrary possible implementation, in the 5th kind of possible implementation, described primary processor also is used in conjunction with first aspect first:

Receive described from processor transmission load request by described PCIe interchanger;

According to described load request read operation system and application program image file;

The described operating system image file that reads is sent to by described PCIe interchanger described from server so that describedly start the operating system according to described operating system image file from processor.

In conjunction with first aspect first to the 5th kind of arbitrary possible implementation, in the 6th kind of possible implementation,

Described primary processor also is used for:

Send online detect-message to described from processor by described PCIe interchanger, describedly whether normally connect from processor to detect;

When determining one during from the processor connection failure, will be sent to a described packet from processor according to default sending strategy and be sent to another from processor by described PCIe interchanger.

In conjunction with the 6th kind of implementation of first aspect, in the 7th kind of possible implementation, when determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

Second aspect, in the possible implementation of the first, the present embodiment discloses a kind of server veneer implementation method, and described server veneer is applied to server system, described server system also comprises at least one other veneer that is connected with described server veneer, comprising:

Primary processor receives the first Ethernet data bag that described other veneers send by network interface;

Described primary processor changes into a PCIe packet with described the first Ethernet data bag;

Described primary processor is given described PCIe interchanger by the described uplink port of described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor with a described PCIe package forward;

Described primary processor receives described the 2nd PCIe packet that sends from processor by described PCIe interchanger;

Described primary processor changes into the second Ethernet data bag with described the 2nd PCIe packet;

Described primary processor is transmitted described the second Ethernet data bag by described network interface to described other veneers.

In conjunction with the possible implementation of second aspect the first, in the possible implementation of the second, described method also comprises:

Described primary processor receives one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger, and gives another described from processor described the 3rd PCIe package forward by described PCIe interchanger.

To the arbitrary possible implementation of the second, in the third possible implementation, described primary processor changes into the second Ethernet data bag with described the 2nd PCIe packet and comprises in conjunction with second aspect first:

If the payload of described the 2nd PCIe packet comprises complete Ethernet data bag, described primary processor directly extracts described Ethernet data bag to obtain the second Ethernet data bag; Or,

If the payload of described the 2nd PCIe packet comprises the payload of Ethernet data bag, the payload that described primary processor extracts described Ethernet data bag encapsulates to obtain the second Ethernet data bag.

To the third arbitrary possible implementation, in the 4th kind of possible implementation, described method also comprises in conjunction with second aspect first:

Generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described primary processor changes into a PCIe packet with described the first Ethernet data bag and comprises:

With in the payload of described the first Ethernet data bag overall package to the PCIe packet or described primary processor extract payload in described the first Ethernet data bag, the payload in described the first Ethernet data bag is encapsulated in the payload of a PCIe packet; According to described path configuration table and described from the obtaining with described from the first routing iinformation corresponding to processor from processor flag of processor, described the first routing iinformation is added to the head of a described PCIe packet;

Described primary processor is given described PCIe interchanger by the described uplink port of described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger comprises to link to each other with described downlink port described a described PCIe package forward from processor:

Uplink port by described PCIe interchanger is given described PCIe interchanger with a described PCIe package forward, so that described PCIe interchanger is given link to each other with described downlink port described from processor according to described the first routing iinformation in the described PCIe packet head with a described PCIe package forward.

To the 4th kind of arbitrary possible implementation, in the 5th kind of possible implementation, described method also comprises in conjunction with second aspect first:

Described primary processor receives described from processor transmission load request by described PCIe interchanger;

Whether to the 5th kind of arbitrary possible implementation, in the 6th kind of possible implementation, described primary processor sends online detect-message to described from processor by described PCIe interchanger in conjunction with second aspect first, describedly normally connect from processor to detect;

When determining one during from the processor connection failure, described primary processor will be sent to a described packet from processor according to default sending strategy and be sent to another from processor by described PCIe interchanger.

In conjunction with the 6th kind of possible implementation of second aspect, in the 7th kind of possible implementation, when determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

The third aspect, in the possible mode of the first, the present embodiment discloses a kind of processor, is applied to the server veneer, and described primary processor comprises:

The first receiver module is used for receiving the first Ethernet data bag that other veneers send by network interface;

The first modular converter, described the first Ethernet data bag that is used for described the first receiver module is received changes into a PCIe packet;

The first sending module, be used for the described PCIe package forward that will described the first modular converter be converted to by the PCIe interchanger to link to each other with described PCIe interchanger from processor;

The second receiver module is used for receiving described the 2nd PCIe packet that sends from processor by described PCIe interchanger;

The second modular converter, described the 2nd PCIe packet that is used for described the second receiver module is received changes into the second Ethernet data bag;

The second sending module is used for transmitting described the second Ethernet data bag that described the second modular converter is converted to by described network interface to described other veneers.

In conjunction with the possible implementation of the third aspect first, in the possible implementation of the second, described the first sending module, concrete be used for by the PCIe interchanger uplink port with a described PCIe packet via the PCIe interchanger send to link to each other with the downlink port of described PCIe interchanger from processor;

Described the second receiver module, concrete being used for receives the 2nd that described downlink port from processor from described PCIe interchanger sends, arrive the uplink port of described PCIe interchanger via described PCIe interchanger PCIe packet from the uplink port of described PCIe interchanger.

To the arbitrary possible implementation of the second, in the third possible implementation, described the second receiver module also is used for receiving one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger in conjunction with the third aspect first;

Described the first sending module also is used for by described PCIe interchanger described the 3rd PCIe package forward that described the second receiver module receives is described from processor to another.

To the third arbitrary possible implementation, in the 4th kind of possible implementation, described primary processor also comprises in conjunction with the third aspect first:

The allocation list generation module is used for the generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described the first modular converter comprises:

The payload processing module, be used for the payload of described the first Ethernet data bag overall package to the PCIe packet or for the payload that extracts described the first Ethernet data bag the payload in described the first Ethernet data bag being encapsulated in the payload of a PCIe packet;

The head processing module, be used for according to described path configuration table and described obtaining with described from the first routing iinformation corresponding to processor from processor flag from processor, described the first routing iinformation is added to the head of a described PCIe packet, so that after described PCIe interchanger receives the described PCIe packet that rear described the first sending module sends, according to described the first routing iinformation in the described PCIe packet head will a described PCIe package forward to described from processor.

In conjunction with the third aspect first to the 4th kind of arbitrary possible implementation, in the 5th kind of possible implementation, the 3rd receiver module, be used for receiving the described load request that sends by described PCIe interchanger from processor, according to described load request read operation system and application program image file;

The 3rd sending module, the described operating system image file that is used for reading is sent to described from processor by described PCIe interchanger, so that describedly start the operating system according to described operating system image file from processor.

To the 5th kind of arbitrary possible implementation, in the 6th kind of possible implementation, described primary processor also comprises in conjunction with second aspect first:

Whether detection module is used for sending online detect-message to described from processor by described PCIe interchanger, describedly normally connect from processor to detect;

Determine one during from the processor connection failure when described detection module, described the first sending module also is used for:

To be sent to described packet from processor according to default sending strategy and be sent to another from processor by described PCIe interchanger; When determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

The server veneer that the embodiment of the invention provides, server veneer implementation method and primary processor, this server veneer is applied to server system, this server system also comprises at least one other veneer that is connected with this server veneer, this server veneer specifically comprises the PCIe interchanger, primary processor and a plurality of from processor, wherein, the PCIe interchanger comprises a uplink port and a plurality of downlink port; Primary processor links to each other with the uplink port of this PCIe, a plurality ofly links to each other with the downlink port of this PCIe interchanger respectively from processor.Adopt a kind of like this server veneer of structure, primary processor can carry out the transmitting-receiving of data by network interface and other veneers, this primary processor is connected from processor with each by the PCIe interchanger again, therefore, all can finish by primary processor from transmitting-receiving and each exchange from data between the processor of processor data.So, need not to adopt multistage tree structure just can realize interconnection between the full processor, thereby avoided data between the multistep treatment device, to transmit, reduced the time-delay of server veneer, improved the quality of network service.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

The structural representation of a kind of server veneer that Fig. 1 provides for the embodiment of the invention;

The structural representation of a kind of primary processor that Fig. 2 a provides for the embodiment of the invention;

The structural representation of another primary processor that Fig. 2 b provides for the embodiment of the invention;

The syndeton schematic diagram of a kind of server veneer that Fig. 3 provides for the embodiment of the invention;

The schematic flow sheet of a kind of server veneer implementation method that Fig. 4 provides for the embodiment of the invention;

The schematic flow sheet of another server veneer implementation method that Fig. 5 provides for the embodiment of the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.

The server veneer 1 that the embodiment of the invention provides can be applied to server system, and this server system can also comprise at least one other veneer 2 that is connected with server veneer 1, and as shown in Figure 1, server veneer 1 can comprise:

PCIe interchanger 11, primary processor 12 and a plurality of from processor 13, this PCIe interchanger 11 can comprise a uplink port and a plurality of downlink port.

This primary processor 12 links to each other with the uplink port of PCIe interchanger 11, a plurality ofly links to each other with the downlink port of this PCIe interchanger 11 respectively from processor 13.

This primary processor 12 is used for receiving the first Ethernet data bag that other veneers 2 send by network interface 14, this the first Ethernet data bag is changed into a PCIe packet, uplink port by PCIe interchanger 11 with a PCIe package forward to PCIe interchanger 11 so that this PCIe interchanger 11 with a PCIe package forward give link to each other with downlink port from processor 13.

For example, primary processor 12 specifically can comprise the process that the first Ethernet data bag changes into a PCIe packet: in the payload of primary processor 12 with this first Ethernet data bag overall package to the PCIe packet, the mode of a kind of like this overall package of employing can efficiently realize the conversion of data packet format rapidly; Perhaps, primary processor 12 can also extract the payload in this first Ethernet data bag, and the payload in this first Ethernet data bag is encapsulated in the payload of a PCIe packet, so, the non-critical data that does not comprise packet header of comprising the Ethernet data bag etc. in the PCIe packet of encapsulation, greatly reduce the capacity of PCIe packet, improved the packaging efficiency of PCIe packet.

This primary processor 12 also is used for receiving the 2nd PCIe packet that sends from processor 13 by PCIe interchanger 11, and the 2nd PCIe packet is changed into the second Ethernet data bag, transmits this second Ethernet data bag by network interface 14 to other veneers 2.

Accordingly, primary processor 12 specifically can comprise the process that the 2nd PCIe packet changes into the second Ethernet data bag: if the payload of the 2nd PCIe packet comprises complete Ethernet data bag, primary processor 12 can directly extract this Ethernet data bag to obtain the second Ethernet data bag; Perhaps, if the payload of the 2nd PCIe packet comprises the payload of Ethernet data bag, the payload that primary processor 12 can extract this Ethernet data bag encapsulates to obtain the second Ethernet data bag.

In embodiments of the present invention, processor can comprise x86 processor or arm processor.Wherein, the x86 processor specifically refers to the processor based on the low-power consumption of x86.In actual applications, because the processor based on the ARM framework has the characteristics such as low cost, low-power consumption, carry out the server that cluster can obtain superior performance by the arm processor with a plurality of lower-performances, when having guaranteed server performance, greatly reduce production cost, reduced the power consumption of server.

The server veneer that the embodiment of the invention provides, be applied to server system, this server system also comprises at least one other veneer that is connected with this server veneer, this server veneer specifically comprises the PCIe interchanger, primary processor and a plurality of from processor, wherein, the PCIe interchanger comprises a uplink port and a plurality of downlink port; Primary processor links to each other with the uplink port of this PCIe, a plurality ofly links to each other with the downlink port of this PCIe interchanger respectively from processor.Adopt a kind of like this server veneer of structure, primary processor can carry out the transmitting-receiving of data by network interface and other veneers, this primary processor is connected from processor with each by the PCIe interchanger again, therefore, all can finish by primary processor from transmitting-receiving and each exchange from data between the processor of processor data.So, need not to adopt multistage tree structure just can realize interconnection between the full processor, thereby avoided data between the multistep treatment device, to transmit, reduced the time-delay of server veneer, improved the quality of network service.

Further, primary processor 12 can also be used for, and receives the 3rd PCIe packet that one of them sends from processor 13 by PCIe interchanger 11, and by PCIe interchanger 11 with the 3rd PCIe package forward to another from processor 13.

So, a plurality of from can carrying out exchanges data by primary processor 12 control PCIe interchangers 11 between the processor 13, thus avoided data between the multistep treatment device, to transmit, reduced the time-delay of server veneer, improved the quality of network service.

Further, primary processor 12 can also be used for:

Initialization PCIe interchanger 11, the register by PCI allocation e interchanger 11 is so that this PCIe interchanger 11 can work.

Wherein, primary processor 12 initialization PCIe interchangers 11 specifically can comprise: for each that links to each other with this PCIe interchanger 11 distributes routing iinformation from processor 13.

Need to prove, in embodiments of the present invention, routing iinformation specifically can comprise BDF (Bus (bus), Device (equipment), Function (function) number general designation) information or BAR (Base Address Register, base address register) space address.

This primary processor 12 can also be used for, the generation pass allocation list, this path configuration table comprise from processor 13 sign and with this from routing iinformation corresponding to processor 13 signs, wherein, identical from routing iinformation corresponding to the processor 13 signs routing iinformation that from processor 13 distribute indicated with being this processor flag with this.

Further, primary processor 12 changes into a PCIe packet with the first Ethernet data bag, uplink port by PCIe interchanger 11 with a PCIe package forward to PCIe interchanger 11, so that PCIe interchanger 11 gives the detailed process from processor 13 that links to each other with downlink port can be as follows a PCIe package forward:

At first, primary processor 12 can with in the payload of the first Ethernet data bag overall package to the PCIe packet or primary processor 12 can extract payload in the first Ethernet data bag, the payload in this first Ethernet data bag is encapsulated in the payload of a PCIe packet.

After the encapsulation of finishing a PCIe packet, primary processor can according to path configuration table and from the obtaining with this from the first routing iinformation corresponding to processor 13 from processor flag of processor 13, add this first routing iinformation on the head of the one PCIe packet; Uplink port by PCIe interchanger 11 with a PCIe package forward to PCIe interchanger 11 so that PCIe interchanger 11 can according to the first routing iinformation in the PCIe packet head with a PCIe package forward give link to each other with downlink port from processor 13.

For example, record each in the path configuration table from the identity information of processor, this identity information can be from the residing bus ID of processor or this MAC (Medium Access Control from processor, media access control layer) address, each is from all corresponding default routing iinformation of identity information of processor, primary processor 12 is before transmitting a PCIe packet by PCIe interchanger 11, can be according to path configuration table and obtaining with this from routing iinformation corresponding to processor 13 from processor flag from processor 13, this routing iinformation is added to the head of a PCIe packet, PCIe interchanger 11 can be by the routing iinformation accessed path allocation list of PCIe packet head record, obtain one or more routing iinformations from processor 13 according to this path configuration table, thereby give a PCIe package forward one or more from processor 13.

Certainly, a plurality of from carrying out according to this path configuration table the exchange of data equally between the processor 13.For example, finish the initialization of PCIe interchanger 11 and generation pass allocation list after the scanning of processor 13 at primary processor 12, and this path configuration table is issued to each from processor 13, when first need to be to second during from the processor forwarding data from processor, can be with this Packet Generation to PCIe interchanger 11, be added with this second identity information from processor in the packet of this forwarding, PCIe interchanger 11 can the query path allocation list, thus according to second from the identity information of processor determine this second from the routing iinformation of processor in order to finish the forwarding of data.

After primary processor 12 initialization PCIe interchangers 11, can also be used for from processor 13:

Send load request by PCIe interchanger 11 to primary processor 12, with operating system and the application program of request of loading necessity.

Accordingly, after receiving this load request, primary processor 12 can also be used for: according to this load request read operation system and application program image file; The operating system image file that reads is sent to from server 13 by PCIe interchanger 11, so that should start the operating system according to this operating system image file from processor 13.

So, can be in advance the image file of operating system and application program be placed in the storage medium of primary processor 12, when needing to load from processor 13, only this image file need to be taken out to be sent to from processor 13 from the storage medium of primary processor 12 and get final product, thereby can be so that each need not to provide for oneself operating system and application program from processor 13, saved from the internal memory of processor 13, improved from the treatment effeciency of processor 13.

Further, primary processor 12 can also be used for:

, whether normally connect to detect from processor 13 to sending online detect-message from processor 13 by PCIe interchanger 11.

Concrete, when determining one during from the processor connection failure, can will be sent to this packet from processor according to default sending strategy and be sent to another from processor by PCIe interchanger 11; When determining to recover to connect from processor, be forwarded to this from processor with being sent to another packet from processor by PCIe interchanger 11.When connection failure, illustrate from processor fault (the perhaps link failure between two primary processors) to have occurred, therefore need to forward the data to other from processor so that data are processed.Here " default sending strategy " specifically do not limit, for example, can predefined good certain from processor for the treatment of other from the data of processor (or link) when being out of order, if other break down from processor (or link), then primary processor is given to processing from processor to this special use with data; Perhaps " default sending strategy " also can be " the sending from the processor load situation according to each " of presetting strategy (as with Packet Generation to load few from processor).

For example, primary processor 12 and respectively have heartbeat detection mechanism between the processor 13, whether primary processor 12 will regularly normally connect to detect from processor 13 to respectively sending the creed detection messages from processor 13.When a heartbeat from processor is lost, primary processor 12 will be somebody's turn to do from the business migration on the processor to another from processor or other are for subsequent use from processor.

The primary processor 12 that the embodiment of the invention provides can be applied to above-mentioned server veneer, and shown in Fig. 2 a, primary processor 12 comprises:

The first receiver module 21 is used for receiving the first Ethernet data bag that other veneers send by network interface.

The first modular converter 22, the first Ethernet data bag that is used for the first receiver module 21 is received changes into a PCIe packet.

The first sending module 23, be used for the PCIe package forward that the first modular converter 22 is converted to by the PCIe interchanger to link to each other with this PCIe interchanger from processor.

The second receiver module 24 is used for receiving the 2nd PCIe packet that sends from processor by the PCIe interchanger.

The second modular converter 25, the 2nd PCIe packet that is used for the second receiver module 24 is received changes into the second Ethernet data bag.

The second sending module 26 is used for transmitting the second Ethernet data bag that the second modular converter 25 is converted to by network interface to other veneers.

The primary processor that the embodiment of the invention provides, be applied to the server veneer, this server veneer is applied to server system, this server system also comprises at least one other veneer that is connected with this server veneer, this server veneer specifically comprises the PCIe interchanger, primary processor and a plurality of from processor, wherein, the PCIe interchanger comprises a uplink port and a plurality of downlink port; Primary processor links to each other with the uplink port of this PCIe, a plurality ofly links to each other with the downlink port of this PCIe interchanger respectively from processor.Adopt a kind of like this server veneer of structure, primary processor can carry out the transmitting-receiving of data by network interface and other veneers, this primary processor is connected from processor with each by the PCIe interchanger again, therefore, all can finish by primary processor from transmitting-receiving and each exchange from data between the processor of processor data.So, need not to adopt multistage tree structure just can realize interconnection between the full processor, thereby avoided data between the multistep treatment device, to transmit, reduced the time-delay of server veneer, improved the quality of network service.

Wherein, the first sending module 23, concrete be used for by the PCIe interchanger uplink port with a PCIe packet via the PCIe interchanger send to link to each other with the downlink port of this PCIe interchanger from processor.

The second receiver module 24, concrete being used for receives the 2nd that downlink port from processor from this PCIe interchanger sends, arrive the uplink port of PCIe interchanger via this PCIe interchanger PCIe packet from the uplink port of PCIe interchanger.

Further, the second receiver module 24 can also be used for receiving the 3rd PCIe packet that one of them sends from processor by the PCIe interchanger; The first sending module 23 can also be used for the 3rd PCIe package forward that the second receiver module received by the PCIe interchanger to another from processor.

So, a plurality of from can carrying out exchanges data by primary processor 12 control PCIe interchangers between the processor, thus avoided data between the multistep treatment device, to transmit, reduced the time-delay of server veneer, improved the quality of network service.

In embodiments of the present invention, the first modular converter 22 can also be used for:

In the payload with the first Ethernet data bag overall package to the PCIe packet, perhaps extract the payload in the first Ethernet data bag, the payload in this first Ethernet data bag is encapsulated in the payload of a PCIe packet;

Accordingly, the second modular converter 25 can also be used for:

If the payload of the 2nd PCIe packet comprises complete Ethernet data bag, directly extract this Ethernet data bag to obtain the second Ethernet data bag, if perhaps the payload of the 2nd PCIe packet comprises the payload of Ethernet data bag, the payload that extracts this Ethernet data bag encapsulates to obtain the second Ethernet data bag.

Further, shown in Fig. 2 b, primary processor 12 can also comprise:

Allocation list generation module 27 is used for the generation pass allocation list, this path configuration table comprise from processor flag and with this from routing iinformation corresponding to processor flag.

The first modular converter 22 can also comprise:

Payload processing module 221, be used for the payload of the first Ethernet data bag overall package to the PCIe packet or for the payload that extracts the first Ethernet data bag the payload in the first Ethernet data bag being encapsulated in the payload of a PCIe packet.

Head processing module 222, be used for according to this path configuration table and obtaining with this from the first routing iinformation corresponding to processor from processor flag from processor, this first routing iinformation is added to the head of a PCIe packet, so that the PCIe interchanger receive after behind the PCIe packet that sends of the first sending module 23, according to the first routing iinformation in the PCIe packet head the one PCIe package forward is given from processor.

Shown in Fig. 2 b, primary processor 12 can also comprise:

The 3rd receiver module 28 is used for receiving the load request that sends by the PCIe interchanger from processor, according to this load request read operation system and application program image file.

The 3rd sending module 29 is used for the operating system image file that reads is sent to from processor by the PCIe interchanger, so that should start the operating system according to this operating system image file from processor.

So, can be in advance the image file of operating system and application program be stored in the storage medium of primary processor 12, in the time need to loading from processor, only this image file need to be taken out to be sent to from processor from the storage medium of primary processor 12 and get final product, thereby can be so that each need not to provide for oneself operating system and application program from processor, save the internal memory from processor, improved the treatment effeciency from processor.

Further, primary processor 12 can also comprise:

Whether detection module 20 is used for by the PCIe interchanger should normally connecting from processor to detect to send online detect-message from processor;

Determine one during from the processor connection failure when detection module 20, the first sending module 23 can also be used for:

To be sent to from the packet of processor according to default sending strategy and to be sent to another from processor by the PCIe interchanger; When determining one when recovering to connect from processor, be forwarded to this from processor with being sent to another packet from processor by the PCIe interchanger.When connection failure, illustrate from processor fault (the perhaps link failure between two primary processors) to have occurred, therefore need to forward the data to other from processor so that data are processed.Here " default sending strategy " specifically do not limit, for example, can predefined good certain from processor for the treatment of other from the data of processor (or link) when being out of order, if other break down from processor (or link), then primary processor is given to processing from processor to this special use with data; Perhaps " default sending strategy " also can be " the sending from the processor load situation according to each " of presetting strategy (as with Packet Generation to load few from processor).

For example, primary processor 12 and respectively from having heartbeat detection mechanism between the processor, whether primary processor 12 will regularly normally connect to detect from processor to respectively sending the creed detection messages from processor.When a heartbeat from processor is lost, primary processor 12 will be somebody's turn to do from the business migration on the processor to another from processor or other are for subsequent use from processor.

Need to prove, in embodiments of the present invention, primary processor 12 can also comprise internal storage location and storage medium, and primary processor 12 can be identical with structure from processor 13.Wherein, internal storage location specifically can comprise DRAM (dynamic random access memory, dynamic random access memory) or SRAM (static random access memory, static RAM); Storage medium specifically can comprise Flash (flash memory), SATA (serial advanced technology attachment, Serial Advanced Technology Attachment), SAS (Serial Attached SCSI, interface connected in series) hard disk or SSD (solid state disk, solid state hard disc), this storage medium can be used for the image file of storage operating system and application program.

The syndeton schematic diagram of the server veneer 1 of a kind of low-power consumption that Fig. 3 provides for the embodiment of the invention.Server veneer 1 comprises server base plate 31, and this server base plate 31 specifically is comprised of power supply 311, single board management controller 312 and heat abstractor (not shown).One primary processor 12 and six interconnect by PCIe interchanger 11 between the processor 13, in embodiments of the present invention, primary processor 12 with all adopt the identical multi-functional subcard of structure from processor 13, this multi-functional subcard mainly comprises arm processor, internal storage location and storage medium.

Wherein, have a plurality of slots on the server base plate 31, be inserted in exactly these slots as primary processor 12 with from the multi-functional subcard of processor 13.Slot is divided into again home slot and from slot, and the slot addresses of home slot is different with slot addresses from slot.After each multi-functional subcard is inserted into the startup of switching in the slot, the arm processor that is inserted on the multi-functional subcard of home slot just automatically is configured to primary processor with self by the identification slot addresses, and the arm processor that is inserted into from the multi-functional subcard of slot just automatically is configured to self from processor by the identification slot addresses.

The arm processor of primary processor 12 is connected to RC (rootcomplex, the root assembly) interface of PCIe interchanger 11, is connected to EP (end point, the terminal equipment) interface of PCIe interchanger 11 from the arm processor of processor 13.

In embodiments of the present invention; primary processor 12 comprises processing unit, internal memory and storage medium; wherein, processing unit can comprise receiver module, modular converter, sending module, initialization module, table look-up module, power down protection module, XOR XOR accelerating module and safety encipher module.

The network interface 14 of primary processor 12 connection server veneers 1, this primary processor 12 are distribution of services point and the service hubs from processor 13, are intelligent network adapters as the multi-functional subcard of primary processor 12.This intelligent network adapter mainly is responsible for the transmitting-receiving of PCIe data message, the transmitting-receiving of Ethernet message; Resolve the address of PCIe data message (comprising address route, ID route, implicit expression route etc.), and according to this address lookup path configuration table; The parsing of Ethernet message and upper strata message, and according to the characteristic query path configuration table of Ethernet and upper strata message; Format conversion between PCIe data message and the Ethernet message.Except above-mentioned functions, primary processor 12 can also finish the initialization of PCIe interchanger 11, to scanning, PCIe interchanger 11 is managed etc. from processor 13.

After the energising of this server veneer starts, primary processor 12 and carry out separately initialization from processor 13, finish the initialization of PCIe interchanger 11 when primary processor 12 after, system namely enters load phase.From processor 13 by PCIe interchanger 11, to primary processor 42 request of loading operating system and application programs.Primary processor 12 is received after the request of processor 13, reads relevant operation system and application program from the storage medium (as: Flash, SATA, SAS hard disk, SSD hard disk etc.) of lower extension, sends to from processor 13 by PCIe interchanger 11.

Primary processor 12 finish the initialization of PCIe interchanger 11 and after the scanning of processor 13 the generation pass allocation list, and this table is issued to respectively from processor 13.Can communicate by letter with primary processor 12 by PCIe interchanger 11 according to this path configuration table from processor 13, also can with this server veneer on other communicate from processor 13.

In embodiments of the present invention, each application program from processor 13 operation can be Dynamical Deployment, and the user can be for different application, respectively is configured from the mode of operation of processor 13 by 12 pairs of primary processors.From between the processor 13 being the cluster relation, respectively from processor 13 operations operating system and application program separately.Also move oneself operating system and application program on the primary processor 12.Such as: first is computing function from processor 131 operation, second from processor 132 operations be memory function, these two can cooperatively interact from processor and to finish a specific business function.Need to be when being responsible for the fetching data from processor 132 of storage from processor 131 when what be responsible for to calculate, can directly finish exchanges data by PCIe interchanger 11, be that exchanges data is finished in this locality, so not only can have reduced time-delay but also outside bandwidth of network is not had impact.

Further, primary processor 12 can also be used for:

Concrete, as shown in Figure 3, when determining first during from processor 131 connection failure, be sent to second from processor 132 with being sent to this first packet from processor 131 by PCIe interchanger 11.

For example, primary processor 12 and respectively have heartbeat detection mechanism between the processor 13, whether primary processor 12 will regularly normally connect to detect from processor 13 to respectively sending the creed detection messages from processor 13.Lose from the heartbeat of processor 131 when first, primary processor 12 with first from the processor 131 business migration to the second from processor 132 or other for subsequent use from processor.

Need to prove, in embodiments of the present invention, primary processor and between the processor from processor and between the processor, all can communicate by self-defining Ethernet packet sending and receiving interface under the linux kernel attitude.On concrete physical aspect, the server veneer that the embodiment of the invention provides can be the server of rack, also can be the server of blade type.

A kind of like this server veneer of structure need not to adopt multistage tree structure just can realize interconnection between the full processor, thereby has avoided data to transmit between the multistep treatment device, has reduced the time-delay of server veneer, has improved network service quality.

The server veneer implementation method that the embodiment of the invention provides, as shown in Figure 4, this server veneer can be applied to server system, and this server system also comprises at least one other veneer that is connected with this server veneer, and the method comprises:

S401, primary processor receive the first Ethernet data bag that other veneers send by network interface.

Need to prove, in embodiments of the present invention, primary processor can be identical with structure from processor.

Concrete, primary processor can receive the first Ethernet data bag that other veneers send from network interface by the first receiver module 21.

S402, primary processor change into a PCIe packet with this first Ethernet data bag.

Concrete, primary processor can change into a PCIe packet with this first Ethernet data bag by the first modular converter 22.For example, primary processor can the payload with this first Ethernet data bag overall package to the PCIe packet in, adopt a kind of like this mode of overall package can efficiently realize rapidly the conversion of data packet format; Perhaps, primary processor can also extract the payload in this first Ethernet data bag, and the payload in this first Ethernet data bag is encapsulated in the payload of a PCIe packet, so, the non-critical data that does not comprise packet header of comprising the Ethernet data bag etc. in the PCIe packet of encapsulation, greatly reduce the capacity of PCIe packet, improved the packaging efficiency of PCIe packet.

S403, the primary processor uplink port by the PCIe interchanger with a PCIe package forward to the PCIe interchanger so that this PCIe interchanger with a PCIe package forward give link to each other with downlink port from processor.

Concrete, primary processor can be given a PCIe package forward one or more from processor by the first sending module 23.

S404, primary processor receive the 2nd PCIe packet that sends from processor by the PCIe interchanger.

S405, primary processor change into the second Ethernet data bag with the 2nd PCIe packet.

Accordingly, if the payload of the 2nd PCIe packet comprises complete Ethernet data bag, primary processor can directly extract this Ethernet data bag to obtain the second Ethernet data bag; Perhaps, if the payload of the 2nd PCIe packet comprises the payload of Ethernet data bag, the payload that primary processor can extract this Ethernet data bag encapsulates to obtain the second Ethernet data bag.

S406, primary processor are transmitted this second Ethernet data bag by network interface to other veneers.

The server veneer implementation method that the embodiment of the invention provides, this server veneer is applied to server system, this server system also comprises at least one other veneer that is connected with this server veneer, this server veneer specifically comprises the PCIe interchanger, primary processor and a plurality of from processor, wherein, the PCIe interchanger comprises a uplink port and a plurality of downlink port; Primary processor links to each other with the uplink port of this PCIe, a plurality ofly links to each other with the downlink port of this PCIe interchanger respectively from processor.Adopt a kind of like this server veneer of structure, primary processor can carry out the transmitting-receiving of data by network interface and other veneers, this primary processor is connected from processor with each by the PCIe interchanger again, therefore, all can finish by primary processor from transmitting-receiving and each exchange from data between the processor of processor data.So, need not to adopt multistage tree structure just can realize interconnection between the full processor, thereby avoided data between the multistep treatment device, to transmit, reduced the time-delay of server veneer, improved the quality of network service.

Further, as shown in Figure 5, the server veneer implementation method that the embodiment of the invention provides comprises:

S501, primary processor initialization PCIe interchanger are so that this PCIe interchanger can work.

Concrete, in the initialized process of PCIe interchanger, primary processor can for link to each other with this PCIe interchanger each from the processor distribution routing iinformation.

S502, primary processor generation pass allocation list, this path configuration table comprise from processor flag and with this from routing iinformation corresponding to processor flag, wherein, with this from routing iinformation corresponding to processor flag be that the indicated routing iinformation from processor distribution of this processor flag is identical.

S503, primary processor receive the first Ethernet data bag that other veneers send by network interface.

S504, primary processor change into a PCIe packet with this first Ethernet data bag.

Concrete, primary processor can with in the payload of this first Ethernet data bag overall package to the PCIe packet or primary processor can extract payload in this first Ethernet data bag, the payload in this first Ethernet data bag is encapsulated in the payload of a PCIe packet; According to this path configuration table and from the obtaining with this from the first routing iinformation corresponding to processor from processor flag of processor, this first routing iinformation is added to the head of a PCIe packet.

S505, the primary processor uplink port by the PCIe interchanger with a PCIe package forward to the PCIe interchanger so that this PCIe interchanger according to the first routing iinformation in the PCIe packet head with a PCIe package forward give link to each other with downlink port from processor.

Concrete, primary processor can pass through table look-up module 25 query path allocation lists, obtains one or more described routing iinformations from processor according to this path configuration table.

For example, record each in the path configuration table from the identity information of processor, this identity information can be from the residing bus ID of processor or this MAC (Medium Access Control from processor, media access control layer) address, each is from all corresponding default routing iinformation of identity information of processor, primary processor is before transmitting a PCIe packet by the PCIe interchanger, can be by the routing iinformation accessed path allocation list of a PCIe packet data recording, obtain one or more routing iinformations from processor according to this path configuration table, give a PCIe package forward one or more from processor by the PCIe interchanger.

Certainly, a plurality of from carrying out according to this path configuration table the exchange of data equally between the processor.For example, finish the initialization of PCIe interchanger and generation pass allocation list after the scanning of processor at primary processor, and this path configuration table is issued to each from processor, when first need to be to second during from the processor forwarding data from processor, can be with this Packet Generation to the PCIe interchanger, be added with this second identity information from processor in the packet of this forwarding, the PCIe interchanger can the query path allocation list, thus according to second from the identity information of processor determine this second from the routing iinformation of processor in order to finish the forwarding of data.

S506, primary processor receive from processor by the PCIe interchanger and send load request.

S507, primary processor are according to this load request read operation system and application program image file.

Concrete, after primary processor receives load request, primary processor will be from storage medium read operation system and application program image file.Storage medium specifically can comprise Flash (flash memory), SATA (serial advanced technology attachment, Serial Advanced Technology Attachment), SAS (Serial Attached SCSI, interface connected in series) hard disk or SSD (solid state disk, solid state hard disc), this storage medium can be used for the image file of storage operating system and application program

S508, primary processor are sent to the operating system image file that reads from processor by the PCIe interchanger, so that should start the operating system according to the operating system image file from processor.

In embodiments of the present invention, each application program of moving from processor can be Dynamical Deployment, and the user can be for different application, by primary processor the mode of operation from processor respectively is configured.From between the processor being the cluster relation, respectively from processor operation operating system and application program separately.Also move oneself operating system and application program on the primary processor.Such as: first is computing function from processor operation, second from the processor operation be memory function, these two can cooperatively interact from processor and to finish a specific business function.Need to can directly finish exchanges data by the PCIe interchanger when being responsible for the fetching data from processor of storage when what be responsible for to calculate from processor, namely exchanges data is finished in this locality, so not only can reduce time-delay but also on the not impact of outside bandwidth of network.

So, can be in advance the image file of operating system and application program be placed in the storage medium of primary processor, in the time need to loading from processor, only this image file need to be taken out to be sent to from processor from the storage medium of primary processor and get final product, thereby can be so that each need not to provide for oneself operating system and application program from processor, save the internal memory from processor, improved the treatment effeciency from processor.

Whether S509, primary processor, normally connect to detect from processor to send online detect-message from processor by the PCIe interchanger.

S510, when determining one during from the processor connection failure, primary processor will be sent to this packet from processor according to default sending strategy and be sent to another from processor by the PCIe interchanger; When determining to recover to connect from processor, be forwarded to described from processor with being sent to another packet from processor by described PCIe interchanger.

When connection failure, illustrate from processor fault (the perhaps link failure between two primary processors) to have occurred, therefore need to forward the data to other from processor so that data are processed.Here " default sending strategy " specifically do not limit, for example, can predefined good certain from processor for the treatment of other from the data of processor (or link) when being out of order, if other break down from processor (or link), then primary processor is given to processing from processor to this special use with data; Perhaps " default sending strategy " also can be " the sending from the processor load situation according to each " of presetting strategy (as with Packet Generation to load few from processor).

For example, primary processor and respectively from having heartbeat detection mechanism between the processor, whether primary processor will regularly normally connect to detect from processor to respectively sending the creed detection messages from processor.Lose from the heartbeat of processor when first, primary processor with first from the processor business migration to the second from processor or other for subsequent use from processor.

S511, primary processor receive the 2nd PCIe packet that sends from processor by the PCIe interchanger.

S512, primary processor change into the second Ethernet data bag with the 2nd PCIe packet.

S513, primary processor are transmitted this second Ethernet data bag by network interface to other veneers.

S514, primary processor receive the 3rd PCIe packet that one of them sends from processor by the PCIe interchanger, and by the PCIe interchanger with the 3rd PCIe package forward to another from processor.

A kind of like this server veneer implementation method need not to adopt multistage tree structure just can realize interconnection between the full processor, thereby has avoided data to transmit between the multistep treatment device, has reduced the time-delay of server veneer, has improved network service quality.

One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.

The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.

Claims

1. a server veneer is applied to server system, and described server system also comprises at least one other veneer that is connected with described server veneer, it is characterized in that, described server veneer comprises:

2. server veneer according to claim 1 is characterized in that:

Described primary processor also is used for, and receives one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger, and gives another described from processor described the 3rd PCIe package forward by described PCIe interchanger.

3. arbitrary described server veneer according to claim 1 and 2 is characterized in that, described primary processor is used for that described the 2nd PCIe packet is changed into the second Ethernet data bag and is specially:

4. arbitrary described server veneer is characterized in that according to claim 1-3, and described primary processor also is used for, generation pass allocation list, described path configuration table comprise from processor flag and with described from routing iinformation corresponding to processor flag;

Described primary processor is used for:

5. arbitrary described server veneer is characterized in that according to claim 1-4, and described primary processor also is used for:

6. arbitrary described server veneer is characterized in that according to claim 1-5, and described primary processor also is used for:

7. server veneer according to claim 6 is characterized in that, when determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

8. server veneer implementation method, described server veneer is applied to server system, and described server system also comprises at least one other veneer that is connected with described server veneer, it is characterized in that, comprising:

9. method according to claim 8 is characterized in that, described method also comprises:

10. according to claim 8 or 9 arbitrary described methods, it is characterized in that, described primary processor changes into the second Ethernet data bag with described the 2nd PCIe packet and comprises:

11. arbitrary described method is characterized in that according to claim 8-10, described method also comprises:

12. arbitrary described method is characterized in that according to claim 8-11, described method also comprises:

13. arbitrary described method is characterized in that according to claim 8-12, described method also comprises:

Whether described primary processor sends online detect-message to described from processor by described PCIe interchanger, describedly normally connect from processor to detect;

14. method according to claim 13 is characterized in that, when determining described one when recovering to connect from processor, be sent to described another from the described packet of processor by described PCIe interchanger be forwarded to described one from processor.

15. a primary processor is applied to the server veneer, it is characterized in that, described primary processor comprises:

16. primary processor according to claim 15 is characterized in that:

Described the first sending module, concrete be used for by the PCIe interchanger uplink port with a described PCIe packet via the PCIe interchanger send to link to each other with the downlink port of described PCIe interchanger from processor;

17. arbitrary described primary processor is characterized in that according to claim 15-16,

Described the second receiver module also is used for receiving one of them described the 3rd PCIe packet that sends from processor by described PCIe interchanger;

18. arbitrary described primary processor is characterized in that according to claim 15-17, described primary processor also comprises:

Described the first modular converter comprises:

19. arbitrary described primary processor is characterized in that according to claim 15-18, also comprises:

The 3rd receiver module is used for receiving the described load request that sends by described PCIe interchanger from processor, according to described load request read operation system and application program image file;

20. arbitrary described primary processor is characterized in that according to claim 15-19, described primary processor also comprises: