CN103035779A

CN103035779A - Photovoltaic device

Info

Publication number: CN103035779A
Application number: CN2012102735037A
Authority: CN
Inventors: 金英水; 李斗烈; 金永镇; 牟灿滨; 朴映相
Original assignee: Samsung SDI Co Ltd
Current assignee: Samsung SDI Co Ltd
Priority date: 2011-10-06
Filing date: 2012-08-02
Publication date: 2013-04-10

Abstract

A photovoltaic device, and a method of fabricating the same are provided. Here, a base portion and an emitter portion are formed on a surface of a semiconductor substrate. An insulation layer is formed on the base portion and the emitter portion. The insulation layer has a plurality of vias to partially expose the base portion and the emitter portion. A first electrode is formed to contact a region of the emitter portion through at least one of the vias, and a second electrode is formed to contact a region of the base portion through at least another one of the vias. Then, a dicing line is set at a bus electrode portion of the second electrode, and the semiconductor substrate is split into at least two photovoltaic devices at the base portion along the dicing line.

Description

Photovoltaic devices

The application requires rights and interests and the priority at the 61/544th, No. 111 U.S. Provisional Application of United States Patent (USP) trademark office submission on October 6th, 2011, and whole disclosures of above-mentioned application are contained in this by reference.

Technical field

One or more embodiment of the present invention relates to photovoltaic devices.

Background technology

In order to make photovoltaic devices, by being doped in the p-type substrate (or N-shaped substrate), N-shaped impurity (or p-type impurity) forms p-n junction, therefore, form emitter.The electron-hole pair that forms via the reception of light is separated.Here, collect electronics by the electrode in the N-shaped zone, and collect the hole by the electrode in the p-type zone.Therefore, produce electric power.

Photovoltaic devices can have such structure, that is, electrode is arranged in as on the front surface of optical receiving surface and be arranged on the rear surface.Here, if on front surface, then receiving the area of light, arrangement of electrodes reduced the nearly area of electrode.Reduce problem in order to solve area, adopt electrode only to be arranged in back-contact structure on the rear surface of substrate.

Summary of the invention

The many aspects of embodiments of the invention relate to photovoltaic devices and make the method for described photovoltaic devices.

Embodiments of the invention relate in one aspect to a kind of method of making photovoltaic devices, wherein, partly locate (that is, partly locating in the base stage of semiconductor wafer) in the base stage of semiconductor base line of cut be set, and along the substrate of line of cut cutting semiconductor.

Embodiments of the invention relate in one aspect to a kind of photovoltaic devices, described photovoltaic devices have the contact photovoltaic devices emitter portion the zone the first electrode and contact second electrode in the base stage zone partly of photovoltaic devices.Here, the second electrode is the electrode that is cut, and photovoltaic devices only has two angle parts that are trimmed at its emitter portion place.

Embodiments of the invention provide a kind of method of making photovoltaic devices.Described method comprises: form the semiconductor base with first surface and second surface, described second surface relatively deviates from described first surface; Form base stage part and emitter portion at described first surface place; Form insulating barrier in described base stage part and described emitter portion; In described insulating barrier, form a plurality of through holes, partly to expose described base stage part and described emitter portion; Form the first electrode, to contact the zone of described emitter portion by at least one through hole; Form the second electrode, to contact the zone of described base stage part by another through hole at least; Partly locate to set line of cut in described base stage; And cut described semiconductor base along described line of cut.

In one embodiment, the step of setting line of cut comprises: partly locate and set described line of cut away from described emitter portion in described base stage; And the step of cutting semiconductor substrate comprises: the location away from described emitter portion at described semiconductor base is cut described semiconductor base.

In one embodiment, the step that forms the first electrode comprises: the first electrode that forms a plurality of the first finger electrodes that comprise the first busbar and extend from described the first busbar; And the step that forms the second electrode comprises: form the second electrode that comprises the second busbar and a plurality of the second finger electrodes, described the second busbar is arranged to across the center of described first surface and extends, and described a plurality of the second finger electrodes are from described the second busbar extension and alternate each other with described the first finger electrode.In addition, the step of partly locating to set line of cut in base stage can comprise: form the opening that extends across the center of described the second busbar, to become described line of cut.

In one embodiment, the step of formation semiconductor base comprises: assign to form described semiconductor base from single semiconductor wafer by at least two bights of repairing described semiconductor wafer.Here, can form a plurality of photovoltaic devices from described single semiconductor wafer.In addition, the step that forms the first electrode can comprise: the first electrode that is formed on a plurality of the first finger electrodes that comprise the first busbar in each photovoltaic devices and extend from described the first busbar in each photovoltaic devices; And the step that forms the second electrode can comprise: the second electrode that forms a plurality of the second finger electrodes comprise the second busbar and to extend from described the second busbar in each photovoltaic devices.

In one embodiment, described method also comprises: form at least one in passivation layer and the antireflection layer at the described second surface place of described semiconductor base.

In one embodiment, described method also comprises: with the described second surface veining of described semiconductor base.

In one embodiment, each in described base stage part and the described emitter portion is formed and has strip.

In one embodiment, each in described base stage part and the described emitter portion is formed a plurality of zone of dispersions.Here, each zone of dispersion can have a shape, ellipse, circle or polygonal shape.

In one embodiment, described second surface is formed the front surface that is configured in the face of light source, and described first surface is formed the rear surface that is configured to deviate from described light source.

Embodiments of the invention provide a kind of photovoltaic devices.Described photovoltaic devices comprises: semiconductor base, have first surface and second surface, and described second surface relatively deviates from described first surface; Base stage part and emitter portion are positioned at described first surface place; Insulating barrier is positioned on described base stage part and the described emitter portion, and described insulating barrier has a plurality of through holes; The first electrode contacts the zone of described emitter portion by at least one through hole; And second electrode, contact the zone of described base stage part by another through hole at least.Here, described the second electrode is the electrode that is cut, and described semiconductor base only has the angle part of two finishings at described emitter portion place.

In one embodiment, described semiconductor base is formed by semiconductor wafer, and is only about half of (1/2) of the size of described semiconductor wafer.Here, the part of described the second electrode can be extended across the center of described semiconductor wafer.

In one embodiment, described the first electrode comprises the first busbar that extends along the first edge of described semiconductor base and a plurality of the first finger electrodes that extend from described the first busbar between described two angle parts that are trimmed; And described the second electrode comprise the second busbar of extending along the second edge relative with described the first edge and from described the second busbar extend and with described the first finger electrode alternate a plurality of the second finger electrodes each other.

In one embodiment, described photovoltaic devices also comprises: at least one in passivation layer and the antireflection layer is positioned at the described second surface place of described semiconductor base.

In one embodiment, each in described base stage part and the described emitter portion is formed a plurality of zone of dispersions.

In one embodiment, described insulating barrier comprises the second layer that ground floor and material are different from described ground floor.

Description of drawings

Figure 1A is the perspective schematic view according to the photovoltaic devices of the embodiment of the invention;

Figure 1B is the cutaway view along the IB-IB line intercepting of Figure 1A;

Fig. 2 A is the rearview according to the photovoltaic devices of the embodiment of the invention, shows the first metal electrode and the second metal electrode, emitter layer and base layer;

Fig. 2 B is the rearview of photovoltaic devices according to another embodiment of the present invention, shows the first metal electrode and the second metal electrode, emitter layer and base layer;

Fig. 3 A is the perspective view of semiconductor base during making the technique of photovoltaic devices according to the embodiment of the invention;

Fig. 3 B is that basis is at the perspective view of the semiconductor base of the modification of the embodiment shown in Fig. 3 A;

Fig. 4 is the perspective view that forms the state of passivation layer and antireflection layer during the technique of making photovoltaic devices according to the embodiment of the invention;

Fig. 5 A is the perspective view that forms the state of passivation layer and antireflection layer during the technique of making photovoltaic devices according to the embodiment of the invention;

Fig. 5 B is the cutaway view along the VB-VB line intercepting of Fig. 5 A;

Fig. 6 A is the perspective view that forms the state of insulating barrier during the technique of making photovoltaic devices according to the embodiment of the invention;

Fig. 6 B is the cutaway view along the VIB-VIB line intercepting of Fig. 6 A;

Fig. 7 A is the perspective view that forms the state of the first metal electrode and the second metal electrode during the technique of making photovoltaic devices according to the embodiment of the invention;

Fig. 7 B is the cutaway view along the VIIB-VIIB line intercepting of Fig. 7 A;

Fig. 7 C is the rearview of Fig. 7 A;

Fig. 8 A be according to the embodiment of the invention during making the technique of photovoltaic devices along the perspective view of the state of the line of cut C-C cutting semiconductor substrate of Fig. 7 A;

Fig. 8 B is the rearview of Fig. 8 A;

Fig. 9 A and Fig. 9 B show the result who uses laser beam induced current (LBIC) method to measure the quantum efficiency (QE) of contrast back-contact photovoltaic devices;

Figure 10 shows the embodiment according to the electrical interconnection photovoltaic devices of the embodiment of the invention;

Figure 11 shows the according to another embodiment of the present invention embodiment of electrical interconnection photovoltaic devices;

Figure 12 shows the according to another embodiment of the present invention embodiment of electrical interconnection photovoltaic devices.

Embodiment

Now, the present invention is described hereinafter with reference to the accompanying drawings more fully, exemplary embodiment of the present invention shown in the drawings.Yet the present invention can implement with many different forms, and should not be understood to the embodiment that is confined in this proposition; To make the disclosure will be thoroughly and complete and provide these embodiment, and will convey to fully those skilled in the art to scope of the present invention.Term used herein only is in order to describe the purpose of specific embodiment, and is not intended to limit the present invention.As used herein, unless context explicitly points out in addition, otherwise " one (kind) " of singulative and " described (being somebody's turn to do) " also are intended to comprise plural form.It will also be understood that, when using in this manual term " to comprise " and/or when " comprising ", illustrate to have described feature, integral body, step, operation, element and/or assembly, do not exist or additional one or more further features, integral body, step, operation, element, assembly and/or their group but do not get rid of.Although can use this type of terms such as " first ", " second " to describe different assemblies, these assemblies are not subjected to the restriction of above-mentioned term.That is, above-mentioned term can only be used for an assembly and another assembly are distinguished.Identical label represents identical element all the time.

In the accompanying drawings, for the sake of clarity, can exaggerate the layer and the zone thickness.Will be appreciated that when element or the layer be known as " " another element or the layer " on " time, this element or the layer can directly on another element, perhaps can between them, arrange one or more intermediate layers or intermediary element.On the contrary, when element be known as " directly existing " another element or the layer " on " time, do not have intermediary element or intermediate layer.

Figure 1A is the perspective schematic view according to the photovoltaic devices of the embodiment of the invention, and Figure 1B is the cutaway view along the IB-IB line intercepting of Figure 1A.Fig. 2 A is the rearview according to the photovoltaic devices of the embodiment of the invention, show the first metal electrode and the second metal electrode, emitter layer and base layer, Fig. 2 B is the rearview of photovoltaic devices according to another embodiment of the present invention, shows the first metal electrode and the second metal electrode, emitter layer and base layer.

For the ease of explaining, the rear surface that Figure 1A and Figure 1B show photovoltaic devices facing up, Fig. 2 A and Fig. 2 B show and are doped with impurity and make with dashed lines form the zone of emitter layer (part) and base layer (part).

With reference to Figure 1A and Figure 1B, photovoltaic devices 100 comprises semiconductor base 110, passivation layer 120, antireflection layer 130, emitter layer (emitter portion) 140, base layer (base stage part) 150, insulating barrier 160 and the first metal electrode 170 and the second metal electrode 180.

Semiconductor base 110 is light absorbing zones.Here, the edge of the first side 111 of semiconductor base 110 is trimmed (trim), and the edge of the second side 112 of semiconductor base is not trimmed.Usually, four of semiconductor base edges are trimmed.Yet according to embodiments of the invention, semiconductor base 110 is corresponding to half of general semiconductor base, and wherein, only two edges in four edges (that is, only the edge of two of the first side 111 opposite ends) is trimmed.The size of semiconductor base 110 can be 5 " wafer or 6 " wafer half or larger.

Semiconductor base 110 can comprise monocrystal silicon substrate or polysilicon substrate.Semiconductor base 110 can be monocrystal silicon substrate or the polysilicon substrate that is doped with N-shaped impurity.N-shaped impurity can comprise V group element, for example phosphorus (P) and arsenic (As).

Although adopt the semiconductor base 110 that is doped with N-shaped impurity in current embodiment, current embodiment is not limited to this.For example, semiconductor base 110 can be monocrystal silicon substrate or the polysilicon substrate that is doped with p-type impurity.P-type impurity can comprise III family element, for example boron (B), aluminium (Al) or gallium (Ga).

Although not shown, semiconductor base 110 can comprise textured structure (textured structure).Textured structure can reduce the incident reflection of light by using from the internal reflection of the rear surface of semiconductor base 110, improves light in the length of semiconductor base 110 interior propagation, and improves light absorbing amount.Therefore, can improve the short circuit current of photovoltaic devices 100.

Passivation layer 120 can be formed on the front surface of semiconductor base 110.Passivation layer 120 can comprise the amorphous silicon (a-Si) that is doped with impurity, perhaps can comprise silicon nitride (SiN _x).Comprise at passivation layer 120 in the situation of the a-Si that is doped with impurity, passivation layer 120 can have the impurity that has the identical conduction type with the impurity of semiconductor base 110 with the high doped in concentrations profiled of concentration than the impurity of semiconductor base 110.

Passivation layer 120 can be by stopping or preventing that the surface recombination of the charge carrier of generation in semiconductor base 110 from improving the efficient of carrier collection.For example, because preventing charge carrier, passivation layer 120 shifts to the front surface of semiconductor base 110, so passivation layer 120 can prevent near the compound and consumption front surface of semiconductor base 110 of electronics and hole.

Antireflection layer 130 is formed on the front surface of semiconductor base 110, and can improve by the optical absorption loss of the photovoltaic devices 100 that prevents from causing because of the light during the incident of sunlight reflection the efficient of photovoltaic devices 100.Antireflection layer 130 can comprise transparent material.For example, antireflection layer 130 can comprise silica (SiO _x), silicon nitride (SiN _x) or silicon oxynitride (SiO _xN _y).Alternatively, antireflection layer 130 can comprise titanium oxide (TiO _x), zinc oxide (ZnO) or zinc sulphide (ZnS).Can form antireflection layer 130 by stacking single layer or a plurality of layers with different refractivity.

Although in the current embodiment that illustrates, passivation layer 120 and antireflection layer 130 are expressed as independently layer, the invention is not restricted to this.For example, silicon nitride (SiN _x) layer can be formed both effects of passivation layer 120 and antireflection layer 130 of playing.

Emitter layer 140 is formed on the rear surface of semiconductor base 110, and forms p-n junction with semiconductor base 110.In the situation that semiconductor base 110 is doped with N-shaped impurity, emitter layer 140 comprises p-type impurity.In the situation that semiconductor base 110 is doped with p-type impurity, emitter layer 140 comprises N-shaped impurity.

With reference to Fig. 2 A, form emitter layer 140 by p-type impurity (or N-shaped impurity) is doped to semiconductor base 110, and diffusion zone can be bar shaped.That is, in one embodiment, emitter layer (emitter portion) 140 is formed has bar shaped.

Alternatively, with reference to Fig. 2 B, diffusion zone (emitter portion) 140' of p-type impurity (or N-shaped impurity) has circular or oval-shaped vertex type.The diffusion zone 140' of vertex type can also have polygonal shape.That is, in one embodiment, emitter portion 140' is formed a plurality of zone of dispersions.Here, in one embodiment, each zone of dispersion 140' has a shape, ellipse, circle or polygonal shape, represents such as the dotted line among Fig. 2 B.

Return with reference to Figure 1A, Figure 1B and Fig. 2 A, emitter layer 140 forms along first side 111 with two finished edge of semiconductor base 110, and forms along the direction perpendicular to the first side 111.That is, in one embodiment, emitter layer 140 comprises along the first emitter zone 141 that the first side 111 forms with along a plurality of the second emitter zones 142 that the direction that is substantially perpendicular to the first emitter zone 141 forms.The second emitter zone 142 is spaced.

Base layer 150 is formed on the rear surface of semiconductor base 110, and comprises the impurity of the same type with the impurity phase of semiconductor base 110.Base layer 150 has impurity with the high doped in concentrations profiled of concentration than the impurity of semiconductor base 110, forming back surface field (BSF), thereby can prevent near the compound and consumption the second metal electrode 180 of hole and electronics.

With reference to Fig. 2 A, form base layer (base stage part) 150 by N-shaped impurity (or p-type impurity) is doped to semiconductor base 110, and diffusion zone can be stripe shape.That is, in one embodiment, base layer (base stage part) 150 is formed has strip.

Alternatively, with reference to Fig. 2 B, the diffusion zone 150' of N-shaped impurity (or p-type impurity) has circular or oval-shaped vertex type.The diffusion zone 150' of vertex type can also have polygonal shape.That is, in one embodiment, diffusion zone (base stage part) 150' is formed a plurality of zone of dispersions.Here, in one embodiment, each zone of dispersion 150' has a shape, ellipse, circle or polygonal shape, represents such as the dotted line among Fig. 2 B.

With reference to Figure 1A, Figure 1B and Fig. 2 A, base layer 150 forms along second side 112 with two unfinished edges of semiconductor base 110, and forms along the direction perpendicular to the second side 112.That is, in one embodiment, base layer 150 comprises along the first matrix region 151 that the second side 112 forms and a plurality of the second matrix regions 152 that form along the direction that is substantially perpendicular to the first matrix region 151.

The second matrix region 152 is arranged between the second spaced emitter zone 142.Therefore, the 142 and second matrix region 152, the second emitter zone is formed on the rear surface of semiconductor base 110 alternate each other.

Insulating barrier 160 is formed on emitter layer 140 and the base layer 150, and below the first metal electrode 170 and the second metal electrode 180, is short-circuited to prevent (or protection) between the assembly with films of opposite conductivity (opposite polarity) (or avoiding).For example, insulating barrier 160 prevents the electrical short between the first metal electrode 170 and the base layer 150, and prevents the electrical short between the second metal electrode 180 and the emitter layer 140.

Insulating barrier 160 comprises through hole (for example, through hole) 165, via (by) through hole 165, the first metal electrodes 170 can directly contact respectively emitter layer 140 and base layer 150 with the second metal electrode 180.Emitter layer 140, the second metal electrodes 180 can be electrically connected to by through hole 165, the first metal electrodes 170 and base layer 150 can be electrically connected to.

Insulating barrier 160 can comprise the first insulating barrier 161 and the second insulating barrier 162.For example, the first insulating barrier 161 can comprise silica (SiO _x), silicon nitride (SiN _x) or SiO _xAnd SiN _xBoth.The second insulating barrier 162 is formed for guaranteeing electric insulation (or being used for firmer) after forming the first insulating barrier 161, and can comprise polyimides (PI).Alternatively, the second insulating barrier 162 can comprise ethylene vinyl acetate (EVA), polyethylene terephthalate (PET) or Merlon (PC).

Although in current embodiment, insulating barrier 160 comprises the first insulating barrier 161 and the second insulating barrier 162, the invention is not restricted to this.The second insulating barrier 162 is used for guaranteeing electric insulation after can being formed in and forming the first insulating barrier 161, and can is that optionally therefore, insulating barrier 160 can only comprise the first insulating barrier 161.

The first metal electrode 170 is arranged on the insulating barrier 160 with corresponding to emitter layer 140, and can be electrically connected to emitter layer 140 by through hole 165.The first metal electrode 170 can comprise silver (Ag), gold (Au), copper (Cu), aluminium (Al) or their alloy.The first metal electrode 170 can comprise that the first busbar 171 and the first finger electrode 172, the first finger electrodes 172 are formed from the first busbar 171 and extend (for example, being formed vertical with respect to the first busbar 171).

The second metal electrode 180 is arranged on the insulating barrier 160 with corresponding to base layer 150, and can be electrically connected to base layer 150 by through hole 165.The second metal electrode 180 can comprise silver (Ag), gold (Au), copper (Cu), aluminium (Al) or their alloy.The second metal electrode 180 can comprise that the second busbar 181 and the second finger electrode 182, the second finger electrodes 182 are formed from the second busbar 181 and extend (for example, being formed vertical with respect to the second busbar 181).

The first busbar 171 is formed on the first side 111 places of semiconductor base 110, and the second busbar 181 is formed on the second side 112 places of semiconductor base 110, thereby is arranged essentially parallel to the first busbar 171.The first finger electrode 172 extends towards the second busbar 181 along the direction perpendicular to the first busbar 171, and the second finger electrode 182 extends towards the first busbar 171 along the direction perpendicular to the second busbar 181.The first finger electrode 172 and the second finger electrode 182 are alternately arranged.In other words, the first finger electrode 172 and the second finger electrode 182 can be formed alternate each other, and collect charge carrier.

In the situation of making general back-contact photovoltaic devices, even light receiving area increases, but when electric current increases according to the increase of light receiving area, still cause square proportional power loss to electric current, therefore, the gain that increases with respect to area can be enough not large.Yet according to embodiments of the invention, by wafer being cut in half to form photovoltaic devices, therefore, voltage can be approximately double, and can reduce electric current.Therefore, can reduce square proportional power loss to electric current.For example, in one embodiment, the second electrode 180 is the electrodes that are cut.That is, in one embodiment, can be by larger busbar is cut into the second busbar 181 that two parts form the second electrode 180, as below describing in more detail.

In addition, because make the photovoltaic devices according to the embodiment of the invention by the zone (that is, the zone away from emitter portion of cutting base stage part) of cutting base stage part, so can reduce or prevent the power loss during the manufacturing of photovoltaic devices.

Hereinafter, will method that make photovoltaic devices be described.

Fig. 3 A to Fig. 8 B schematically shows the state according to the method for the manufacturing photovoltaic devices of the embodiment of the invention.For the ease of explaining, the rear surface that Fig. 3 A to Fig. 8 B shows photovoltaic devices facing up.

With reference to Fig. 3 A, provide semiconductor base (for example, semiconductor wafer) 310.Four edges of finishing semiconductor base 310, the size of semiconductor base (wafer) 310 can be 5 inches, 6 inches or larger.As example, in one embodiment, utilize 5 inches, 6 inches or larger single semiconductor wafer to form a plurality of photovoltaic devices.Yet therefore the present invention is not restricted, and can utilize semiconductor wafer or the substrate of other suitable type or quantity.

Semiconductor base 310 can comprise monocrystal silicon substrate or polysilicon substrate.Semiconductor base 310 can be monocrystal silicon substrate or the polysilicon substrate that is doped with N-shaped impurity or p-type impurity.In current embodiment, for the ease of explaining, description semiconductor base 310 is comprised the situation of N-shaped impurity.

Can carry out the clean operation that uses acid solution or aqueous slkali, invest physical impurity and/or the chemical impurity on the surface of semiconductor base 310 with removal.

With reference to Fig. 3 B, semiconductor base 310' can have the rough surface that forms in the veining operation according to another embodiment of the present invention.Can form texture structure via anisotropy wet etching or plasma dry etch.The rough surface that can form in the veining operation forms passivation layer and the antireflection layer that the following describes.

Hereinafter, for the ease of explaining, description is used the technique of making photovoltaic devices at the semiconductor base 310 shown in Fig. 3 A.

With reference to Fig. 4, on the front surface of semiconductor base 310, form in the following order passivation layer 320 and antireflection layer 330.Before forming passivation layer 320, can clean semiconductor substrate 310.

Passivation layer 320 can comprise the a-Si that is doped with impurity.For example, passivation layer 320 can be formed on the front surface of semiconductor base 310 as high concentration n+ layer, passivation layer 320 can form front surface field (FSF), to reduce the compound loss that causes owing to hole and electronics.

According to another embodiment of the present invention, passivation layer 320 can comprise silicon nitride (SiN _x).Can form passivation layer 320 by using plasma enhanced chemical vapor deposition (PECVD) method.

Because passivation layer 320 is formed on the optical receiving surface of semiconductor base 310, so can regulate band gap to reduce light absorption.For example, can add additive, with the raising band gap, thereby reduce light absorption, thereby make in the inside of more incident light through semiconductor base 310.

Antireflection layer 330 can pass through the method for utilization such as CVD, sputter or spin coating by silica (SiO _x), silicon nitride (SiN _x) or silicon oxynitride (SiO _xN _y) form.For example, antireflection layer 330 can be formed single silica (SiO _x) layer, single silicon nitride (SiN _x) layer or single silicon oxynitride (SiO _xN _y) layer or comprise silica (SiO _x), silicon nitride (SiN _x), silicon oxynitride (SiO _xN _y) composite bed.

Although in current embodiment, passivation layer 320 and antireflection layer 330 are formed independently layer, the invention is not restricted to this.For example, passivation layer 320 and antireflection layer 330 can be used as single layer and form.In other words, silicon nitride (SiN _x) layer can be formed for passivation and antireflective.

With reference to Fig. 5 A and Fig. 5 B, form base layer (base stage part) 350 and emitter layer (emitter portion) 340 in the rear surface of semiconductor base 310.Can form base layer 350 and emitter layer 340 in the semiconductor base 310 by impurity is doped to strips.

According to embodiments of the invention, the zones of different that can be doped to by the impurity with films of opposite conductivity the rear surface of semiconductor base 310 forms base layer 350 and emitter layer 340.At first, can N-shaped impurity be doped to across the central area of the rear surface of semiconductor base 310 and form the first matrix region 351 in the semiconductor base 310, and can N-shaped impurity be doped to along the direction perpendicular to the first matrix region 351 and form the second matrix region 352 in the semiconductor base 310.Here, the second matrix region 352 that is doped with N-shaped impurity is formed spaced setting or predetermined interval.

Next, can form emitter layer 340 by p-type impurity being doped in the remaining zone (that is, the zone except the zone that is doped with N-shaped impurity).Therefore, two different sides around a zone of base layer 350 form the zone of emitter layer 340, emitter layer 340 comprises the first emitter zone 341 and is substantially perpendicular to the second emitter zone 342 in the first emitter zone 341, wherein, the second emitter zone 342 is formed alternate each other with the second matrix region 352.

According to another embodiment of the present invention, base layer 350 is formed the whole rear surface that covers semiconductor base 310, then can be by forming emitter layer 340 in a plurality of parts that impurity optionally are doped to base layer 350.For example, after the whole rear surface with N-shaped impurity doped semiconductor substrate 310, can be with a plurality of zones of the rear surface of the p-type impurity doped semiconductor substrate 310 of high concentration, to form emitter layer (part) 340.Here, the zone that is doped with the p-type impurity of high concentration is illustrated as emitter layer 340 in Fig. 5 A.

Although base layer 350 and emitter layer 340 are stripe shape doped regions, also can be in zone of dispersion impurity (for example, to form a some shape).In the situation of impurity in zone of dispersion (for example, to have a shape), matrix doped region and emitter doped region such as top described with reference to Fig. 2 B.

With reference to Fig. 6 A and Fig. 6 B, form insulating barrier 360 at base layer 350 and emitter layer 340.Insulating barrier 360 can be formed and comprise two layers.For example, comprising silica (SiO by utilizing the CVD method to form _x) and silicon nitride (SiN _x) the first insulating barrier 361 after, can form the second insulating barrier 362, to improve electric insulation.

The second insulating barrier 362 can comprise polyimides (PI).Alternatively, the second insulating barrier 162 can comprise ethylene vinyl acetate (EVA), polyethylene terephthalate (PET) or Merlon (PC)

Next, in insulating barrier 360, form through hole (for example, through hole) 365, partly to expose base layer 350 and emitter layer 340(referring to Fig. 7 B).Although not shown, the part that can expose by the etched mask that forms etching mask (not shown) and etching isolation layer 360 at insulating barrier 360 forms through hole 365.

Base layer 350 can via (by) some through holes in a plurality of through holes 365 partly expose, emitter layer 340 can via (by) remaining through hole 365 partly exposes.The electrical connection that some through holes 365 are used between emitter layer 340 and the first metal electrode 370, and the electrical connection that remaining through hole 365 is used between base layer 350 and the second metal electrode 380.

With reference to Fig. 7 A to Fig. 7 C, form the first metal electrode 370 and the second metal electrode 380.

Place, two opposite ends in the rear surface of semiconductor base 310 forms the first metal electrode 370.The emitter layer 340 of at least a portion contact doping of the first metal electrode 370.The first metal electrode 370 includes the first busbar 371 and from the first busbar 371(for example is formed, along the direction perpendicular to the first busbar 371) the first finger electrode 372 of extending.

The second metal electrode 380 is formed on the center of the rear surface of semiconductor base 310.For example, the second metal electrode 380 comprises across the second busbar 381 of the center arrangement of semiconductor base 310 and is formed on two opposite sides around the second busbar 381 and the second finger electrode 382 that extends towards the first metal electrode 370.For example, the second finger electrode 382 extends along the direction that is substantially perpendicular to the second busbar 381.The second finger electrode 382 can be formed with the first finger electrode 372 alternate and collect charge carrier each other.

The pattern that can be formed by the electroconductive paste that comprises silver (Ag), gold (Au), copper (Cu), aluminium (Al) or nickel (Ni) by silk screen printing also carries out hot baked with pattern and forms the first metal electrode 370 and the second metal electrode 380.

According to another embodiment of the present invention, can form the first metal electrode 370 and the second metal electrode 380 by plating.Form by (via) after the Seed Layer of through hole (for example, through hole) 365 contact emitter layer 340 and base layer 350, can be with metal deposition on Seed Layer.

In one embodiment of the invention, when forming the second metal electrode 380, form along its length at opening (for example, the hole) h(of the center of the second busbar 381 referring to Fig. 7 A and Fig. 7 C).For example, in one embodiment, in the forming process of the second metal electrode 380, apply paste or metal lining in the location except the zone corresponding with opening h, thereby do not form metal in the center of the second busbar 381.Line C-C across the opening h of the center that is formed on the second busbar 381 becomes line of cut.That is, line of cut can be opening (for example, the hole) h in the second metal electrode 380, but the invention is not restricted to this.Yet, in another embodiment of the present invention, line of cut needs not to be opening or hole, and can only be that the second metal electrode 380 should be cut part (namely, at base stage part 350 places) sign, and in the second metal electrode, in fact do not form opening or hole (for example, in the second busbar 381 of the second metal electrode 380, not forming the hole).

With reference to Fig. 8 A and Fig. 8 B, can by along line of cut cutting semiconductor substrate 310(for example, cut into two independent semiconductor base parts) form two photovoltaic devices.Can be by come cutting semiconductor substrate 310 with laser scribing.Alternatively, can be by come cutting semiconductor substrate 310 with scroll saw.In one embodiment of the invention, because carry out cutting with respect to the base stage of photovoltaic devices part (or partly locate in the base stage of photovoltaic devices) and away from the emitter zone, so can reduce that possible power loss maybe can minimize it when making photovoltaic devices.The below will provide its detailed description.

Fig. 9 A and Fig. 9 B show the result who uses laser beam induced current (LBIC) method to measure the quantum efficiency (QE) of contrast back-contact photovoltaic devices.

With reference to Fig. 9 A and Fig. 9 B, the base area of base stage part is indicated as dark areas D1 and D2.Dark base area indication electric current in respective regions is low significantly.In other words, base area is to the almost not contribution of efficient of photovoltaic devices.

Because according to embodiments of the invention, the base area of base stage part is moved toward the center of semiconductor base (wafer), and as cutting zone, so the loss that causes owing to the failure area that forms during cutting operation can be reduced or minimize.

As mentioned above, compare with the finger electrode of photovoltaic devices among the compare device, the first metal electrode 170 according to the photovoltaic devices of the embodiment of the invention can have the relative little finger electrode 172 of length and 182 with the second metal electrode 180, therefore can reduce power consumption penalty.In addition, because can reduce the thickness of

metal electrode

170 and 180, thus can reduce to be used to form the cost of the first metal electrode 170 and the second metal electrode 180, and can reduce or prevent the bending of semiconductor base 110.

And manufacturing method according to the invention can be produced a plurality of photovoltaic devices, and can reduce number of processes or make number of processes minimized.For example, can make two photovoltaic devices by a process cycle (1 cycle) of explaining according to Fig. 3 A to Fig. 8 B.Therefore, can be with that reduce or minimized cost and time production high efficiency photovoltaic devices.

In addition, according to embodiments of the invention, form photovoltaic devices by a semiconductor wafer is cut into two halves, therefore, voltage can be approximately double, and can reduce electric current.Therefore, can further reduce the loss relevant with electric current.

Figure 10 to Figure 12 shows the embodiment of electrical connection photovoltaic devices according to other embodiments of the present invention.

With reference to Figure 10 to Figure 12, can a plurality of photovoltaic devices electrical interconnections be come manufacturing module by the combination with the series and parallel connections that utilizes ribbon.

With reference to Figure 10, can be by with series connection and will become photovoltaic devices 100 interconnection in parallel of row form individual module, second busbar 181 at the first busbar 171 and the second end place that is arranged in another photovoltaic devices 100 that described series connection utilizes ribbon 10 will be arranged in the first end place of a photovoltaic devices 100 interconnects.

With reference to Figure 11, can be by with in parallel and photovoltaic devices 100 is connected in series to form individual module, described parallel connection is by utilizing ribbon 20 will be arranged in the second busbar 181 interconnection at the second busbar 181 and the first end place that is arranged in another photovoltaic devices 100 at the first end place of a photovoltaic devices 100.

Similarly, with reference to Figure 12, can be by utilizing ribbon 30 that the second busbar 181 of a photovoltaic devices 100 connect with the first busbar 171 interconnection of another photovoltaic devices 100, with photovoltaic devices 100 and photovoltaic devices 100 in parallel interconnection of series connection that will be in groups form individual module.

Except above-described embodiment, a plurality of photovoltaic devices can also by (via) various suitable combinations and arrange in combination in any and layout be one another in series and/or be connected in parallel.

According to top description, embodiments of the invention provide a kind of method of making photovoltaic devices.Here, the method comprises provides semiconductor base (for example, semiconductor wafer).Then, form base stage part and emitter portion on the surface of semiconductor base.Form insulating barrier in base stage part and emitter portion.Insulating barrier has a plurality of through holes, partly to expose base stage part and emitter portion.The first electrode is formed zone by at least one through hole contact emitter portion, the second electrode is formed by zone of another through hole contact base stage part at least.Then, partly locate to arrange line of cut at the bus electrode of the second electrode, and partly locate semiconductor base is divided into two photovoltaic devices in base stage along line of cut.Like this, according to embodiments of the invention, form two photovoltaic devices by a semiconductor wafer is cut into two halves, therefore, voltage can be approximately double, and owing to two photovoltaic devices that form from a wafer, so can reduce electric current.Therefore, can reduce current loss.

In addition, because the matrix region of base stage part used according to the invention is as cutting zone, and because the matrix region is to the almost not contribution of efficient of photovoltaic devices, so because the loss that the matrix region that be cut or that damage that forms during above-mentioned cutting operation causes can not affect formed photovoltaic devices significantly.

Although illustrated and described the present invention with reference to the preferred embodiments of the present invention, but those skilled in the art are to be understood that, in the situation that does not break away from the spirit and scope of the present invention that limit such as claims, can make the various changes of form and details aspect here.The embodiment that describes should only consider with the descriptive meaning, rather than for the purpose of restriction.Therefore, scope of the present invention is not limited by detailed description of the present invention, but limited by claim and equivalent thereof.

Label is described

110,310: semiconductor base 120,320: passivation layer

130,330: antireflection layer 140,340: emitter layer (part)

150,350: base layer (part) 160,360: insulating barrier

161,361: the first insulating barriers 162,362: the second insulating barriers

170,370: the first metal electrodes 171,371: the first busbars

172,372: the first finger electrodes 180,380: the second metal electrodes

181,381: the second busbars 182,382: the second finger electrodes

Claims

1. method of making photovoltaic devices, described method comprises the steps:

Formation has the semiconductor base of first surface and second surface, and described second surface relatively deviates from described first surface;

Form base stage part and emitter part at described first surface place;

Form insulating barrier in described base stage part and described emitter portion;

In described insulating barrier, form a plurality of through holes, partly to expose described base stage part and described emitter portion;

Form the first electrode, to contact the zone of described emitter portion by at least one through hole;

Form the second electrode, to contact the zone of described base stage part by another through hole at least;

Partly locate to arrange line of cut in described base stage; And

Cut described semiconductor base along described line of cut.

2. method according to claim 1, wherein:

The step that line of cut is set comprises: partly locate and away from described emitter portion described line of cut is set in described base stage; And

The step of cutting semiconductor substrate comprises: the location away from described emitter portion at described semiconductor base is cut described semiconductor base.

3. method according to claim 1, wherein:

The step that forms the first electrode comprises: the first electrode that forms a plurality of the first finger electrodes comprise the first busbar and to extend from described the first busbar; And

The step that forms the second electrode comprises: form the second electrode that comprises the second busbar and a plurality of the second finger electrodes, described the second busbar is arranged to across the center of described first surface and extends, and described a plurality of the second finger electrodes are from described the second busbar extension and alternate each other with described the first finger electrode.

4. method according to claim 3, wherein, the step of partly locating to arrange line of cut in base stage comprises: form the opening that extends across the center of described the second busbar, to become described line of cut.

5. method according to claim 1, wherein, the step that forms semiconductor base comprises: assign to form described semiconductor base from single semiconductor wafer by at least two bights of repairing described semiconductor wafer.

6. method according to claim 5 wherein, forms a plurality of photovoltaic devices from described single semiconductor wafer.

7. method according to claim 6, wherein:

The step that forms the first electrode comprises: the first electrode that is formed on a plurality of the first finger electrodes that comprise the first busbar in each photovoltaic devices and extend from described the first busbar in each photovoltaic devices; And

The step that forms the second electrode comprises: the second electrode that forms a plurality of the second finger electrodes comprise the second busbar and to extend from described the second busbar in each photovoltaic devices.

8. method according to claim 1, described method also comprises the steps:

In the described second surface place of described semiconductor base formation passivation layer and antireflection layer at least one.

9. method according to claim 1, described method also comprises the steps:

Described second surface veining with described semiconductor base.

10. method according to claim 1, wherein, each in described base stage part and the described emitter portion is formed has strip.

11. method according to claim 1, wherein, each in described base stage part and the described emitter portion is formed a plurality of zone of dispersions.

12. method according to claim 11, wherein, each zone of dispersion has a shape, ellipse, circle or polygonal shape.

13. method according to claim 1, wherein, described second surface is formed the front surface that is configured in the face of light source, and described first surface is formed the rear surface that is configured to deviate from described light source.

14. a photovoltaic devices, described photovoltaic devices comprises:

Semiconductor base has first surface and second surface, and described second surface relatively deviates from described first surface;

Base stage part and emitter portion are positioned at described first surface place;

Insulating barrier is positioned on described base stage part and the described emitter portion, and described insulating barrier has a plurality of through holes;

The first electrode contacts the zone of described emitter portion by at least one through hole; And

The second electrode contacts the zone of described base stage part by another through hole at least,

Wherein, described the second electrode is cutting electrode; And

Wherein, described semiconductor base only has two angle parts that are trimmed at described emitter portion place.

15. photovoltaic devices according to claim 14, wherein, described semiconductor base is formed by semiconductor wafer, and is half of size of described semiconductor wafer.

16. photovoltaic devices according to claim 15, wherein, the part of described the second electrode is extended across the center of described semiconductor wafer.

17. photovoltaic devices according to claim 14, wherein:

Described the first electrode comprises the first busbar that extends along the first edge of described semiconductor base and a plurality of the first finger electrodes that extend from described the first busbar between the angle part of described two finishings; And

Described the second electrode comprise the second busbar of extending along the second edge relative with described the first edge and from described the second busbar extend and with described the first finger electrode alternate a plurality of the second finger electrodes each other.

18. photovoltaic devices according to claim 14, described photovoltaic devices also comprises:

In passivation layer and the antireflection layer at least one is positioned at the described second surface place of described semiconductor base.

19. photovoltaic devices according to claim 14, wherein, each in described base stage part and the described emitter portion is formed has strip.

20. photovoltaic devices according to claim 14, wherein, each in described base stage part and the described emitter portion is formed a plurality of zone of dispersions.

21. photovoltaic devices according to claim 14, wherein, described insulating barrier comprises the second layer that ground floor and material are different from the material of described ground floor.