CN103035575B - The forming method of the memory element of flash memory - Google Patents
The forming method of the memory element of flash memory Download PDFInfo
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- CN103035575B CN103035575B CN201210559697.7A CN201210559697A CN103035575B CN 103035575 B CN103035575 B CN 103035575B CN 201210559697 A CN201210559697 A CN 201210559697A CN 103035575 B CN103035575 B CN 103035575B
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Abstract
A kind of forming method of the memory element of flash memory, including: the second dielectric layer being positioned at the first medium layer of semiconductor substrate surface, the floating gate layer on first medium layer surface and floating gate layer surface is provided; Forming the first opening and the second opening that are mutually communicated in second dielectric layer, the sidewall of the first opening is perpendicular to semiconductor substrate surface, and the sidewall of the second opening has the second angle relative to semiconductor substrate surface; The 3rd opening is formed in the floating gate layer of the second open bottom; Sidewall the first side wall covering the first opening, the second opening and the 3rd opening is formed in the 3rd open bottom; After semiconductor substrate surface between the first side wall forms source line layer and the second side wall, remove second dielectric layer; The floating gate layer of dry etching the first side wall and Xian Ceng both sides, source is till exposing first medium layer again; Afterwards, word line layer is formed on the first medium layer surface of the first side wall, floating gate layer and Xian Ceng both sides, source. The memory element performance of the flash memory formed improves.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of the memory element of a kind of flash memory.
Background technology
In existing integrated circuit, memory device has become a kind of important devices. In current memory device, the development of flash memory (FlashMemory) is particularly rapid. The information being mainly characterized by when not powered keeping for a long time storage of flash memory; And there is integrated level height, access speed is fast, be prone to the advantages such as erasing and rewriting, thus be widely used in the multinomial field such as microcomputer, Automated condtrol.
The memory element of existing flash memory is as it is shown in figure 1, include: Semiconductor substrate 10; It is positioned at first insulating barrier 11 on described Semiconductor substrate 10 surface; Cover the floating gate layer 12 on part the first insulating barrier 11 surface, there is in described first insulating barrier 11 and floating gate layer 12 opening (mark) exposing Semiconductor substrate 10; It is positioned at described floating gate layer 12 top surface and covers the side wall 13 of described opening sidewalls; Being positioned at Semiconductor substrate 10 surface of described open bottom and cover the source line layer 14 of described side wall 13 part surface, the surface of described source line layer 14 is not higher than the top of described side wall 13; It is positioned at the first insulating barrier 11 surface, and cover described side wall 13 and do not covered the word line layer 15 of side sidewall by source line layer 14, the top of described word line layer 15 is not higher than the top of described side wall 13, and it is mutually isolated to pass through the second insulating barrier 16 between described word line layer 15 and floating gate layer 12; It is positioned at the source region (mark) of Semiconductor substrate 10 below described source line layer 14. Wherein, the top surface of the sidewall of described floating gate layer 12 side adjacent with word line layer 15 and described floating gate layer 12 constitutes top 19, and described top 19 can be used in controlling erasing (Erase).
But, the memory element poor-performing of the flash memory that prior art is formed, program rate or memory capacity are relatively low.
The structure of more flush memory devices or the related data of forming method refer to the U.S. patent documents that publication number is US2008/0108193.
Summary of the invention
The problem that this invention address that is to provide the forming method of the memory element of a kind of flash memory, improves the performance of the memory element of the flash memory formed.
For solving the problems referred to above, the present invention provides the forming method of the memory element of a kind of flash memory, including: providing Semiconductor substrate, described semiconductor substrate surface has first medium layer, is positioned at the floating gate layer on first medium layer surface and is positioned at the second dielectric layer on floating gate layer surface; The first opening and second opening through with the bottom of described first opening is formed in described second dielectric layer, the sidewall of described first opening is perpendicular to semiconductor substrate surface, described second opening exposes floating gate layer surface, the top dimension of described second opening is identical with the bottom size of described first opening, the sidewall of described second opening has the second angle relative to semiconductor substrate surface, and the top dimension of described second opening is more than the bottom size of described second opening; With described second dielectric layer for mask, adopt the floating gate layer of the segment thickness of isotropic etching technics described second open bottom of etching, in described floating gate layer, form the 3rd opening; The first side wall of the sidewall covering described first opening, the second opening and the 3rd opening is formed on the part floating gate layer surface of described 3rd open bottom; With described first side wall and second dielectric layer for mask, the dry etch process adopting anisotropic etches described floating gate layer and first medium layer till exposing Semiconductor substrate, form the 4th opening, and form the second side wall in the sidewall surfaces of described 4th opening; Part semiconductor substrate surface in described 4th open bottom forms the source line layer covering described second side wall and part the first side wall surface, and the surface of described source line layer is not higher than described first side coping, and Xian Ceng surface, described source has mask layer; After forming described source line layer and mask layer, remove described second dielectric layer, and with described first side wall and mask layer for mask, adopt anisotropic dry etch process to etch described floating gate layer, till exposing first medium layer; After etching described floating gate layer, forming word line layer on described first medium layer surface, described word line layer covers described first side wall and is not covered the partial sidewall surface of side by source line layer, and described word line layer is lower than described first side coping.
Optionally, the degree of depth of described first opening is more than 0 angstrom, less than or equal to 500 angstroms.
Optionally, also include: the sidewall of described first opening has the first angle relative to semiconductor substrate surface, and the top dimension of described first opening is more than or equal to bottom size.
Optionally, described first angle is 88 degree ~ 90 degree.
Optionally, the degree of depth of described second opening is 3000 angstroms ~ 4500 angstroms.
Optionally, described second angle is 83 degree ~ 87 degree.
Optionally, the formation process of described first opening and the second opening includes: adopts first time anisotropic dry etch process to etch described second dielectric layer surface, forms the first opening in described second dielectric layer; Adopt the second dielectric layer of bottom of second time anisotropic dry etch process described first opening of etching till exposing described floating gate layer surface, form the second opening.
Optionally, the formation process of described word line layer includes: the sidewall surfaces at described first medium layer and mask layer surface and the first side wall layer deposits wordline thin film;Anisotropic dry etch process is adopted to etch described wordline thin film till exposing first medium layer surface.
Optionally, the formation process of described source line layer includes: at the sidewall surfaces sedimentary origin line thin film of the surface of described second dielectric layer and described first side wall and the second side wall; Remove the source line thin film being positioned at described second dielectric layer surface.
Optionally, the material of described floating gate layer, source line layer and word line layer is polysilicon.
Optionally, the material of described first medium layer is silicon oxide, and the material of second dielectric layer is silicon nitride.
Optionally, the material of described first side wall and the second side wall is silicon oxide.
Optionally, the material of described mask layer is photoresist.
Optionally, also include: with described first side wall and mask layer for mask, after adopting anisotropic dry etch process to etch described floating gate layer, before forming word line layer, the sidewall surfaces at the floating gate layer being exposed through over etching forms insulating barrier.
Optionally, the material of described insulating barrier is silicon oxide, and formation process is thermal oxidation technology.
Compared with prior art, technical scheme has the advantage that
The first opening is formed in the second dielectric layer on floating gate layer surface, and through with the bottom of described first opening and expose second opening on floating gate layer surface; The sidewall of described first opening is perpendicular to semiconductor substrate surface, and the sidewall of described second opening has the second angle relative to semiconductor substrate surface, and the top dimension of described second opening is more than bottom size; After forming the first side wall in the sidewall surfaces of described first opening and the second opening; Owing to described first side wall is for the mask as follow-up anisotropic dry etch floating gate layer, therefore, the shape that described first side wall projects to floating gate layer surface determines the shape of the floating gate layer of subsequent etching gained.
First, the first side wall upright projection figure to floating gate layer surface of the second opening it is positioned at, it is possible to definition meets the writing area size of design and the end shape of floating gate layer; Simultaneously as the sidewall of described first opening is vertical relative to Semiconductor substrate, therefore, the first side wall being positioned at the first opening will not additionally increase the upright projection size to the figure on floating gate layer surface; Thus, make follow-up with the first side wall for mask, the floating gate layer size of etching gained and the end shape of floating gate layer meet design requirement, and then guarantee that the performance of device meets product demand.
Simultaneously, when the first side wall being positioned at the second opening can define the end shape of writing area size and the floating gate layer meeting design, the first side wall being positioned at the first opening can also additionally improve the total height of described first side wall, and then raise and be formed at first medium layer surface, and cover the height that described first side wall is not covered the word line layer of side sidewall by source line layer; When the height of described word line layer improves, it is possible to increase the program rate of the memory element of flash memory, the performance of device is made to improve further.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the memory element of existing flash memory;
Fig. 2 to Fig. 5 is the cross-sectional view that prior art forms the process of the floating gate layer in the memory element of flash memory, side wall and word line layer;
Fig. 6 to Figure 14 is the cross-sectional view in the forming process of the memory element of the flash memory described in embodiments of the invention.
Detailed description of the invention
As stated in the Background Art, the memory element poor-performing of the flash memory that prior art is formed, program rate or memory capacity are relatively low.
Fig. 2 to Fig. 5 is the cross-sectional view of the process embodiments of the floating gate layer of the memory element forming flash memory as described in Figure 1, side wall and source line layer.
Refer to Fig. 2, form tunnel oxide 101 on Semiconductor substrate 100 surface, be positioned at the floating boom thin film 102 on tunnel oxide 101 surface and be positioned at the dielectric layer 103 on floating boom thin film 102 surface, the material of described floating boom thin film 102 is polysilicon, there is in described dielectric layer 103 the first opening 104 exposing floating boom thin film 102, the sidewall of described first opening 104 tilts relative to Semiconductor substrate 100 surface, and described first opening 104 top dimension is more than bottom size.
Refer to Fig. 3, with the described dielectric layer 103 with the first opening 104 for mask, adopt isotropic etching technics to etch the floating boom thin film 102 bottom described first opening 104, form the second opening 105. Owing to the sidewall of described first opening 104 has inclination angle relative to Semiconductor substrate 100 surface, the sidewall of the second opening 105 therefore formed also has corresponding inclination angle relative to described Semiconductor substrate 100 surface; Being additionally, since the technique forming described second opening 205 is isotropic etching technics, and the drift angle bottom described second opening 105 is fillet; Therefore, the sloped sidewall of described second opening 105 and the bottom with fillet drift angle are conducive to being subsequently formed the floating gate layer with top.
Refer to Fig. 4, at described second opening 105(as shown in Figure 3) floating boom thin film 102 surface of bottom forms and covers described first opening 104(as shown in Figure 3) and the first side wall 106 of the second opening 105 sidewall; With described first side wall 106 and dielectric layer 103 for mask, anisotropic dry etch process is adopted to etch described floating boom thin film 102 and tunnel oxide 101 till exposing Semiconductor substrate 100, form the 3rd opening 107, and form the second side wall 108 in the sidewall surfaces of described 3rd opening 107.
Refer to Fig. 5, at described 3rd opening 107(as shown in Figure 4) Semiconductor substrate 100 surface of bottom forms the source line layer 109 covering described second side wall 108 sidewall and part the first side wall 106 sidewall surfaces; After forming described source line layer 109, wet-etching technology is adopted to remove described dielectric layer 103(as shown in Figure 4), and photoresist layer is covered on Xian Ceng surface, described source, with described first side wall 106 and photoresist layer for mask, anisotropic dry etch process is adopted to etch described floating boom thin film 102(as shown in Figure 4) till exposing tunnel oxide 101, form floating gate layer 102a and floating gate layer 102b, and described floating gate layer 102a has top A, described floating gate layer 102b has top B. The sidewall 1022 that described top A is exposed through over etching by top surface 1021 and the described floating gate layer 102a of described floating gate layer 102a is constituted, and the sidewall that described top B is exposed through over etching by top surface and the described floating gate layer 102b of described floating gate layer 102b is constituted.
After forming described floating gate layer 102a and floating gate layer 102b, thermal oxidation technology is adopted to form insulating barrier in described floating gate layer 102a and the floating gate layer 102a sidewall surfaces being exposed through over etching; Owing to described thermal oxidation technology can consume the silicon of the described floating gate layer 102a of part and floating gate layer 102b sidewall, therefore, it is possible to make described top A and top B constitute wedge angle; The top A and top B of described tip-angled shape can be used in controlling the erasing operation of device.
The formation process of follow-up word line layer includes: after forming described insulating barrier, wordline thin film is deposited on described tunnel oxide 101, insulating barrier, source line layer 109 and the first side wall 106 surface, anisotropic dry etch process is adopted to etch described wordline thin film till exposing tunnel oxide 101 again, form word line layer on described tunnel oxide 101 surface, described word line layer covers the sidewall surfaces that the first side wall 106 is not covered by source line layer. Therefore, the height of described word line layer is determined by the height of described first side wall 106, and when the first side wall 106 is more high, the word line layer height formed is more high.
The present inventor finds through research, the performance of the memory element of flash memory is subject to the control of word line layer height, and when the height of word line layer is more big, the resistivity of described word line layer is more little, the migration rate of carrier is more fast, it is possible to make the program rate raising of the memory element of flash memory, performance more good; By said method it can be seen that the height of described word line layer is determined by the height of described first side wall 106, when the height of the first side wall 106 is more high, the height of the word line layer formed is more high; But, owing to described first side wall 106 defines shape and the position of floating gate layer 102a and the floating gate layer 102b formed, once the height of described first side wall 106 becomes big, shape and the position change of described floating gate layer 102a and floating gate layer 102b can be caused, and the shape of institute top A and top B also can change accordingly; Described top A and the excessive or too small meeting of top B cause that erasing was lost efficacy, and the change of the width of described floating gate layer 12 can change the writing area size of flush memory device, ultimately results in the device performance formed bad.
Concrete, the width of described floating gate layer 102a and floating gate layer 102b is by described first side wall 106 upright projection to floating gate layer 102(as shown in Figure 4) the dimension of picture decision on surface; Due to the sidewall slope that described first side wall 106 contacts with the first opening 104, if improving the height of word line layer and improving the height of described first side wall 106, described first side wall 106 can be increased and project to floating gate layer 102 surfacial pattern size, so that the width of the floating gate layer 102a formed and floating gate layer 102b increases, then cause that writing area size and designing requirement are not inconsistent, make device performance bad.
In addition, described top A is by the top surface 1021 of described floating gate layer 102a, and sidewall 1022 is constituted, therefore, the sidewall 106a that the shape of described top A is not contacted with source line layer by described first side wall 106, upright projection determines to the dimension of picture on floating gate layer 102 surface; Owing to described sidewall 106a tilts, when the height of described first side wall 106 improves, can cause that the described sidewall 106a dimension of picture projecting to Semiconductor substrate 100 becomes big, thus changing the shape of the top A formed; Accordingly, the height of described first side wall 106 improves, and also can change the shape of top B; And the alteration of form of described top A or top B, erasing can be caused to lose efficacy, make the performance of flush memory device formed bad. Therefore, the word line layer height that prior art is formed cannot improve further, thus performance cannot improve.
The present inventor is after further research, in the second dielectric layer on floating gate layer surface, form sidewall be perpendicular to semiconductor substrate surface the first opening, etch the second dielectric layer of described first open bottom again, form the second opening that is through with described first opening and that expose floating gate layer surface, the sidewall of described second opening tilts relative to semiconductor substrate surface, and described second open top is sized larger than bottom size; After the sidewall surfaces at described first opening and the second opening forms the first side wall, described first side wall is as the mask of follow-up anisotropic dry etch floating gate layer, and therefore the described first side wall upright projection shape in floating gate layer surface determines the shape of the floating gate layer after etching.
Wherein, being positioned at the first side wall of described second opening, its upright projection dimension of picture in floating gate layer surface can define the width of floating gate layer, and the width of described floating gate layer determines the size of writing area of flash memory cell;Therefore, the thickness of the shape and the first side wall by controlling described second opening sidewalls can make the size of writing area meet design; Secondly, the sidewall that described first side wall and the second opening contact, its upright projection dimension of picture on floating gate layer is for defining the shape on the top of floating gate layer, and the top of described floating gate layer is for controlling the erasing operation of flash memory cell; Therefore, by controlling the sidewall shape of described second opening, additionally it is possible to accurately control the shape on described top.
When the first side wall being positioned at the second opening can the floating gate layer shape of explication design and during position, the surface contacted due to described first side wall and the sidewall of the first opening is vertical relative to Semiconductor substrate, therefore, the first side wall being positioned at the first opening will not additionally increase by the first side wall upright projection dimension of picture to floating gate layer surface of entirety; So that follow-up with the first side wall be mask etching gained floating gate layer size and the end shape of floating gate layer meet design requirement, and then guarantee that the performance of device meets product demand; Simultaneously, first side wall described in being positioned at the first opening can also raise the whole height of described first side wall, and then the height making to be subsequently formed the word line layer not covered side by source line layer in the first side wall improves, thus improving the program rate of flash memory, therefore the performance of device improves further.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
As shown in Fig. 6 to Figure 14, be flash memory described in embodiments of the invention memory element forming process in cross-sectional view.
Refer to Fig. 6, it is provided that Semiconductor substrate 200, described Semiconductor substrate 200 surface has first medium layer 201, is positioned at the floating gate layer 202 on first medium layer 201 surface and is positioned at the second dielectric layer 203 on floating gate layer 202 surface; First time etches described second dielectric layer 203 surface, forms the first opening 204 in described second dielectric layer 203, and the sidewall of described first opening 204 is perpendicular to Semiconductor substrate 200 surface.
Described Semiconductor substrate 200 is for providing work platforms for subsequent technique; Described Semiconductor substrate 300 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V substrate (such as silicon nitride or GaAs etc.).
The material of described first medium layer 201 is silicon oxide, and formation process is depositing operation, it is preferred that chemical vapor deposition method; When the material of described Semiconductor substrate 200 is silicon, the formation process of described first medium layer 201 can also be thermal oxidation technology; Described first medium layer 201 is for isolation of semiconductor substrate 200 and floating gate layer 202, as tunnel oxide, after the memory element being subsequently formed flash memory, carrier can pass described first medium layer 201, realize the migration between Semiconductor substrate 200 and floating gate layer 202, thus reaching storage or the purpose of erasing.
The material of described floating gate layer 202 is polysilicon, and the thickness of described floating gate layer 202 is determined according to concrete process requirements; The formation process of described floating gate layer 202 is depositing operation, it is preferred that chemical vapor deposition method; Described floating gate layer 202 can be captured or lose electronics such that it is able to reach storage and the function of erasing.
The material of described second dielectric layer 203 is silicon nitride, and be subsequently formed there is Etch selectivity between the first side wall and the second side wall that silicon oxide is material, thus when the described second dielectric layer 203 of follow-up removal, the first side wall formed will not be damaged;The formation process of described second dielectric layer 203 is depositing operation, it is preferred that chemical vapor deposition method, and thickness is 3000 angstroms ~ 4500 angstroms; The thickness of described second dielectric layer 203 determines the height of follow-up the first formed side wall, then determines the height of word line layer; And described word line layer is more high, the performance of the memory element of the flash memory formed is more excellent.
The formation process of described first opening 204 is anisotropic dry etch process, and the degree of depth of described first opening 204 is more than 0 angstrom, less than or equal to 500 angstroms; In the present embodiment, the sidewall of described first opening 204 is perpendicular to Semiconductor substrate 200 surface; When follow-up after described first opening 204 and the sidewall surfaces of the second opening that is subsequently formed form the first side wall, owing to the sidewall of described first opening 204 is perpendicular to Semiconductor substrate 200, dimension of picture thus without extra floating gate layer 202 surface increasing described first side wall upright projection, it is ensured that meet design standard with the floating gate layer shape that described first side wall obtains for mask etching; Meanwhile, the first side wall being subsequently formed in described first opening 204 can improve the whole height of described first side wall, so that the height of follow-up formed word line layer improves, and then improves the performance of the memory element of flash memory.
In other embodiments, the sidewall of described first opening 204 has the first angle relative to Semiconductor substrate 200 surface, and the top dimension of described first opening 204 is more than or equal to bottom size; Described first angle is 88 degree ~ 90 degree, described first angle is more than follow-up the second the formed opening the second angle relative to Semiconductor substrate 200 surface, still ensure that while not changing the floating gate layer shape that etching obtains, improve the height of the first side wall being subsequently formed.
Refer to Fig. 7, second time etches the second dielectric layer 203 of the bottom of described first opening 204, till exposing described floating gate layer 202 surface, form the second opening 205, the sidewall of described second opening 205 has the second angle relative to Semiconductor substrate 200 surface, the bottom size of described first opening 204 is identical with the top dimension of described second opening 205, and the top dimension of described second opening 205 is more than the bottom size of described second opening 205.
Described second time etching is anisotropic dry etch process, and the sidewall of the second opening 205 formed is 83 degree ~ 87 degree relative to the second angle that Semiconductor substrate 200 tilts, and the degree of depth of described second opening 205 is 3000 angstroms ~ 4500 angstroms; The sloped sidewall of the second opening 205 formed can pass through to regulate the parameter of described anisotropic dry etch process and realize, including gas componant and content, power and direction of supplying gas; Concrete; described etching gas has the gas for forming polymeric layer; the polymeric layer formed is for forming the etching surface that protection is perpendicular on Semiconductor substrate 200 direction; and it is more few for forming the gas of passivation polymer layer; the sidewall of the second opening 205 formed more tilts; therefore by adjusting in etching gas for forming the gas content of polymeric layer, it is possible to adjust the sidewall slope angle of described second opening 205.
When the sidewall slope of described second opening 205, follow-up with described second dielectric layer 203 for mask, adopt the sidewall that isotropic etching technics etches the 3rd opening that described floating gate layer 202 surface is formed to tilt also relative to Semiconductor substrate 200 surface;Thus when follow-up the first side wall to be formed is for floating gate layer 202 described in mask etching, floating gate layer 202 sidewall being etched can constitute top with the sidewall of described 3rd opening, described top can be used in controlling erasing.
Due to the sidewall slope of described second opening 205, the surface that the first side wall being therefore subsequently formed contacts with described second opening 205 sidewall tilts also relative to Semiconductor substrate 200 surface; When follow-up with the first side wall for floating gate layer 202 described in mask etching time, the surface projection that described first side wall and the second opening 205 sidewall contact can define etching to the figure on floating gate layer surface after the size on top of floating gate layer 202; And the top of described floating gate layer 202 is excessive or too small all can cause erasing disabler, it is therefore desirable to control the height of described second opening 205, to ensure that the top formed disclosure satisfy that process requirements. Thus, the height of described second opening 205 is limited, it is necessary to be positioned at described first opening to raise the total height of the first side wall being subsequently formed, thus improving the height of word line layer.
Refer to Fig. 8, with described second dielectric layer 203 for mask, adopt isotropic etching technics to etch the floating gate layer 202 of the segment thickness bottom described second opening 205, in described floating gate layer 202, form the 3rd opening 206.
The technique forming described 3rd opening 206 is isotropic etching technics, it is preferred that isotropic dry etch process; In another embodiment, first the floating gate layer 202 bottom described second opening 205 can also be carried out anisotropic dry etching, form the 3rd opening that the angle of inclination of sidewall is consistent with the sidewall of the second opening 205, more described 3rd opening is carried out the etching technics of described isotropic.
Owing to described second dielectric layer 203 has the first opening 204 and the second opening 205, and the sidewall of described second opening 205 tilts relative to Semiconductor substrate 200 surface, therefore when with described second dielectric layer 203 for mask, when adopting isotropic etching technics to etch the floating gate layer 202 bottom described second opening 205, etching technics etches described floating gate layer 202 along the sidewall of described second opening 205, it is possible to make the sidewall of the 3rd opening 206 formed tilt also relative to described Semiconductor substrate 200 surface; And, owing to described etching technics is anisotropic etching technics, therefore, it is possible to the bottom drift angle making the 3rd opening 206 formed is fillet, so that the sidewall of described 3rd opening 206 is bigger than the second angle relative to the angle of inclination on Semiconductor substrate 200 surface; When subsequent technique forms the first side wall, and it is follow-up with described first side wall for floating gate layer described in mask etching 202, can making between sidewall and the sidewall being etched of described 3rd opening 206 composition top, described top is for controlling the erasing function of the memory element of flash memory formed.
Therefore, second opening 205 described in sloped sidewall can be used in being formed the 3rd opening 206 of sidewall slope; Meanwhile, the sloped sidewall of described second opening 205 projects to the figure on floating gate layer 202 surface and also defines simultaneously and be subsequently formed in the end shape of floating gate layer 202; So, the described height of the second opening 205 and the angle of inclination of sidewall determine width and the end shape of the follow-up floating gate layer through over etching.
Refer to Fig. 9, part floating gate layer 202 surface bottom described 3rd opening 206 forms the first side wall 207 of the sidewall covering described first opening the 204, second opening 205 and the 3rd opening 206.
The material of described first side wall 207 is silicon oxide, and formation process includes: on described second dielectric layer 203 surface, the sidewall of first opening the 204, second opening 205 and the 3rd opening 206, and the first side wall thin film is formed on the bottom of the 3rd opening 206; Being etched back to described first side wall thin film until exposing floating gate layer 202 surface bottom the surface of second dielectric layer 203 and part the 3rd opening 206, forming the first side wall 207. The thickness of described first side wall thin film determines the width of the first side wall 207 formed, and the width between the first adjacent side wall 207 determines the size of the source line layer being subsequently formed; Again owing to the size bottom described second opening 205 determines the position of the floating gate layer after subsequent etching, therefore, the thickness of described first side wall thin film and shape and the size of the second opening 205 are determined all in accordance with concrete process requirements, it is impossible to arbitrarily change.
Described first side wall 207 is for the mask as subsequent etching floating gate layer 202, and therefore described first side wall 207 projects to the figure on described floating gate layer 202 surface and determines the shape of the floating gate layer 202 after subsequent etching. Wherein, being positioned at the first side wall 207 of the second opening 205 and the 3rd opening 206 to project to the figure on floating gate layer surface and determine the width of the floating gate layer 202 after subsequent etching, the width of described floating gate layer 202 determines the writing area size of the memory element of the flash memory formed; Secondly, the sidewall that described first side wall 207 contacts with the second opening 205 projects to the size on the top being formed at floating gate layer after the figure on described floating gate layer 202 surface also determines subsequent etching, the top of described floating gate layer is used for controlling device erasing, and described top is excessive or too small all can cause that erasure lost efficacy; Again, owing to the sidewall of described first opening 204 is vertical relative to Semiconductor substrate 200 surface, will not additionally increase described first side wall 207 therefore in the first side wall 207 in the first opening 204 and project to the dimension of picture on floating gate layer 202 surface, it is ensured that the width of the floating gate layer 202 after etching meets design standard; Meanwhile, the first side wall 207 being positioned at described first opening 204 can increase the total height of described first side wall 207, thus improving the height of the word line layer being subsequently formed, with the device performance that improvement is formed.
Refer to Figure 10, with described first side wall 207 and second dielectric layer 203 for mask, the dry etch process adopting anisotropic etches described floating gate layer 202 and first medium layer 201 till exposing Semiconductor substrate 200, form the 4th opening 208, and form the second side wall 209 on floating gate layer 202 surface of the sidewall of described 4th opening 208.
The etching technics of described formation the 4th opening 208 is anisotropic dry etch process; The material of described second side wall 209 is silicon oxide, and formation process is identical with the formation process of the first side wall 207, does not repeat at this; Described 4th opening 208 exposes Semiconductor substrate 200 surface, for enabling the source line layer being subsequently formed in first opening the 204, second opening 205 and the 3rd opening 206 to connect described Semiconductor substrate 200.
Refer to Figure 11, at described 4th opening 208(as shown in Figure 10) part semiconductor substrate 200 surface of bottom forms the source line layer 210 covering described second side wall 209 and part the first side wall 207 surface, the surface of described source line layer 210 is not higher than the top of described first side wall 207, and Xian Ceng210 surface, described source has mask layer (not shown).
The material of described source line layer 210 is polysilicon; The formation process of described source line layer 210 is: at described second dielectric layer 203 surface and the first opening 204(as shown in Figure 10), the second opening 205(as shown in Figure 10), the 3rd opening 206(as shown in Figure 10) and the 4th opening 208 in deposited polycrystalline silicon thin film; Adopt CMP process or be etched back to the technique removal polysilicon membrane higher than described second dielectric layer 203 surface, forming source line layer 210; In the present embodiment, the source line layer 210 formed is lower than the top of described first side wall 207.
Described mask layer for protecting Xian Ceng surface, described source injury-free when subsequent etching floating gate layer, and the material of described mask layer is photoresist; Described mask layer can be removed after floating gate layer described in subsequent etching 202, or removes after being subsequently formed word line layer.
In other embodiments, the formation process of described source line layer 210 can also be selective epitaxial depositing operation, and the height of the source line layer 210 formed is more accurate, is conducive to improving device performance.
Refer to Figure 12, after forming described source line layer 210 and mask layer, remove described second dielectric layer 203(as shown in figure 11), and with described first side wall 207 and mask layer for mask, anisotropic dry etch process is adopted to etch described floating gate layer 202(as shown in figure 11), till exposing first medium layer 201.
The technique of described removal second dielectric layer 203 is wet-etching technology, owing to the material of described mask layer, the first side wall 207 and floating gate layer 202 is respectively provided with Etch selectivity relative to the material of second dielectric layer 203, therefore, adopt wet-etching technology quickly can remove described second dielectric layer 203 up hill and dale, without damaging described first side wall 207 and floating gate layer 202; The etching liquid of described wet etching includes phosphoric acid.
With the first side wall 207 and mask layer for mask, the technique etching described floating gate layer 202 is anisotropic dry etch process, therefore, described first side wall 207 upright projection is in described floating gate layer 202(as shown in figure 11) figure on surface determine etching after the shape of described floating gate layer 202 and position.
Wherein, the surface contacted with the second opening 205 sidewall due to described first side wall 207 tilts relative to Semiconductor substrate 200 surface, vertical relative to Semiconductor substrate 200 surface with the surface that the first opening 204 sidewall contacts, when the gas in described etching technics from described first side wall 207 plan vertical to described floating gate layer 202(as shown in figure 11) bombardment time, being formed floating gate layer 202 sidewall that is etched can with the floating gate layer 202 sidewall composition top of the 3rd opening 206; It follows that the dimension of picture on the surface upright projection that contacts with the second opening 205 sidewall of the first side wall 207 and floating gate layer 202 surface determines the size on the top formed; Owing to described top is excessive or the too small erasing that all can cause floating gate layer 202 was lost efficacy, accordingly, it would be desirable to the angle of inclination of the height and sidewall by controlling described second opening 205, to form the top meeting design requirement.
Sidewall again due to described first opening 204(as shown in Figure 8) is vertical relative to Semiconductor substrate 200 surface, the width of the floating gate layer 202 after etching will not be increased therefore in the first side wall 207 in the first opening 204, make the width of the floating gate layer after etching 202 only by being positioned at the second opening 205(as shown in Figure 9) and the 3rd opening 206(is as shown in Figure 9) first side wall 207 upright projection dimension of picture in floating gate layer 202 surface determine;And the first side wall 207 being positioned at described first opening 204 can improve the total height of the first side wall 207 formed, making the height of follow-up formed word line layer improve, thus improving the programming efficiency of the memory element of the flash memory formed, improving device performance.
To sum up, being formed at the first side wall 207 in first opening the 204, second opening 205 and the 3rd opening 206 can at the width forming the floating gate layer 202 meeting design requirement, and meet the floating gate layer 202 of design requirement end shape meanwhile, it is capable to make the height of word line layer being subsequently formed improve; Thus improving the programming efficiency of the memory element of the flash memory formed, to improve device performance.
It should be noted that with described first side wall 207 and mask layer for mask, after etching described floating gate layer 202, forming insulating barrier 213 on the surface that described floating gate layer 202 is etched; The formation process of described insulating barrier 213 is thermal oxidation technology, for isolating floating gate layer 202 and the word line layer being subsequently formed; The polysilicon of the sidewall being etched of the described floating gate layer 202 of part can be consumed such that it is able to make the end shape of the floating gate layer 202 through over etching become tip-angled shape, with the demand of satisfied erasing function due to described thermal oxidation technology; Point discharge principle is passed through on described tip-angled shape top, it is possible to makes electronics be pulled away from described floating gate layer 202 from described wedge angle, reaches wiping purposes. In the present embodiment, the mask layer on Xian Ceng210 surface, described source is removed after etching described floating gate layer 202.
Refer to Figure 13, after etching floating gate layer 202, the sidewall surfaces at described first medium layer 201 and Xian Ceng210 surface, source and the first side wall layer 107 deposits wordline thin film 211.
The material of described wordline thin film 211 is polysilicon, and formation process includes chemical vapor deposition method and physical vapor deposition technique, it is preferred that chemical vapor deposition method; Owing to the follow-up wordline thin film 211 being positioned at first medium layer 201 surface and Xian Ceng210 surface, source needs to be etched removal, therefore the thickness of described wordline thin film 211 and the height of wordline thin film 211 that contacts with the first side wall 207 sidewall surfaces determine the height being subsequently formed word line layer; In the present embodiment, owing to the height of described first side wall 207 increases, the wordline thin film 211 therefore contacted with the first side wall 207 sidewall highly improves, thus the height of the word line layer being subsequently formed increases, the device performance formed improves.
Refer to Figure 14, anisotropic dry etch process is adopted to etch described wordline thin film 211(as shown in figure 13) till exposing first medium layer 201 surface, word line layer 211a, the described word line layer 211a top lower than described first side wall 107 is formed on first medium layer 201 surface of described first side wall 107, floating gate layer 202 and Xian Ceng210 both sides, source.
Described anisotropic dry etch process is for removing the wordline thin film 211 of first medium layer 201, due in the present embodiment, be positioned at the first opening 204(as shown in Figure 9) the first side wall 207 can increase the total height of described first side wall 207, do not change the position of floating gate layer 202, width dimensions and the end shape that are formed with described first side wall 207 for mask etching simultaneously, therefore, while the performance of the floating gate layer 202 that can be formed after ensureing etching, the height of the word line layer 211a formed is made to improve; And the height of described word line layer 211a is more high, the program rate of the memory element of the flash memory formed is more fast, and device performance is more good.
In the present embodiment, the surface that the first side wall 207 contacts with the second opening 205 sidewall tilts relative to Semiconductor substrate 200 surface, vertical relative to Semiconductor substrate 200 surface with the surface that the first opening 204 sidewall contacts;The first side wall 207 being formed in the second opening 205 and the 3rd opening 206 can be used in making the width of the floating gate layer 202 formed and the end shape of floating gate layer 202 meet design requirement; Meanwhile, the first side wall 207 being positioned at the first opening 204 on the basis of the width of the floating gate layer 202 after not increasing etching, can improve the total height of the first side wall 207 formed; So that the height of the word line layer 211a formed improves, to improve the programming efficiency of the memory element of the flash memory formed, improve device performance.
In sum, in the second dielectric layer on floating gate layer surface, form the first opening, and through with the bottom of described first opening and expose second opening on floating gate layer surface; The sidewall of described first opening is perpendicular to semiconductor substrate surface, and the sidewall of described second opening has the second angle relative to semiconductor substrate surface, and the top dimension of described second opening is more than bottom size; After forming the first side wall in the sidewall surfaces of described first opening and the second opening; Owing to described first side wall is for the mask as follow-up anisotropic dry etch floating gate layer, therefore, the shape that described first side wall projects to floating gate layer surface determines the shape of the floating gate layer of subsequent etching gained.
First, the first side wall upright projection figure to floating gate layer surface of the second opening it is positioned at, it is possible to definition meets the writing area size of design and the end shape of floating gate layer; Simultaneously as the sidewall of described first opening is vertical relative to Semiconductor substrate, therefore, the first side wall being positioned at the first opening will not additionally increase the upright projection size to the figure on floating gate layer surface; Thus, make follow-up with the first side wall for mask, the floating gate layer size of etching gained and the end shape of floating gate layer meet design requirement, and then guarantee that the performance of device meets product demand.
Simultaneously, when the first side wall being positioned at the second opening can define the end shape of writing area size and the floating gate layer meeting design, the first side wall being positioned at the first opening can also additionally improve the total height of described first side wall, and then raise and be formed at first medium layer surface, and cover the height that described first side wall is not covered the word line layer of side sidewall by source line layer; When the height of described word line layer improves, it is possible to increase the program rate of the memory element of flash memory, the performance of device is made to improve further.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (15)
1. the forming method of the memory element of a flash memory, it is characterised in that including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface has first medium layer, is positioned at the floating gate layer on first medium layer surface and is positioned at the second dielectric layer on floating gate layer surface;
The first opening and second opening through with the bottom of described first opening is formed in described second dielectric layer, the sidewall of described first opening is perpendicular to semiconductor substrate surface, or the top dimension of described first opening is more than bottom size, described second opening exposes floating gate layer surface, the top dimension of described second opening is identical with the bottom size of described first opening, the sidewall of described second opening has the second angle relative to semiconductor substrate surface, and the top dimension of described second opening is more than the bottom size of described second opening;
With described second dielectric layer for mask, adopt the floating gate layer of the segment thickness of isotropic etching technics described second open bottom of etching, in described floating gate layer, form the 3rd opening;
The first side wall of the sidewall covering described first opening, the second opening and the 3rd opening is formed on the part floating gate layer surface of described 3rd open bottom;
With described first side wall and second dielectric layer for mask, the dry etch process adopting anisotropic etches described floating gate layer and first medium layer till exposing Semiconductor substrate, form the 4th opening, and form the second side wall in the sidewall surfaces of described 4th opening;
Part semiconductor substrate surface in described 4th open bottom forms the source line layer covering described second side wall and part the first side wall surface, and the surface of described source line layer is not higher than described first side coping, and Xian Ceng surface, described source has mask layer;
After forming described source line layer and mask layer, remove described second dielectric layer, and with described first side wall and mask layer for mask, adopt anisotropic dry etch process to etch described floating gate layer, till exposing first medium layer;
After etching described floating gate layer, forming word line layer on described first medium layer surface, described word line layer covers described first side wall and is not covered the partial sidewall surface of side by source line layer, and described word line layer is lower than described first side coping.
2. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the degree of depth of described first opening is more than 0 angstrom, less than or equal to 500 angstroms.
3. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that also include: the sidewall of described first opening has the first angle relative to semiconductor substrate surface, and the top dimension of described first opening is more than or equal to bottom size.
4. the forming method of the memory element of flash memory as claimed in claim 3, it is characterised in that described first angle is 88 degree��90 degree.
5. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the degree of depth of described second opening is 3000 angstroms��4500 angstroms.
6. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that described second angle is 83 degree��87 degree.
7. the forming method of the memory element of flash memory as claimed in claim 1, it is characterized in that, the formation process of described first opening and the second opening includes: adopts first time anisotropic dry etch process to etch described second dielectric layer surface, forms the first opening in described second dielectric layer; Adopt the second dielectric layer of bottom of second time anisotropic dry etch process described first opening of etching till exposing described floating gate layer surface, form the second opening.
8. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the formation process of described word line layer includes: the sidewall surfaces at described first medium layer and mask layer surface and the first side wall layer deposits wordline thin film; Anisotropic dry etch process is adopted to etch described wordline thin film till exposing first medium layer surface.
9. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the formation process of described source line layer includes: at the sidewall surfaces sedimentary origin line thin film of the surface of described second dielectric layer and described first side wall and the second side wall; Remove the source line thin film being positioned at described second dielectric layer surface.
10. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the material of described floating gate layer, source line layer and word line layer is polysilicon.
11. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the material of described first medium layer is silicon oxide, and the material of second dielectric layer is silicon nitride.
12. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the material of described first side wall and the second side wall is silicon oxide.
13. the forming method of the memory element of flash memory as claimed in claim 1, it is characterised in that the material of described mask layer is photoresist.
14. the forming method of the memory element of flash memory as claimed in claim 1, it is characterized in that, also include: with described first side wall and mask layer for mask, after adopting anisotropic dry etch process to etch described floating gate layer, before forming word line layer, the sidewall surfaces at the floating gate layer being exposed through over etching forms insulating barrier.
15. the forming method of the memory element of flash memory as claimed in claim 14, it is characterised in that the material of described insulating barrier is silicon oxide, and formation process is thermal oxidation technology.
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| CN105097488A (en) * | 2014-05-16 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon chip etching method |
| CN106783866B (en) * | 2017-01-05 | 2019-07-02 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of flush memory device |
| CN108987403B (en) * | 2018-07-20 | 2020-11-13 | 上海华虹宏力半导体制造有限公司 | Method for controlling tip of floating gate of flash memory |
| CN111834245B (en) * | 2020-08-26 | 2022-09-23 | 上海华虹宏力半导体制造有限公司 | Semiconductor PCM structure and detection method thereof |
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