CN103021469A - Universal single event effect detecting method of memory circuit - Google Patents
Universal single event effect detecting method of memory circuit Download PDFInfo
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Abstract
The invention provides a universal single event effect detecting method of a memory circuit. The universal single event effect detecting method comprises the following steps of (1) configuring a memory to be detected to be in a write state, and writing into a test vector; and then arranging the memory to be detected in a radiation environment; (2) if a dynamic test is conducted, configuring the memory to be detected to be in a read state, reading out data stored in each address unit and comparing the read-out data with the written-in data, using the quantity of address units with different comparing results as a total error count, and further analyzing a condition that each address unit generates 2-bit or more than 2-bit data flipping; and (3) if a static test is conducted, configuring the memory to be detected to be in a non-read non-write state; after irradiation particles accumulated in an irradiation process reach a standard, sequentially reading out data in each address unit and comparing with the written-in data; and using the quantity of the address units with the different comparing results as the total error count. In the irradiation process, working current of the memory to be detected can be monitored in real time. Latch is implemented when the working current exceeds 1.5 times of normal working current.
Description
Technical field
The present invention relates to a kind of verification method of anti-space single particle effect capability of semiconductor devices.
Background technology
Field programmable gate array (FPGA) can be finished the function that a plurality of discreet logic devices of original needs and storage chip are finished, reduce simultaneously power consumption and the cost of system, shorten the lead time, thus in fields such as the test of semiconductor devices, embedded system development designs in occupation of more and more important position.
When memory circuitry was applied in the space environment, Energetic particle can penetrate semiconductor device inside and produce ionization in the path, causes the circuit mistake thereby circuit node can absorb electronics and the hole of ionization generation, and this effect is called single particle effect.Particle bombardment mainly contains two kinds of single-particle inversion effect (SEU), single event latch-up effects (SEL) at the inner caused single particle effect of memory circuitry, wherein the single-particle inversion effect refers in the memory circuitry that the data of each address location storage overturn under radiation parameter, causes losing of the information of storing; The single event latch-up effect refers to the generation current pulse in the device inside circuit of single ion, so that the conducting of PN-PN structure causes device current significantly to increase.The detection of single event latch-up effect is comparatively simple, mainly is that the working current to semiconductor devices carries out Real Time Monitoring, and the detection of single-particle inversion effect is then comparatively complicated.
Existing memory circuitry single particle effect test method mainly is by write fixing test vector to memory circuitry, continuous memory read in irradiation process, then misaddress is rewritten as right value if make a mistake, and mistake sum, misaddress and data are beamed back host computer.This method mainly exists following two deficiencies: the one, can count the upset sum of whole circuit and overturn address and wrong number, but when being arranged, a large amount of upset is difficult to locate the multidigit upset and add up 0 and turn over 1,1 turns over 0 situation, and this has just caused difficulty for the data analysis of memory circuitry; The 2nd, do not have versatility, at present for the single particle effect detection method of memory circuitry or ad hoc approach for particular electrical circuit, when new memory circuitry is arranged, also need the method that restudies and test system building, and the method for testing of synchronous memories and asynchronous memory and system do not have compatibility.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of general purpose single particle effect detection method that is applicable to various memory circuitries is provided.
Technical solution of the present invention is: a kind of general purpose single particle effect detection method of memory circuitry, and step is as follows:
(1) configuration memory circuitry to be measured also needs to determine its working clock frequency for writing state for the synchronous memories circuit;
(2) select test vector and test vector write each address location of memory circuitry to be measured, then place radiation environment to begin irradiation memory circuitry to be measured; The working current of Real-Time Monitoring memory circuitry to be measured in irradiation process is judged when the working current abnormal and when surpassing 1.5 times of running current breech lock occurs until test finishes;
(3) selecting is to carry out dynamic test or static test, if dynamic test then enters step (4), if static test then enters step (6);
(4) be read states with memory circuit arrangement to be measured, compare with the data reading of each address location storage of memory circuitry to be measured and with the data that write, the quantity of the inconsistent address location of comparative result as total error count, is then entered step (5);
(5) all carry out following operation for inconsistent each address location of comparative result, remember that operated address location is address location i,
(51) with each negate of the data writing Si of address location i and and the corresponding positions of the sense data Si+1 of address location i carry out the operation of logical and, obtain corresponding one group of data sequence T (i, j), wherein i represents this address location, j is the data bits of this address location, if the value of T (i, j) is 1, judge that then 0-has occured the data of the j position among the address location i〉1 upset; If the value of T (i, j) is 0, judge that then 0-does not occur the data of the j position among the address location i〉1 upset;
(52) with the non-operation of carrying out logical and of the corresponding positions of the sense data Si+1 of each and the address location i of the data writing Si of address location i, obtain corresponding one group of data sequence K (i, j), if K is (i, j) value is 1, judges that then 1-has occured the data of the j position among the address location i〉0 upset; If the value of K (i, j) is 0, judge that then 1-does not occur the data of the j position among the address location i〉0 upset;
(53) add up respectively two groups of data sequences of T (i, j) and K (i, j), according to the value condition of j in the data sequence, obtain the situation that 2 or 2 above Data flippings occur address location i, finish test;
(6) with memory circuit arrangement to be measured for not reading not write state, also need to set its clock signal for the synchronous memories circuit and stop, after the accumulative total irradiation particle in the irradiation process reaches standard, stop irradiation; Setting its clock signal for the synchronous memories circuit replys, then call over the data in each address location of memory circuitry to be measured and compare with data writing, then directly call over the data in each address location of memory circuitry to be measured and compare with data writing for the asynchronous memory circuit, the quantity of the inconsistent address location of comparative result as total error count, is finished test.
Described test vector is: " 00 ", " FF ", " 55 ", " AA ", " 55 "+" AA ", " 00 "+" FF ", perhaps MARCH.
The present invention's advantage compared with prior art is:
(1) the inventive method can detect memory circuitry by single-particle inversion and single event latch-up situation that the single-particle bombardment causes, both has been applicable to the single particle effect test of synchronous memories, also is applicable to the single particle effect test of asynchronous memory;
(2) the inventive method can provide multiple test vector to the memory under test circuit, satisfies the different testing requirements of memory circuitry;
(3) the inventive method can be finished by the model selection instruction test of dynamic test and two kinds of patterns of static test of memory circuitry, has enriched test method, so that measuring ability is more comprehensive;
(4) the inventive method can count respectively 0 and turns over 1,1 and turn over 0 and multidigit upset situation, thereby accurately the store status of analyzing stored device circuit is to the susceptibility of single-particle inversion;
(5) the inventive method can accurately be located address bit and the data bit that upset occurs, and can analyze upper address bits and low address position, and high data bit and low bit be to the susceptibility of single-particle inversion, thereby instructs the chip design personnel to improve design;
(6) the inventive method can real-time online in process of the test the single-particle inversion situation of observation memory under test, can analyze particle fluence rate and fluence to the impact of the anti-single particle overturn performance of memory device.
Description of drawings
Fig. 1 is the process flow diagram of the inventive method.
Embodiment
As shown in Figure 1, be the process flow diagram of the general single particle effect detection method of memory circuitry of the present invention.After beginning test, at first by disposing the pin signal of storage component part to be measured, so that memory operation to be measured is being write state or read states or do not read under three kinds of different mode of operations of the state of not writing.
Writing under the state, according to test instruction, write test vector (" 00 ", " FF ", " 55 ", " AA ", " 55 "+" AA ", " 00 "+" FF ", MARCH etc.) to all addresses of storer to be measured.In process of the test, can input the required test vector of Instruction Selection so that the store status of the unit of memory circuitry and duty are under the particular state by host computer, and then comprehensively examine the anti-single particle effect performance of memory circuitry.
Under read states, detect the data output end of storer to be measured, and with the data that receive with compare writing the test vector that writes to storage component part to be measured under the state, if inconsistent then think overturn, and with the address and the address date that overturn, the upset sum is recorded.
Do not reading under the state of not writing, memory under test spare is in reset mode.
In the irradiation process, if select dynamic test, then storer to be measured is in read states, and single-particle inversion then writes correct value with misaddress after occuring again, simultaneously the single-particle inversion situation is carried out record; If selection envelope test, after then test vector being write each address location of storer to be measured, do not read not write state until irradiation finishes so that storer to be measured is in, then the single-particle inversion situation is once read and added up to the data of each address location of storer to be measured.When carrying out single-particle inversion test, but the working current of Real-Time Monitoring device, in case device operation current abnormal (surpass running current 1.5 times) then think the generation breech lock.
Concrete workflow is as follows:
(1) mode of operation is selected: if measured device be the synchronous memories circuit need to determine device working clock frequency, read or write that control, dynamic test and static test are selected, test vector is selected (to write " 00 ", " FF ", " 55 ", " AA ", " 55 "+" AA ", " 00 "+" FF ", MARCH etc.); When if measured device is the asynchronous memory circuit then need to determine to read or write that control, dynamic test and static test are selected, test vector is selected;
(2) the config memory circuit with each address location of test vector write store circuit, is finished initial configuration for writing state, open line and begin irradiation, if dynamic test, jump procedure (3), if static test, jump procedure (4);
(3) duty with memory circuitry is made as read states, compare with the data reading of each address location storage of memory circuitry and with data writing, if comparison error then adds error count 1 and be correct data with the data rewriting of misaddress, misaddress and data and error count are recorded carried out data analysis and process simultaneously.
The method of single-particle inversion data statistic analysis is as follows:
In data handling procedure, the corresponding positions phase of data Si+1 after each negate of data Si before the same address location i upset and the Si upset and, obtain corresponding one group of new data sequence T (i, j), if j is the data bits of memory cell, if the value of T (i, j) is 1 so, then 0-has occured in the data of the j position among the address location i〉1 upset; If the value of T (i, j) is 0, then 0-does not occur in the data of the j position among the i of address〉1 upset.
In like manner, the corresponding positions of data Si+1 after each of data Si before the same address location i upset is overturn with Si non-with, obtain corresponding one group of new data sequence K (i, j), if j is the data bits of memory cell, if the value of K (i, j) is 1 so, then 1-has occured in the data of the j position among the address location i〉0 upset; If the value of K (i, j) is 0, then 1-does not occur in the data of the j position among the address location i〉0 upset.
T (i according to statistics, j) and K (i, j) two groups of data are overturn to multidigit and are analyzed, if for same address location i long numeric data overturn (j has a plurality of values) is arranged, perhaps there are the data of a plurality of storage unit to reverse on the same address wire, then be defined as this address the multidigit upset occurs, and 2 bit flippings occur in statistics respectively, 3 bit flippings, 4 bit flippings or above number of times, this can be more comprehensively the analysis list particle effect impact of memory circuitry function is conducive to promote the radiation resistance of memory circuitry.
(4) duty of memory circuitry is configured to not read do not write state (if synchronous memories circuit then clock signal stop), after reaching standard, accumulative total irradiation particle stops irradiation, (if the synchronous memories circuit then recovers synchronizing clock signals), call over the interior data of storage unit and compare mistake of statistics number and record with data writing.
The content that is not described in detail in the instructions of the present invention belongs to those skilled in the art's known technology.
Claims (2)
1. the general purpose single particle effect detection method of a memory circuitry is characterized in that step is as follows:
(1) configuration reservoir circuit to be measured also needs to determine its working clock frequency for writing state for the synchronous memories circuit;
(2) select test vector and test vector write each address location of memory circuitry to be measured, then place radiation environment to begin irradiation memory circuitry to be measured; The working current of Real-Time Monitoring memory circuitry to be measured in irradiation process is judged when the working current abnormal and when surpassing 1.5 times of running current breech lock occurs until test finishes;
(3) selecting is to carry out dynamic test or static test, if dynamic test then enters step (4), if static test then enters step (6);
(4) be read states with memory circuit arrangement to be measured, compare with the data reading of each address location storage of memory circuitry to be measured and with the data that write, the quantity of the inconsistent address location of comparative result as total error count, is then entered step (5);
(5) all carry out following operation for inconsistent each address location of comparative result, remember that operated address location is address location i,
(51) with each negate of the data writing Si of address location i and and the corresponding positions of the sense data Si+1 of address location i carry out the operation of logical and, obtain corresponding one group of data sequence T (i, j), wherein i represents this address location, j is the data bits of this address location, if the value of T (i, j) is 1, judge that then 0-has occured the data of the j position among the address location i〉1 upset; If the value of T (i, j) is 0, judge that then 0-does not occur the data of the j position among the address location i〉1 upset;
(52) with the non-operation of carrying out logical and of the corresponding positions of the sense data Si+1 of each and the address location i of the data writing Si of address location i, obtain corresponding one group of data sequence K (i, j), if K is (i, j) value is 1, judges that then 1-has occured the data of the j position among the address location i〉0 upset; If the value of K (i, j) is 0, judge that then 1-does not occur the data of the j position among the address location i〉0 upset;
(53) add up respectively two groups of data sequences of T (i, j) and K (i, j), according to the value condition of j in the data sequence, obtain the situation that 2 or 2 above Data flippings occur address location i, finish test;
(6) with memory circuit arrangement to be measured for not reading not write state, also need to set its clock signal for the synchronous memories circuit and stop, after the accumulative total irradiation particle in the irradiation process reaches standard, stop irradiation; Setting its clock signal for the synchronous memories circuit replys, then call over the data in each address location of memory circuitry to be measured and compare with data writing, then directly call over the data in each address location of memory circuitry to be measured and compare with data writing for the asynchronous memory circuit, the quantity of the inconsistent address location of comparative result as total error count, is finished test.
2. the general purpose single particle effect detection method of a kind of memory circuitry according to claim 1, it is characterized in that: described test vector is: " 00 ", " FF ", " 55 ", " AA ", " 55 "+" AA ", " 00 "+" FF ", perhaps MARCH.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642725B2 (en) * | 2001-06-28 | 2003-11-04 | Chung-Shan Institute Of Science And Technology | Method of testing radiation for a SDRAM |
| CN101017193A (en) * | 2007-03-09 | 2007-08-15 | 北京芯技佳易微电子科技有限公司 | Testing method for irradiation of memory and device for implementing method thereof |
| CN101458299A (en) * | 2008-12-31 | 2009-06-17 | 成都华微电子***有限公司 | On site programmable gate array single particle effect test method |
| CN102243502A (en) * | 2011-03-22 | 2011-11-16 | 北京时代民芯科技有限公司 | Temperature control system and method for performing single event effect test under same |
-
2012
- 2012-11-30 CN CN2012105126204A patent/CN103021469A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642725B2 (en) * | 2001-06-28 | 2003-11-04 | Chung-Shan Institute Of Science And Technology | Method of testing radiation for a SDRAM |
| CN101017193A (en) * | 2007-03-09 | 2007-08-15 | 北京芯技佳易微电子科技有限公司 | Testing method for irradiation of memory and device for implementing method thereof |
| CN101458299A (en) * | 2008-12-31 | 2009-06-17 | 成都华微电子***有限公司 | On site programmable gate array single particle effect test method |
| CN102243502A (en) * | 2011-03-22 | 2011-11-16 | 北京时代民芯科技有限公司 | Temperature control system and method for performing single event effect test under same |
Non-Patent Citations (1)
| Title |
|---|
| 杜守刚: "通用存储器单粒子效应测试***研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》, no. 10, 15 October 2010 (2010-10-15), pages 137 - 15 * |
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| CN110045204A (en) * | 2019-04-26 | 2019-07-23 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Single event latch-up maintains current test method, apparatus and system |
| CN110045204B (en) * | 2019-04-26 | 2021-09-07 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Single event latch-up holding current test method, device and system |
| CN112216336A (en) * | 2020-08-28 | 2021-01-12 | 珠海欧比特宇航科技股份有限公司 | Memory single-particle testing method and system |
| CN112216336B (en) * | 2020-08-28 | 2024-04-30 | 珠海欧比特宇航科技股份有限公司 | Memory single particle testing method and system |
| CN112649715A (en) * | 2020-12-14 | 2021-04-13 | 兰州空间技术物理研究所 | Laser single event effect test method for 3D stacked memory |
| CN112649715B (en) * | 2020-12-14 | 2023-07-28 | 兰州空间技术物理研究所 | Laser single event effect test method of 3D (three-dimensional) stacked memory |
| CN113012749A (en) * | 2021-01-06 | 2021-06-22 | 北京航空航天大学 | Method for detecting single event effect of Flash memory |
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