CN103020008B - The reconfigurable micro server that computing power strengthens - Google Patents
The reconfigurable micro server that computing power strengthens Download PDFInfo
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- CN103020008B CN103020008B CN201210575648.2A CN201210575648A CN103020008B CN 103020008 B CN103020008 B CN 103020008B CN 201210575648 A CN201210575648 A CN 201210575648A CN 103020008 B CN103020008 B CN 103020008B
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Abstract
The invention provides the reconfigurable micro server that a kind of computing power strengthens, comprising: microprocessor, system bus, internal memory, restructural acceleration components and input/output peripheral; Wherein, microprocessor, internal memory and input/output peripheral are connected to system bus, thus microprocessor carries out exchanges data by system bus and internal memory and input/output peripheral; And microprocessor is connected directly to restructural acceleration components; Further, restructural acceleration components is connected to system bus, thus carries out exchanges data by system bus and internal memory and input/output peripheral; Wherein, restructural acceleration components comprises at least one in reconfigurable instruction expanding element, reconfigurable hardware thread units and reconfigurable task accelerator module.
Description
Technical field
The present invention relates to computing technique field, more particularly, the present invention relates to the reconfigurable micro server that a kind of computing power strengthens.
Background technology
Along with the continuous increase of the server farms in data center and enterprise-level field, the problem of data center and Iarge-scale system not energy efficient is more outstanding and serious, system power dissipation unnecessary consumption and waste, the power consumption utilization factor of data center is less than 10%, and the overall Cost Problems brought thus is also outstanding all the more.Data show, the energy expenditure of the annual server consumption in the whole world has accounted for the half of server buying expenses.
In this context, microserver (Micro Server) progresses into the visual field of people, the proposition of its concept can trace back to 2009 the earliest, it be in Intel about cloud data center to a kind of innovative idea that the basis of low-power server demand is advocated, comprise Intel, the Main Processor Unit manufacturer of AMD, ARM is all proposed low power processor towards microserver application, the main servers manufacturers such as HP, Dell have also released one after another its microserver product.Microserver adopts novel low power processor, compare traditional server efficiency higher, volume is less, and therefore in the cabinet of same size, integration density is higher, is mainly used in the network service such as unique host, static Web pages support less to computational resource requirements at present.
Current microserver is in order to improve efficiency and the node density of system, main employing low power processor or other low-power consumption miniaturized device carry out constructing system, cause it in the absolute performance of each side such as computing power, storage capacity, I/O ability lower than existing standard server, limit application and the popularization of microserver.
Therefore, it is desirable to provide that a kind of computing power strengthens and the server that can not cause system power dissipation unnecessary consumption and waste.
Summary of the invention
Technical matters to be solved by this invention is for there is above-mentioned defect in prior art, provides that a kind of computing power strengthens and can not cause the server of system power dissipation unnecessary consumption and waste.
According to the present invention, provide the reconfigurable micro server that a kind of computing power strengthens, comprising: microprocessor, system bus, internal memory, restructural acceleration components and input/output peripheral; Wherein, microprocessor, internal memory and input/output peripheral are connected to system bus, thus microprocessor carries out exchanges data by system bus and internal memory and input/output peripheral; And microprocessor is connected directly to restructural acceleration components; Further, restructural acceleration components is connected to system bus, thus carries out exchanges data by system bus and internal memory and input/output peripheral; Wherein, restructural acceleration components comprises at least one in reconfigurable instruction expanding element, reconfigurable hardware thread units and reconfigurable task accelerator module.
Preferably, restructural acceleration components adopts programmable logic device (PLD) to realize.
Preferably, reconfigurable instruction expanding element is directly connected with microprocessor, for certain operations or operation being realized with the form of specific instruction extension unit; And reconfigurable instruction expanding element is directly connected with the data path of microprocessor, and directly perform with the certain operations of the form of specific instruction extension unit realization or operation.
Preferably, the multiple hardware threads comprised in reconfigurable hardware thread units, described multiple hardware thread runs to realize the calculation function identical with software thread in restructural acceleration components, thus realizes accelerating the thread-level of software application by the mode of hardware thread.
Preferably, reconfigurable task accelerator module accelerates the task level of application for realizing, and be reconfigured as the dedicated hardware logic unit having and realize complete application task ability, and reconfigurable task accelerator module is directly controlled and access memory and input/output peripheral by the privately owned interface of system bus or restructural acceleration components, thus whole application load is transferred to restructural acceleration components from microprocessor.
The invention provides a kind of by low-power microprocessor and the closely-coupled reconfigurable micro server system framework of restructural acceleration components, can by carrying out hardware reconstruction to restructural acceleration components, realize the restructural computing accelerating module of object-oriented application demand, the arithmetic capability of enhancing system, improves system performance and efficiency.And, reconfigurable micro server system provided by the invention instruction-level, thread-level, task level from low to high three logical levels strengthen structure and the method for system computing capacity, realize accelerating the optimizing application of various scale different characteristic and computing.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the functional block diagram of the reconfigurable micro server that computing power according to a first embodiment of the present invention strengthens.
Fig. 2 schematically shows the functional block diagram of the reconfigurable micro server that computing power according to a second embodiment of the present invention strengthens.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Along with the development of semiconductor technology and the theory of computation, some unconventional form of calculation are also risen gradually, and Reconfigurable Computation is exactly a very important class.In conventional computer system, hardware is fixing, immutable, people are by carrying out programming to realize the functions such as calculating to the software operated on its hardware, Reconfigurable Computation adopts FPGA(field programmable gate array) etc. programmable logic device (PLD), can by programming to its hardware logic, the 26S Proteasome Structure and Function of hardware in change system, thus greatly improve the dirigibility of system, by realizing the specialized hardware structure towards application-specific, overall performance and the efficiency of system can greatly be improved.Meanwhile, the power consumption of the programming devices such as the FPGA that Reconfigurable Computation adopts is also relatively low, if can combine with microserver, while maintenance low-power consumption, must improve the processing power of microserver greatly.
And, instruction-level, thread-level, task level from low to high three logical levels realize structure that system computing capacity strengthens and method, can flexible combination and reconstruct, realization is accelerated the optimizing application of various scale, different characteristic and computing, gives full play to the restructural computing acceleration capacity of reconfigurable micro server.
Thus, the invention provides a kind of by low-power microprocessor and the closely-coupled reconfigurable micro server system framework of restructural acceleration components, can by carrying out hardware reconstruction to restructural acceleration components, realize the restructural computing accelerating module of object-oriented application demand, the arithmetic capability of enhancing system, improves system performance and efficiency.And, reconfigurable micro server system provided by the invention instruction-level, thread-level, task level from low to high three logical levels strengthen structure and the method for system computing capacity, realize accelerating the optimizing application of various scale different characteristic and computing.
< first embodiment >
Fig. 1 schematically shows the functional block diagram of the reconfigurable micro server that computing power according to a first embodiment of the present invention strengthens.
Comprise according to the reconfigurable micro server that the computing power of the embodiment of the present invention strengthens: microprocessor 10, system bus 100, internal memory 20, restructural acceleration components 40 and input/output peripheral (hereinafter referred to as I/O peripheral hardware) 30.
Wherein, microprocessor 10, internal memory 20 and input/output peripheral 30 are connected to system bus 100, thus microprocessor 10 carries out exchanges data by system bus 100 and internal memory 20 and input/output peripheral 30.
Microprocessor 10 is connected directly to restructural acceleration components 40; Further, restructural acceleration components 40 is connected to system bus 100, thus carries out exchanges data by system bus 100 and internal memory 20 and input/output peripheral 30.
Such as, I/O peripheral hardware 30 includes but not limited to the equipment such as hard disk, network, USB.
Wherein, such as, restructural acceleration components 40 comprises: reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42 and reconfigurable task accelerator module 43.
That is, restructural acceleration components can be reconstructed into the restructural computing accelerating modules such as reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42, reconfigurable task accelerator module 43, thus realizes accelerating in the calculating of instruction-level, thread-level, task level three levels.
And, although in above-mentioned specific embodiment, show the example that restructural acceleration components 40 comprises reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42 and reconfigurable task accelerator module 43, but it should be understood that, when specific implementation, restructural acceleration components 40 may only include in reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42 and reconfigurable task accelerator module 43 one or two.
Wherein, reconfigurable instruction expanding element 41 is directly connected with microprocessor, for certain operations or operation being realized with the form of specific instruction extension unit; And reconfigurable instruction expanding element 41 is directly connected with the data path of microprocessor, and directly perform with the certain operations of the form of specific instruction extension unit realization or operation.
For conventional computing or operation in some application, can by its abstract be extended instruction, realize in reconfigurable instruction expanding element, the instruction set extension as microprocessor realizes computing acceleration.Reconfigurable instruction expanding element 41 is directly closely connected with microprocessor by Microprocessor Interface, can some are conventional or computing that efficiency is lower or operation realize with the form of specific instruction extension unit, by hardware flowing water or parallel method optimizing and the execution performance and the efficiency that improve original operation.And, reconfigurable instruction expanding element 41 is directly connected with the data path of microprocessor, when processor intrinsic instruction efficiency is lower or calculation resources is subject in limited time, this part command operating can performed by heavy instruction extension unit 41, thus extend the calculation resources of microprocessor, enhance its arithmetic capability.
Multiple hardware threads of comprising in reconfigurable hardware thread units 42 (hardware thread 1 in such as Fig. 1, hardware thread 2 ..., hardware thread 3, hardware thread 4), described multiple hardware thread runs to realize the calculation function identical with software thread in restructural acceleration components, thus realizes accelerating the thread-level of software application by the mode of hardware thread.
Reconfigurable hardware thread units 42 realizes accelerating the thread-level of traditional software application by the mode of hardware thread.Hardware thread operates in restructural acceleration components, can realize the calculation function identical with software thread, can by large for some calculated amount in application, and the thread of limited performance is transferred in reconfigurable hardware thread units, realizes with the form of hardware thread.The computing acceleration capacity of reconfigurable hardware thread units 42 is mainly reflected in two aspects, the degree of parallelism that can improve thread on the one hand, traditional software thread runs in the microprocessor, although be conceptually executed in parallel, but in fact can only the limited computational resource of multiplex processor inside, and in reconfigurable hardware thread units, can a large amount of hardware thread unit of instantiation, for each thread provides independently computational resource, realize real thread parallel; Operational performance and the efficiency that can improve single thread on the other hand, reconfigurable hardware thread units can be reconstructed into the dedicated hardware logic structure for optimizing application, avoid the overhead that instruction scheduling, process switching etc. bring, operational performance can also be improved by flowing water, the mode such as parallel, realize the raising of thread execution efficiency and the enhancing of operational performance.
Reconfigurable task accelerator module 43 accelerates the task level of application for realizing, and it according to practical application request, can be reconstructed into the dedicated hardware logic unit having and realize complete application task ability.And, reconfigurable task accelerator module 43 can directly be controlled and access memory 20 and input/output peripheral 30 by the privately owned interface of system bus or restructural acceleration components, thus whole application load is transferred to restructural acceleration components from microprocessor, reduce the computing load of microprocessor, can also improve its operational performance by the hardware optimization such as streamlined, parallelization method, the task level computing realizing application is accelerated simultaneously.
In the application of reconfigurable micro server, above-mentioned three kinds of functional parts can according to application characteristic and actual demand, flexible combination and reconstruct, realizes the efficient collaborative of microprocessor and restructural acceleration components, improves the efficiency of the whole operational performance of system.
< second embodiment >
Fig. 2 schematically shows the functional block diagram of the reconfigurable micro server that computing power according to a second embodiment of the present invention strengthens.
With the first embodiment shown in Fig. 1 unlike, in the reconfigurable micro server that the computing power according to a second embodiment of the present invention shown in Fig. 2 strengthens, restructural acceleration components 30 can connect independently internal memory 21, independently I/O peripheral hardware 31 and other expansion interface, thus expands and strengthen system resource and ability.
In addition, it should be noted that, unless otherwise indicated, otherwise the term " first " in instructions, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in instructions, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (2)
1. a reconfigurable micro server for computing power enhancing, is characterized in that comprising: microprocessor, system bus, internal memory, restructural acceleration components and input/output peripheral;
Wherein, microprocessor, internal memory and input/output peripheral are connected to system bus, thus microprocessor carries out exchanges data by system bus and internal memory and input/output peripheral;
And microprocessor is connected directly to restructural acceleration components;
Further, restructural acceleration components is connected to system bus, thus carries out exchanges data by system bus and internal memory and input/output peripheral;
Wherein, restructural acceleration components comprises reconfigurable instruction expanding element, reconfigurable hardware thread units and reconfigurable task accelerator module;
Wherein, reconfigurable instruction expanding element is directly connected with microprocessor, for certain operations or operation being realized with the form of specific instruction extension unit; And reconfigurable instruction expanding element is directly connected with the data path of microprocessor, and directly perform with the certain operations of the form of specific instruction extension unit realization or operation;
And, the multiple hardware threads comprised in reconfigurable hardware thread units, described multiple hardware thread runs to realize the calculation function identical with software thread in restructural acceleration components, thus realizes accelerating the thread-level of software application by the mode of hardware thread;
And, reconfigurable task accelerator module accelerates the task level of application for realizing, and be reconfigured as the dedicated hardware logic unit having and realize complete application task ability, and reconfigurable task accelerator module is directly controlled and access memory and input/output peripheral by the privately owned interface of system bus or restructural acceleration components, thus whole application load is transferred to restructural acceleration components from microprocessor.
2. the reconfigurable micro server of computing power enhancing according to claim 1, is characterized in that, restructural acceleration components adopts programmable logic device (PLD) to realize.
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| US9917746B2 (en) * | 2014-11-04 | 2018-03-13 | Futurewei Technologies, Inc. | Adaptive allocation of server resources |
| CN104657330A (en) * | 2015-03-05 | 2015-05-27 | 浪潮电子信息产业股份有限公司 | High-performance heterogeneous computing platform based on x86 architecture processor and FPGA |
| CN108536526B (en) * | 2017-03-02 | 2022-09-13 | 腾讯科技（深圳）有限公司 | Resource management method and device based on programmable hardware |
| CN109254859B (en) * | 2018-09-12 | 2021-10-26 | 中国人民解放军国防科技大学 | Multilayer-control self-adaptive micro-service system |
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| CN101630305A (en) * | 2008-07-16 | 2010-01-20 | 中国人民解放军信息工程大学 | Flexible management method for reconfigurable components in high-efficiency computer |
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