CN102999077B - Current leveling circuit with high linear compensation - Google Patents
Current leveling circuit with high linear compensation Download PDFInfo
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- CN102999077B CN102999077B CN201210509155.9A CN201210509155A CN102999077B CN 102999077 B CN102999077 B CN 102999077B CN 201210509155 A CN201210509155 A CN 201210509155A CN 102999077 B CN102999077 B CN 102999077B
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Abstract
The invention provides a current leveling circuit with high linear compensation, belongs to the field of circuit and electronics and overcomes the disadvantage of insufficient linearity of the existing current injection compensation unit so as to realize the high linear compensation. The current leveling circuit comprises a current detection module and a current injection compensation module, wherein the current detection module is used for detecting changing current DeltaIcore generated by current Icore flowing through a password core circuit, converting the changing current deltaIcore into corresponding changing voltage DeltaV, and transmitting the changing voltage DeltaV to the current injection compensation module; the current injection compensation module is used for linearly converting the changing voltage DeltaV into compensation current DeltaIR, compensating the compensation current DeltaIR for the changing current DeltaIcore so as to offset the total changing current DeltaItot detected by a power supply end; and the current injection compensation module consists of an amplifier A, a third PMOS (P-channel metal oxide semiconductor) transistor M3, a fourth PMOS transistor M4, and a fifth to tenth NMOS (N-channel metal oxide semiconductor) transistors M5 to M10. The current leveling circuit provided by the invention can conceal the change of core current of a chip, and can be widely applied to encryption.
Description
Technical field
The present invention relates to electric circuit electronics technical field, be specifically related to the smooth circuit structure of electric current of high linear compensation for resisting the Differential power attack analysis of crypto chip.
Background technology
The encryption devices such as smart card are able to widespread use in the various industry departments such as telecommunications, finance, enterprise security and government, and its safe importance is self-evident.Although the embedded characteristic of encryption device makes assailant cannot directly contact the key information in crypto chip, but can leak the certain side such as power consumption, electromagnetic radiation channel information when crypto chip work, differential power consumption analysis (Differential Power Analysis, DPA) attack technology utilizes the correlativity between key data and these information, can analyze the value that draws key by modes such as mathematical statisticss.Due to the noninvasive that DPA attacks, universality and the feature such as simple, its security to crypto chips such as smart cards has caused serious threat.Opposing DPA attacks the correlativity that the most basic thought is the data that use while eliminating the working current of crypto chip and its execution algorithm.
The electric current of the power supply end of the smooth technology of electric current by making crypto chip keeps relatively constant, has eliminated the correlativity of data in the power consumption of crypto chip and cryptographic algorithm, can increase assailant's attack difficulty, is a kind of practical defence measure.Compared with other safeguard procedures, the smooth technology of electric current has a lot of advantages.First, the deviser of the smooth circuit of electric current is without internal algorithm or the circuit of understanding original encryption device, and the smooth circuit of electric current can not affect the function of original crypto chip; Moreover, other safeguard procedures relatively, the design of the smooth circuit of electric current is more simple.In order to reach the smooth effect of good electric current, in the smooth circuit of electric current, the linearity of current compensation unit just seems extremely important, and current compensation unit adopts simple trsanscondutance amplifier conventionally in existing solution, can not effectively solve the problem of linearity deficiency.
Summary of the invention
The present invention, in order to solve the deficiency of the estimated current injecting compensating unit linearity, reaches the object of high linear compensation, has proposed a kind of smooth circuit of electric current of high linear compensation.
The smooth circuit of electric current of high linear compensation of the present invention has improved the structure of electric current injecting compensating module, and it comprises current detection module 1 and electric current injecting compensating module 2;
Current detection module 1, for detection of the electric current I of the cipher core circuit of flowing through
corethe variable-current Δ I producing
core, and change variable-current Δ I
corefor the corresponding voltage Δ V that changes, also for variation voltage Δ V is sent to electric current injecting compensating module 2;
Electric current injecting compensating module 2 is offset current Δ I for changing voltage Δ V linear transformation
b, and by offset current Δ I
rto variable-current Δ I
corecompensate the variable-current Δ I that total power end is detected
totscabbled;
Current detection module 1 is respectively arranged with variable-current Δ I
corecollection terminal and variation voltage Δ V output terminal; Electric current injecting compensating module 2 is respectively arranged with and changes voltage Δ V input end and offset current Δ I
routput terminal; The variation voltage Δ V output terminal of current detection module 1 is connected with the variation voltage Δ V input end of electric current injecting compensating module 2;
Electric current injecting compensating module 2 is made up of amplifier A, the 3rd PMOS pipe M3, the 4th PMOS pipe M4 and the 5th NMOS pipe M5 to the ten NMOS pipe M10,
The grid of the 3rd PMOS pipe M3 was connected with the grid of the 4th PMOS pipe M4, the drain electrode of the 5th NMOS pipe M5, the drain electrode of the tenth NMOS pipe M10 with drain electrode short circuit while,
The source electrode of the 5th NMOS pipe M5 is connected with the in-phase input end of amplifier A with the drain electrode of the 6th NMOS pipe M6 simultaneously,
The grid of the tenth NMOS pipe M10 is connected with the output terminal of amplifier A with the grid of the 9th NMOS pipe M9 simultaneously,
The source electrode of the 9th NMOS pipe M9 is connected with the inverting input of amplifier A with the drain electrode of the 8th NMOS pipe M8 simultaneously,
The source electrode of the 8th NMOS pipe M8 is connected with the drain electrode of the 7th NMOS pipe M7,
The drain electrode of the source electrode of the 3rd PMOS pipe M3, the source electrode of the 4th PMOS pipe M4 and the 9th NMOS pipe M9 meets power end VDD,
The source ground of the source electrode of the 6th NMOS pipe M6, the source electrode of the 7th NMOS pipe M7 and the tenth NMOS pipe M10,
The grid of the 6th NMOS pipe M6 meets the 3rd bias voltage V
c, the grid of the 7th NMOS pipe M7 meets the 4th bias voltage V
dmeet the 5th bias voltage V with the grid of the 8th NMOS pipe M8
e;
The drain electrode of the 4th PMOS pipe M4 is the offset current Δ I of electric current injecting compensating module 2
routput terminal; The 4th PMOS pipe drain electrode of M4 and the ground end of cipher core circuit are connected,
The grid of the 5th NMOS pipe M5 is the variation voltage Δ V input end of electric current injecting compensating module 2.
When the present invention normally works at cipher core circuit, the electric current I of the cipher core circuit of flowing through
corecan produce Δ I
corechange, current detection module 1 detects rapidly these curent changes, and is converted to corresponding change in voltage Δ V, and then Δ V is converted to linearly offset current Δ I by electric current injecting compensating module 2
r, the total current changes delta I detecting at total power end
totto be scabbled, reached the object of hiding chip core curent change.
Brief description of the drawings
Fig. 1 is the structural representation of the smooth circuit of electric current of the high linear compensation of the present invention; Fig. 2 is the circuit diagram of the smooth circuit of electric current of the high linear compensation of the present invention; Fig. 3 is the simulation result figure of the smooth circuit of the electric current of the high linear compensation of the present invention under 0.18 μ m CMOS technique, in this figure, curve O represents the total current of the power end after smooth, curve P represents the offset current that electric current injection module produces, and curve Q represents the electric current of cipher core electric current.
Embodiment
Embodiment one: in conjunction with Fig. 1 and Fig. 2, present embodiment is described, present embodiment comprises current detection module 1 and electric current injecting compensating module 2;
Current detection module 1, for detection of the electric current I of the cipher core circuit of flowing through
corethe variable-current Δ I producing
core, and change variable-current Δ I
corefor the corresponding voltage Δ V that changes, also for variation voltage Δ V is sent to electric current injecting compensating module 2;
Electric current injecting compensating module 2 is offset current Δ I for changing voltage Δ V linear transformation
r, and by offset current Δ I
rto variable-current I
corecompensate the variable-current Δ I that total power end is detected
totscabbled;
Current detection module 1 is respectively arranged with variable-current Δ I
corecollection terminal and variation voltage Δ V output terminal; Electric current injecting compensating module 2 is respectively arranged with and changes voltage Δ V input end and offset current Δ I
routput terminal; The variation voltage Δ V output terminal of current detection module 1 is connected with the variation voltage Δ V input end of electric current injecting compensating module 2;
Electric current injecting compensating module 2 is made up of amplifier A, the 3rd PMOS pipe M3, the 4th PMOS pipe M4 and the 5th NMOS pipe M5 to the ten NMOS pipe M10,
The grid of the 3rd PMOS pipe M3 was connected with the grid of the 4th PMOS pipe M4, the drain electrode of the 5th NMOS pipe M5, the drain electrode of the tenth NMOS pipe M10 with drain electrode short circuit while,
The source electrode of the 5th NMOS pipe M5 is connected with the in-phase input end of amplifier A with the drain electrode of the 6th NMOS pipe M6 simultaneously,
The grid of the tenth NMOS pipe M10 is connected with the output terminal of amplifier A with the grid of the 9th NMOS pipe M9 simultaneously,
The source electrode of the 9th NMOS pipe M9 is connected with the inverting input of amplifier A with the drain electrode of the 8th NMOS pipe M8 simultaneously,
The source electrode of the 9th NMOS pipe M9 and the 8th NMOS manage the drain electrode short circuit of M8 and feed back to the inverting input formation negative feedback of amplifier A;
The source electrode of the 8th NMOS pipe M8 is connected with the drain electrode of the 7th NMOS pipe M7,
The drain electrode of the source electrode of the 3rd PMOS pipe M3, the source electrode of the 4th PMOS pipe M4 and the 9th NMOS pipe M9 meets power end VDD,
The source ground of the source electrode of the 6th NMOS pipe M6, the source electrode of the 7th NMOS pipe M7 and the tenth NMOS pipe M10,
The grid of the 6th NMOS pipe M6 meets the 3rd bias voltage V
c, the grid of the 7th NMOS pipe M7 meets the 4th bias voltage V
dmeet the 5th bias voltage V with the grid of the 8th NMOS pipe M8
e; The 3rd bias voltage V
c, the 4th bias voltage V
dwith the 5th bias voltage V
ecan obtain from external bias circuit;
The drain electrode of the 4th PMOS pipe M4 is the offset current Δ I of electric current injecting compensating module 2
routput terminal; The 4th PMOS pipe drain electrode of M4 and the ground end of cipher core circuit are connected,
The grid of the 5th NMOS pipe M5 is the variation voltage Δ V input end of electric current injecting compensating module 2, and the grid of the 5th NMOS pipe M5 connects the drain electrode of M2 in current detection module 1,
In circuit: the 5th NMOS pipe M5 is as source follower, and the 6th NMOS pipe M6 is operated in amplification region, and the tenth NMOS pipe M10 is operated in saturation region; The size design of the 9th NMOS pipe M9 must be larger, and due to the regulating action of the 7th NMOS pipe M7, the 8th NMOS pipe M8 and amplifier A, the source node voltage of the 9th NMOS pipe M9 equates with the drain-source voltage of the 6th NMOS pipe M6.
Embodiment two: present embodiment is described in conjunction with Fig. 2, present embodiment and embodiment one difference are that current detection module 1 is by a NMOS pipe M1, the 2nd NMOS pipe M2, the 11 NMOS pipe M11, the 12 NMOS pipe M12, the 13 PMOS pipe M13, the 14 PMOS pipe M14, the 15 PMOS pipe M15 and resistance R 1 form
The drain electrode of the one NMOS pipe M1 is the variable-current Δ I of current detection module 1
corecollection terminal, a drain electrode of NMOS pipe M1 and the ground end of cipher core circuit are connected with the grid of the 13 PMOS pipe M13 simultaneously,
The drain electrode of the grid of the one NMOS pipe M1, the grid of the 2nd NMOS pipe M2, the 12 NMOS pipe M12 is connected with the drain electrode of the 14 NMOS pipe M14,
The drain electrode of the grid of the 11 NMOS pipe M11, the grid of the 12 NMOS pipe M12, the 11 NMOS pipe M11 is connected with the drain electrode of the 13 PMOS pipe M13,
The source electrode of the 13 PMOS pipe M13, the source electrode of the 14 PMOS pipe M14 are connected with the drain electrode of the 15 PMOS pipe M15,
The 2nd NMOS pipe drain electrode of M2 and one end of resistance R 1 are connected to the variation voltage Δ V output terminal of current detection module 1; The drain node voltage of the 2nd NMOS pipe M2 is delivered to the variation voltage Δ V input end of electric current injecting compensating module 2 as the variation voltage Δ V output of current detection module 1, i.e. the grid of the 5th NMOS pipe M5,
The source electrode of one end of resistance R 1 and the 15 PMOS pipe M15 meets power end VDD,
The source electrode of the one NMOS pipe M1, the source electrode of the 2nd NMOS pipe M2, the source electrode of the 11 NMOS pipe M11 and the source ground of the 12 NMOS pipe M12,
The grid of the 14 PMOS pipe M14 meets the second bias voltage V
b, the 15 PMOS pipe M15 grid meet the first bias voltage V
a, the first bias voltage V
awith the second bias voltage V
bcan obtain from external bias circuit.
Other composition and connected mode are identical with embodiment one.
Content of the present invention is not limited only to the content of the respective embodiments described above, and the combination of one of them or several embodiments equally also can realize the object of invention.
The smooth circuit solution of the electric current details that the present invention provides as shown in Figure 2.V in circuit
a, V
b, V
c, V
dwith V
eprovide by biasing circuit Deng voltage and the required bias voltage of the normal work of amplifier.Wherein current detection module 1 is that a kind of current-mirror structure of improving (is managed M11, the 12 NMOS pipe M12 by a NMOS pipe M1, the 2nd NMOS pipe M2, the 11 NMOS, the 13 PMOS pipe M13, the 14 PMOS pipe M14, the 15 PMOS pipe M15 and resistance R
1composition).A differential amplifier of the 11 NMOS pipe M11 to the 15 PMOS pipe M15 compositions, the ground terminal voltage V of cipher core circuit
gND-Cwith the second bias voltage V
b(being provided by external bias circuit) is as the input of differential amplifier, output is as the grid voltage of a NMOS pipe M1 in current mirror and the 2nd NMOS pipe M2, by retroactive effect, the source-drain voltage of the NMOS pipe M1 in current mirror is fixed on to lower voltage value, and variation range is very little.Current-mirror structure after improving, can, ensureing that a NMOS pipe M1 and the 2nd NMOS pipe M2 always work under the prerequisite of saturation region, not have influence on the work of cipher core circuit itself, can copy fast and accurately the curent change value of cipher core circuit.The 2nd NMOS pipe M2 mono-side is converted to the variable-current of cipher core circuit the voltage of variation.When device current increases Δ I
coretime, make node N
1voltage drop Δ V, vice versa.
The variation voltage Δ V that electric current injecting compensating module 2 passes over current detection module 1 is converted to offset current Δ I
r, the offset current Δ I that electric current injecting compensating module 2 produces
rbe the copying of electric current sum of the 6th NMOS pipe M6 and two metal-oxide-semiconductors of the tenth NMOS pipe M10 of flowing through, wherein the 6th NMOS pipe M6 is operated in linear zone, and the tenth NMOS pipe M10 is operated in saturation region.Through appropriate design circuit parameter, the electric current sum of flow through the 6th NMOS pipe M6 and the tenth NMOS pipe M10 and input voltage can keep very high linear relationship.In Fig. 2, the 5th NMOS pipe M5 forms source follower, and the drain-source voltage of the 6th NMOS pipe M6 can be obtained by following formula:
Wherein β=μ
nc
oXw/L.The size that is operated in the leakage current of the 6th NMOS pipe M6 of linear zone is:
The tenth NMOS pipe M10 is operated in saturation region, and while ignoring channel-length modulation, its leakage current is:
Formula (2) and formula (3) are added, and in the 6th NMOS pipe M6 and the tenth NMOS pipe M10, current summation can obtain:
Suppose V
gS10-V
t10=V
dS6, formula (4) becomes:
ΔI
R＝β(V
GS6-V
T6)(ΔV-V
T5) (5)
By V is set
gS6-V
t6be a 3rd fixing bias voltage Vc, change voltage Δ V and output offset current Δ I
rbetween just can obtain linear relationship, β is its coefficient.
Wherein, V
gS10-V
t10=V
dS6condition can be met by appropriate design circuit parameter.The in-phase input end voltage of amplifier is drain-source voltage V
dS6, anti-phase input terminal voltage is because feedback is also fixed on V
dS6, amplifier output voltage is V
gS10.What the breadth length ratio of the 9th NMOS pipe M9 was designed is larger, and the electric current that flows through the 9th NMOS pipe M9 is I
b:
So,
V
GS10V
DS6+V
GS9V
DS6+V
T9 (7)
The bulk effect of ignoring the 9th NMOS pipe M9, has
V
T10≈V
T9 (8)
So have
V
GS10--V
T10＝V
DS6 (9)
Known by above-mentioned analysis, if put aside offset voltage impact or other factors in operational amplifier, by electric current injection module, the Δ V that current detection module 1 produces can high linear conversion offset current Δ I
r.Electric current injection module produces offset current Δ I
rv with cipher core circuit
gND-Cend, with the curent change Δ I of core circuit
corephase " counteracting ", realizes the effect of hiding cipher core curent change.
In order to assess the smooth effect of the smooth circuit of electric current of high linear compensation in the present invention, under 0.18 μ m CMOS technique, realize this circuit, and set up a circuit model that can reflect cipher core circuital current situation of change.In the emulation experiment of the smooth circuit of electric current, the driving source using the current curve sample data of this circuit model as the smooth circuit of electric current.Because the frequency of operation of encryption device is conventionally not high, emphasis has been assessed the smooth effect under low frequency (VDD=1.8V, bias voltage V
a, V
e=1V, V
b=200mV, V
c=1.8V, V
d=800mV, these bias voltages can easily obtain from external bias circuit), as shown in Figure 3.In Fig. 3, in the time that the peak-to-peak value of cipher core circuital current is about 3.43mA, the peak-to-peak value of the electric current of general supply end is about 0.18mA, can calculate thus inhibiting rate and be about 95%, greatly cut down the amplitude of variation of power end current signal, reduce the correlativity (Current-to-Data Dependency, CDD) of encryption device electric current and data, increased the difficulty that DPA attacks.
Claims (2)
1. the smooth circuit of the electric current of high linear compensation, is characterized in that it comprises current detection module (1) and electric current injecting compensating module (2);
Current detection module (1), for detection of the electric current I of the cipher core circuit of flowing through
corethe variable-current Δ I producing
core, and change variable-current Δ I
corefor the corresponding voltage Δ V that changes, also for variation voltage Δ V is sent to electric current injecting compensating module (2);
Electric current injecting compensating module (2) is offset current Δ I for changing voltage Δ V linear transformation
r, and by offset current Δ I
rto variable-current Δ I
corecompensate the variable-current Δ I that total power end is detected
totscabbled;
Current detection module (1) is respectively arranged with variable-current Δ I
corecollection terminal and variation voltage Δ V output terminal; Electric current injecting compensating module (2) is respectively arranged with and changes voltage Δ V input end and offset current Δ I
routput terminal; The variation voltage Δ V output terminal of current detection module (1) is connected with the variation voltage Δ V input end of electric current injecting compensating module (2);
Electric current injecting compensating module (2) is made up of amplifier A, the 3rd PMOS pipe M3, the 4th PMOS pipe M4 and the 5th NMOS pipe M5 to the ten NMOS pipe M10,
The grid of the 3rd PMOS pipe M3 was connected with the grid of the 4th PMOS pipe M4, the drain electrode of the 5th NMOS pipe M5, the drain electrode of the tenth NMOS pipe M10 with drain electrode short circuit while,
The source electrode of the 5th NMOS pipe M5 is connected with the in-phase input end of amplifier A with the drain electrode of the 6th NMOS pipe M6 simultaneously,
The grid of the tenth NMOS pipe M10 is connected with the output terminal of amplifier A with the grid of the 9th NMOS pipe M9 simultaneously,
The source electrode of the 9th NMOS pipe M9 is connected with the inverting input of amplifier A with the drain electrode of the 8th NMOS pipe M8 simultaneously,
The source electrode of the 8th NMOS pipe M8 is connected with the drain electrode of the 7th NMOS pipe M7,
The drain electrode of the source electrode of the 3rd PMOS pipe M3, the source electrode of the 4th PMOS pipe M4 and the 9th NMOS pipe M9 meets power end VDD,
The source ground of the source electrode of the 6th NMOS pipe M6, the source electrode of the 7th NMOS pipe M7 and the tenth NMOS pipe M10,
The grid of the 6th NMOS pipe M6 meets the 3rd bias voltage V
c, the grid of the 7th NMOS pipe M7 meets the 4th bias voltage V
dmeet the 5th bias voltage V with the grid of the 8th NMOS pipe M8
e;
The drain electrode of the 4th PMOS pipe M4 is the offset current Δ I of electric current injecting compensating module (2)
routput terminal; The 4th PMOS pipe drain electrode of M4 and the ground end of cipher core circuit are connected,
The grid of the 5th NMOS pipe M5 is the variation voltage Δ V input end of electric current injecting compensating module (2).
2. the smooth circuit of the electric current of a kind of high linear compensation according to claim 1, it is characterized in that its current detection module (1) is by a NMOS pipe M1, the 2nd NMOS pipe M2, the 11 NMOS pipe M11, the 12 NMOS pipe M12, the 13 PMOS pipe M13, the 14 PMOS pipe M14, the 15 PMOS pipe M15 and resistance R 1 form
The drain electrode of the one NMOS pipe M1 is the variable-current Δ I of current detection module (1)
corecollection terminal, the drain electrode of a NMOS pipe M1 is connected with the ground end of cipher core circuit with the grid of the 13 PMOS pipe M13 simultaneously,
The drain electrode of the grid of the one NMOS pipe M1, the grid of the 2nd NMOS pipe M2, the 12 NMOS pipe M12 is connected with the drain electrode of the 14 PMOS pipe M14,
The drain electrode of the grid of the 11 NMOS pipe M11, the grid of the 12 NMOS pipe M12, the 11 NMOS pipe M11 is connected with the drain electrode of the 13 PMOS pipe M13,
The source electrode of the 13 PMOS pipe M13, the source electrode of the 14 PMOS pipe M14 are connected with the drain electrode of the 15 PMOS pipe M15,
The 2nd NMOS pipe drain electrode of M2 and one end of resistance R 1 are connected to the variation voltage Δ V output terminal of current detection module (1);
The source electrode of one end of resistance R 1 and the 15 PMOS pipe M15 meets power end VDD,
The source electrode of the one NMOS pipe M1, the source electrode of the 2nd NMOS pipe M2, the source electrode of the 11 NMOS pipe M11 and the source ground of the 12 NMOS pipe M12,
The grid of the 14 PMOS pipe M14 meets the second bias voltage V
b, the 15 PMOS pipe M15 grid meet the first bias voltage V
a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210509155.9A CN102999077B (en) | 2012-12-03 | 2012-12-03 | Current leveling circuit with high linear compensation |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210509155.9A CN102999077B (en) | 2012-12-03 | 2012-12-03 | Current leveling circuit with high linear compensation |
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| CN102999077B true CN102999077B (en) | 2014-08-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104283673A (en) * | 2014-10-09 | 2015-01-14 | 东南大学 | Random and dynamic voltage regulation anti-attack method for password circuit system and circuit system |
| US10255462B2 (en) * | 2016-06-17 | 2019-04-09 | Arm Limited | Apparatus and method for obfuscating power consumption of a processor |
| CN107104591A (en) * | 2017-05-27 | 2017-08-29 | 成都为远信安电子科技有限公司 | A kind of power-supply system of safety chip resisting differential power consumption attack |
| CN108446556B (en) * | 2018-03-01 | 2020-04-07 | 北京智芯微电子科技有限公司 | Power consumption resisting analysis circuit and method for cryptographic chip |
| CN109617162B (en) * | 2018-12-17 | 2022-08-09 | 思瑞浦微电子科技（苏州）股份有限公司 | Circuit and method for compensating linearity of charging current |
| CN110716604B (en) * | 2019-10-11 | 2023-06-13 | 哈尔滨理工大学 | Protection circuit for resisting power consumption attack based on current leveling technology |
| CN110597339A (en) * | 2019-10-11 | 2019-12-20 | 哈尔滨理工大学 | Circuit for protecting password chip from power consumption analysis attack |
| CN113485511B (en) * | 2021-07-05 | 2022-05-10 | 哈尔滨工业大学（威海） | Band gap reference circuit with low temperature coefficient |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360715A (en) * | 1999-05-11 | 2002-07-24 | 格姆普拉斯公司 | Countermeasure method in electronic component using dynamic secret key cryptographic algorithm |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4117008B2 (en) * | 2006-10-30 | 2008-07-09 | シャープ株式会社 | Encryption device |
-
2012
- 2012-12-03 CN CN201210509155.9A patent/CN102999077B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360715A (en) * | 1999-05-11 | 2002-07-24 | 格姆普拉斯公司 | Countermeasure method in electronic component using dynamic secret key cryptographic algorithm |
Non-Patent Citations (6)
| Title |
|---|
| 乐大珩.抗功耗攻击的密码芯片电路级防护关键技术研究.《中国博士学位论文全文数据库》.2012, |
| 加密芯片的旁道攻击防御对策研究;李海军;《中国博士学位论文全文数据库》;20100430;全文 * |
| 抗功耗攻击的安全SoC设计与实现关键技术研究;童元满;《中国博士学位论文全文数据库》;20100430;全文 * |
| 抗功耗攻击的密码芯片电路级防护关键技术研究;乐大珩;《中国博士学位论文全文数据库》;20120331;全文 * |
| 李海军.加密芯片的旁道攻击防御对策研究.《中国博士学位论文全文数据库》.2010, |
| 童元满.抗功耗攻击的安全SoC设计与实现关键技术研究.《中国博士学位论文全文数据库》.2010, |
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| CN102999077A (en) | 2013-03-27 |
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