CN102983130A - An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof - Google Patents
An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof Download PDFInfo
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- CN102983130A CN102983130A CN2011102609006A CN201110260900A CN102983130A CN 102983130 A CN102983130 A CN 102983130A CN 2011102609006 A CN2011102609006 A CN 2011102609006A CN 201110260900 A CN201110260900 A CN 201110260900A CN 102983130 A CN102983130 A CN 102983130A
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- ggmos
- integrated circuit
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Abstract
The present invention discloses an electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof. The protection circuit includes a GGMOS and at least one through-silicon via which share the same substrate; and the silicon via is arranged in the substrate around the GGMOS. In the electro-static discharge protection circuit for the integrated circuit of the present invention, when the ESD (electro-static discharge) is produced, heat will be generated on the GGMOS due to the presence of the ESD current; by using the silicon via disposed in the substrate around the GGMOS, better and faster heat dissipation for the GGMOS can be achieved, thus preventing damage to the GGMOS caused by heat, and extending the service life of the electro-static discharge protection circuit; and GGMOS turn-on voltage adjustment can also be achieved by arrangement mode of silicon vias at the same time. According to the protection circuit, the size of the GGMOS is reduced, so that the entire region GGMOS is enabled to be completely open when the ESD is produced, thereby improving utilization rate of the GGMOS.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of integrated circuit static release protection circuit and manufacture method thereof.
Background technology
ESD (Electro-Static discharge, static discharge) is a kind of quick N-process of electric charge.Because electrostatic potential is very high, ESD can bring destructive consequence to integrated circuit, causes the inefficacy of integrated circuit.Therefore, for Protective IC exempts from the infringement of ESD, esd protection circuit design simultaneously damages because being subject to ESD to prevent integrated circuit in integrated circuit.
At CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) in the technology, NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide semiconductor (MOS)) device includes parasitic horizontal npn triode.At present; often adopt GGNMOS (Gate Grounded NMOS; grounded-grid N-type metal-oxide semiconductor (MOS)) as static release protection circuit; if the parasitic triode of GGNMOS has the ability of processing large electric current; then under snapback (rebound) state, the ESD electric current that GGNMOS can release large.
As shown in Figure 1, be the GGNMOS structural representation.P type substrate 1a, grid 3a and the equal ground connection of source electrode 4a of this GGNMOS, drain electrode 2a is connected with protected circuit in the integrated circuit.Under the integrated circuit normal operation, GGNMOS can conducting.When ESD occurs, static discharge current I
ESD2a flows into GGNMOS by drain electrode, and snowslide will occur for the drain electrode 2a of GGNMOS and the depletion region of substrate 1a, and be accompanied by the generation of electron hole pair.The hole that a part produces is absorbed by source electrode 4a, and remaining flowing through substrate 1a (produces substrate current I
Sub), again because there is resistance substrate R in substrate 1a
Sub, so that underlayer voltage U
SubImprove (U
Sub=I
Sub* R
Sub), immediately, its parasitic triode is started working so that drain current constantly increases, simultaneously so that voltage constantly descend.If electric current continues to increase to certain value, just then second breakdown might occur NMOS, the puncture of this moment is irreversible, then finally causes the damage of NMOS.
Fig. 2 is current-voltage rebound (snapback) performance diagram of above-mentioned GGNMOS.(V wherein
T1, I
T1) be the PN junction positively biased between substrate 1a and the source electrode 4a, the electric current and voltage when lateral transistor is opened; (V
h, I
h) be clamping voltage and the electric current of NMOS lateral transistor; (V
T2, I
T2) voltage and current when being NMOS lateral transistor generation second breakdown.
In the prior art, the plan structure of a GGNMOS circuit that is typically applied in esd protection as shown in Figure 3.The structure of this GGNMOS circuit is: form source-drain area 5 at substrate; the interval arranges drain electrode 2b and source electrode 4b in the source-drain area 5; grid 3b adopts many finger-like (multiple-finger) to design and be arranged between drain electrode 2b and the source electrode 4b; the outside of source-drain area 5 is provided with pick-up area 7 (pickup) pick-up area 7 and is connected with substrate; be used for the electric current conduction between substrate and the external world; be respectively equipped with a plurality of contact plug 8 (contact plug) at drain electrode 2b and source electrode 4b; be used for the static conduction; contact plug 8 at drain electrode 2b is gone back connection metal line 6, is used for being connected with the protected circuit of integrated circuit.Wherein, substrate, drain electrode 2b, grid 3b and source electrode 4b have consisted of NMOS jointly, and substrate, grid 3b and the equal ground connection of source electrode 4b formed GGNMOS (substrate is by pick-up area 7 ground connection), its laterally long and wide size be the length and width size of source-drain area 5.During use, metal wire 6 is connected with protected circuit in the integrated circuit, and substrate is by pick-up area 7 ground connection, and source electrode 4b is by contact plug 8 ground connection on it, grid 3b ground connection.When ESD produces; ESD is delivered to drain electrode 2b by metal wire 6, the upper contact plug 8 that arranges of drain electrode 2b; and by contact plug 8 derivation on substrate, pick-up area 7, grid 3b and the source electrode 4b, thereby realization is to the esd protection of the protected circuit in the integrated circuit.In the practical application, in order to conduct large ESD electric current, the size that in general the GGNMOS circuit is made is larger, and adopts the polysilicon gate (poly gate) of many finger-like shown in Figure 3.
But in actual use, above-mentioned larger-size many finger-like GGNMOS circuit but exists certain defective.Reason is, because size is larger, and everywhere resistance substrate (R on this many finger-like GGNMOS circuit
Sub) difference: the mid portion of many finger-like GGNMOS is because far away apart from pick-up area 7, and its resistance substrate is larger, and the resistance substrate of other parts is along with distance pick-up area 7 more and more closely becomes more and more less.Like this, when ESD occurs, as shown in Figure 4, the mid portion of above-mentioned many finger-like GGNMOS circuit is opened prior to other parts, form ESD and open zone 10, other parts are opened gradually along with the increase of ESD electric current, and then the scope in ESD unlatching zone 10 increases gradually.In the ideal situation, when arriving a certain moment, can realize the unlatching of whole many finger-like GGNMOS circuit, but the ESD electric current of the conduction of intermediate portion is still large than the ESD electric current that other parts are conducted, thereby the heat that brings is also just larger, so just causes easily its damage.And in actual applications, above-mentioned many finger-like GGNMOS circuit, often only the intermediate portion to the conduction generation effect of ESD electric current, and near its marginal portion very little to the conduction of ESD electric current.Simultaneously, mid portion reduces the useful life of integrated circuit because conduction current is larger, and the heat of its generation also should not dissipate rapidly, causes easily the premature aging of device.
Summary of the invention
In view of this, the invention provides a kind of novel integrated circuit static release protection circuit, when effectively discharging ESD to prolong the useful life of protective circuit and integrated circuit.
Technical scheme of the present invention is achieved in that
A kind of integrated circuit static release protection circuit comprises GGMOS and at least 1 silicon through hole of sharing same substrate, and described silicon through hole is arranged in the GGMOS substrate on every side.
Further, described integrated circuit static release protection circuit also comprises the pick-up area that is arranged on the described substrate and centers on described GGMOS and silicon through hole.
Further, the length of described GGMOS is not more than 2/3 of described pick-up area length, and the width of described GGMOS is not more than 2/3 of described pick-up area width.
Further, the length of described GGMOS is 1/3～1/2 of described pick-up area length, and the width of described GGMOS is 1/3～1/2 of described pick-up area width.
Further, the thermal conductivity of the material in the described silicon through hole is greater than the thermal conductivity of silicon.
Further, the material in the described silicon through hole is Cu or W.
Further, described GGMOS is GGNMOS or GGPMOS.
Further, described GGNMOS is many finger-like GGNMOS.
Further, described many finger-like GGNMOS comprises described substrate, is provided with source-drain area at described substrate, in described source-drain area, is interval with drain electrode and source electrode, and many finger-like grid is arranged between drain electrode and the source electrode.
Further, be respectively equipped with the contact plug of conducting for static in described drain electrode and source electrode, connect for the metal wire that is connected with the protected circuit of integrated circuit in the contact plug that drains.
The present invention provides the manufacture method of said integrated circuit static release protection circuit simultaneously, is included in the step of preparation GGMOS on the substrate, and prepares the step of silicon through hole in the same substrate around the GGMOS.
Can find out from such scheme; in the integrated circuit static release protection circuit of the present invention; when ESD produces; because the existence of ESD electric current can produce heat at GGMOS, utilize the silicon through hole that is arranged in the GGMOS substrate on every side; just can realize GGMOS is carried out faster and better heat radiation; thereby avoid heat to the damage of GGMOS, prolonged the useful life of static release protection circuit, the arrangement mode of silicon through hole also can be realized the cut-in voltage of GGMOS is regulated simultaneously.The present invention has reduced the size of GGMOS simultaneously, thereby when ESD occurs, can so that the Zone Full of whole GGMOS is opened fully, improve the utilance of GGMOS.
Description of drawings
Fig. 1 is the structural representation of GGNMOS;
Fig. 2 is the current-voltage curve figure of GGNMOS;
Fig. 3 is the plan structure figure of a kind of GGNMOS for esd protection of the prior art;
Fig. 4 is that GGNMOS shown in Figure 3 forms the schematic diagram that ESD opens the zone when ESD occurs;
Fig. 5 is the plan structure figure of an embodiment of integrated circuit static release protection circuit of the present invention.
In the accompanying drawing, the list of parts of each label representative is as follows:
1a, substrate, 2a, drain electrode, 3a, grid, 4a, source electrode, 2b, drain electrode, 3b, grid, 4b, source electrode, 5, source-drain area, 6, metal wire, 7, pick-up area, 8, contact plug, 9, the silicon through hole, 10, ESD opens the zone
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
As a specific embodiment, integrated circuit electrostatic discharge protection circuit structure of the present invention as shown in Figure 5.In the situation that does not change pick-up area 7 sizes of the prior art, reduce the length and width size of GGNMOS, the length and width size that is about to source-drain area 5 is dwindled, and forms a plurality of silicon through holes 9 (TSV, Through Silicon Via) in the substrate between source-drain area 5 and pick-up area 7.Specifically, integrated circuit electrostatic discharge protection circuit structure of the present invention is: form source-drain area 5 at substrate, and the size of this source-drain area 5 is less than source-drain area size of the prior art; In the source-drain area 5, the interval arranges drain electrode 2b and source electrode 4b, and grid 3b adopts many finger-like (multiple-finger) to design and be arranged between drain electrode 2b and the source electrode 4b; Silicon through hole 9 more than 1 or 1 is set in the substrate around the source-drain area 5, and the quantity of silicon through hole 9 can be carried out multiple choices as required; Outside substrate at source-drain area 5 and silicon through hole 9 arranges pick-up area 7 (pickup), and source-drain area 5 and silicon through hole 9 are centered around in this pick-up area 7, and the size of pick-up area is suitable in the size of pick-up area 7 and the prior art; Be respectively equipped with a plurality of contact plug 8 (contact plug) at drain electrode 2b and source electrode 4b, be used for the static conduction, connection metal line 6 on the contact plug 8 of drain electrode 2b is used for being connected with the protected circuit of integrated circuit.
Substrate, drain electrode 2b, grid 3b and source electrode 4b have consisted of NMOS jointly, and the equal ground connection of substrate, grid 3b and source electrode 4b forms GGNMOS (substrate is by pick-up area 7 ground connection), the horizontal length of this GGNMOS and wide size are the length and width size of source-drain area 5, its position is arranged at the core in the pick-up area 7 substantially, because drain electrode 2b, source electrode 4b and grid 3b form at source-drain area 5, therefore source-drain area 5 residing positions namely are the residing positions of this GGNMOS, the length and width size of source-drain area 5 is dwindled, and namely is dwindling of GGNMOS length and width size.
Consider the setting of silicon through hole 9, the length and width size of GGNMOS should satisfy the scope that silicon through hole 9 can be set, be not more than 2/3 of pick-up area 7 length such as the length of GGNMOS being arranged at, the width of GGNMOS be arranged at be not more than 2/3 of pick-up area 7 width.The scope that ESD opens zone 10 among the GGNMOS when occuring with reference to ESD among Fig. 4 is part therebetween only, the size of this scope is about half of the length and width size of pick-up area 7, therefore the length and width size of the GGNMOS among the present invention can preferably be arranged at half less than or equal to the length and width size of pick-up area 7, thereby can open fully GGNMOS when ESD occurs.But, too small GGNMOS length and width size so that the release channel of ESD narrow down, thereby be unfavorable for the release of ESD, so the length and width size of GGNMOS can not be too small, it can be arranged at more than or equal to 1/3 of the length and width size of pick-up area 7.
Silicon through hole 9 can adopt the various arrangement mode to be arranged in the substrate between GGNMOS and the pick-up area 7 as required, its size and and GGNMOS (source-drain area 5) between distance also can carry out as required multiple setting.It should be noted that, the thermal conductivity of the material that adopts in the silicon through hole 9 is greater than the thermal conductivity of silicon, and (silicon is to make one of semiconductor, the employed main material of integrated circuit, as as backing material, its thermal conductivity is 149W/mK (watt/meter Kelvin)), as adopt metal Cu (copper, copper, thermal conductivity 401W/mK) or metal W (wolfram, tungsten, thermal conductivity 173W/mK) etc.The reason that silicon through hole 9 is set is: when ESD produces, because the existence of ESD electric current can produce heat at GGNMOS, if this heat can in time dissipate, then can prolong greatly the useful life of GGNMOS.In the substrate around the GGNMOS, silicon through hole 9 is set and fills thermal conductivity greater than the metal (such as Cu or W) of Si (silicon, silicon), just can realize the faster and better heat radiation to GGNMOS, to prolong the useful life of GGNMOS.On the other hand, the arrangement mode of silicon through hole 9 also can be used for the cut-in voltage of GGNMOS is regulated.
During the manufacturing, the size of pick-up area 7, GGNMOS and silicon through hole 9 can be adjusted under spiritual principles of the present invention as required.In the present embodiment, the size of pick-up area 7, GGNMOS and silicon through hole 9 can adopt following parameter: the length of pick-up area 7 and widely can be set to 20～500um, the length and width size of GGNMOS (being the length and width of source-drain area 5) can be set to respectively 6～250um, and the distance between the diameter of silicon through hole 9 and the silicon through hole 9 can be set to 2～20um according to the design needs.More preferably, the size of pick-up area 7, GGNMOS and silicon through hole 9 can adopt following parameter: the length of pick-up area 7 and widely can be set to 30um, the length and width size of GGNMOS can be set to respectively 10～15um, and the distance between the diameter of silicon through hole 9 and the silicon through hole 9 can be set to 2～15um according to the design needs.
The said integrated circuit static release protection circuit in use, metal wire 6 is connected with protected circuit in the integrated circuit, substrate is by pick-up area 7 ground connection, source electrode 4b is by contact plug 8 ground connection on it, grid 3b ground connection.When ESD produces; the ESD electric current is delivered to drain electrode 2b by metal wire 6, the upper contact plug 8 that arranges of drain electrode 2b; and by contact plug 8 derivation on substrate, pick-up area 7, grid 3b and the source electrode 4b, thereby realization is to the esd protection of the protected circuit in the integrated circuit.Because the length and width size of the GGNMOS in the said integrated circuit static release protection circuit (being the length and width size of source-drain area 5) design is less; so when ESD occurs; can so that the Zone Full of whole GGNMOS is opened fully, improve the utilance of GGNMOS.The heat that the ESD electric current causes GGNMOS to produce dissipates rapidly by silicon through hole 9, thereby avoids heat to the damage of GGNMOS device, has prolonged the useful life of esd protection circuit.
The manufacture process of the integrated circuit electrostatic discharge protection circuit structure of above-described embodiment is included in the step of preparation GGNMOS on the substrate, and prepares the step of silicon through hole in the same substrate around the GGNMOS.In general, adopt that to prepare first behind the GGNMOS mode of preparation silicon through hole comparatively easy, prepare first that the mode of preparation GGNMOS also is fine behind the silicon through hole but as required it is adjusted into.In general the preparation of pick-up area is to carry out simultaneously with the preparation of GGNMOS, but also can be prepared pick-up area separately.
Adopted the main devices of GGNMOS as esd protection circuit in above-described embodiment; substitute as a kind of; also can adopt other GGMOS (Gate Grounded Metal-Oxide-Semiconductor; the grounded-grid metal-oxide semiconductor (MOS)) such as GGPMOS (Gate Grounded P-Metal-Oxide-Semiconductor; the grounded-grid P-type mos) as the main devices of esd protection circuit; when adopting other GGMOS as the main devices of esd protection circuit; inevitably need to change a little circuit, but its Integral Thought; the preparation process of principle and integral body is identical as the main devices of esd protection circuit with employing GGNMOS.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (11)
1. integrated circuit static release protection circuit is characterized in that: comprise GGMOS and at least 1 silicon through hole of sharing same substrate, described silicon through hole is arranged in the GGMOS substrate on every side.
2. integrated circuit static release protection circuit according to claim 1 is characterized in that: also comprise the pick-up area that is arranged on the described substrate and centers on described GGMOS and silicon through hole.
3. integrated circuit static release protection circuit according to claim 2, it is characterized in that: the length of described GGMOS is not more than 2/3 of described pick-up area length, and the width of described GGMOS is not more than 2/3 of described pick-up area width.
4. integrated circuit static release protection circuit according to claim 3, it is characterized in that: the length of described GGMOS is 1/3～1/2 of described pick-up area length, the width of described GGMOS is 1/3～1/2 of described pick-up area width.
5. integrated circuit static release protection circuit according to claim 1, it is characterized in that: the thermal conductivity of the material in the described silicon through hole is greater than the thermal conductivity of silicon.
6. integrated circuit static release protection circuit according to claim 5, it is characterized in that: the material in the described silicon through hole is Cu or W.
7. according to claim 1 to 6 each described integrated circuit static release protection circuits, it is characterized in that: described GGMOS is GGNMOS or GGPMOS.
8. integrated circuit static release protection circuit according to claim 7, it is characterized in that: described GGNMOS is many finger-like GGNMOS.
9. integrated circuit static release protection circuit according to claim 8; it is characterized in that: described many finger-like GGNMOS comprises described substrate, is provided with source-drain area at described substrate, in described source-drain area; be interval with drain electrode and source electrode, many finger-like grid is arranged between drain electrode and the source electrode.
10. integrated circuit static release protection circuit according to claim 9; it is characterized in that: be respectively equipped with the contact plug of conducting for static in described drain electrode and source electrode, connect for the metal wire that is connected with the protected circuit of integrated circuit in the contact plug that drains.
11. the manufacture method of an integrated circuit static release protection circuit is included in the step of preparation GGMOS on the substrate, and prepares the step of silicon through hole in the same substrate around the GGMOS.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102609006A CN102983130A (en) | 2011-09-05 | 2011-09-05 | An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof |
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| CN2011102609006A CN102983130A (en) | 2011-09-05 | 2011-09-05 | An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108630677A (en) * | 2017-03-17 | 2018-10-09 | 智瑞佳（苏州）半导体科技有限公司 | A kind of power device domain structure and production method |
| CN110071104A (en) * | 2019-04-15 | 2019-07-30 | 长江存储科技有限责任公司 | A kind of ESD-protection structure and preparation method thereof |
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Application publication date: 20130320 |