CN102970081B - Method and system for judging downlink pilot time slot of time division-synchronous code division multiple access (TD-SCDMA) repeater - Google Patents
Method and system for judging downlink pilot time slot of time division-synchronous code division multiple access (TD-SCDMA) repeater Download PDFInfo
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- CN102970081B CN102970081B CN201210248387.3A CN201210248387A CN102970081B CN 102970081 B CN102970081 B CN 102970081B CN 201210248387 A CN201210248387 A CN 201210248387A CN 102970081 B CN102970081 B CN 102970081B
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Abstract
The invention discloses a method and a system for judging a downlink pilot time slot of a TD-SCDMA repeater. The method comprises the steps of conducting m-point sampling on a current TD downlink detection signal, wherein m>=3, and the sampling interval is smaller than 50 mu s; comparing m-point sampling values with a reference level and obtaining corresponding comparison results; comparing comparison results with digital features of a downlink pilot and adjacent portions of the downlink pilot; if comparison results conform to digital features of the downlink pilot and adjacent portions of the downlink pilot, determining that the position of an m-point sampling sequence is an initial position of the downlink pilot; in an interval of the latest sampling point time delay 4875-4925 mu s, starting comparison between the TD downlink detection signal and a reference level signal; and detecting output after starting of the comparison between the TD downlink detection signal and the reference level signal, and judging that this moment is the falling edge of the downlink pilot when the output is the low level. The method and the system are reliable, accurate and easy to implement.
Description
Technical field
The present invention relates to communication technical field, be specifically related to the TD-SCDMA repeater synchronous switching control of the first time slot switching point and method.
Background technology
TD-SCDMA 3-G (Generation Three mobile communication system) (being called for short TD system) is through nervous construction, for vast mobile communication subscriber provides more fast and the network service of high-quality.The second generation communication system of knowing with respect to everybody, TD system provides numerous attracting network characteristics, comprises the technology such as dynamic channel configuration, joint-detection, synchronous, smart antenna.The introduction of these new technologies has brought the change of some technology and higher requirement, and the complexity of system equipment design has also increased greatly.
For repeater and the dry equipment of putting, be different from traditional 2G equipment, can TD equipment duplex mode can not rely on duplexer to realize simply, stablize the design difficulty that accurate realization and base station synchronization become equipment.What TD system adopted is TDD(time division duplex), the switching point of this system has two, and wherein first is for what fix, and second can be slided, and second time slot switching point can change according to the difference of traffic carrying capacity; More than the equal specific energy of emission peak of TD system reaches 10dB.The energy envelope of TD signal is more mixed and disorderly, can not directly by energy changing, control the switch of power amplifier, if done like this, in the time slot inside of TD system, just there will be a large amount of misoperations that has to cause distorted signals.
We know that the frame length of TD system is 10ms; two identical wireless sub-frames of structure, consist of, each wireless sub-frame includes three special time slots: i.e. descending pilot frequency time slot (DwPTS), descending pilot frequency time slot (DwPTS) and the protection interval time slot (GP) between them.5ms subframe structure is as follows:
TS0-DwPTS-GP1-UpPTS-TS1-TS2-TS3-TS4-TS5-TS6
The solution of controlling for TD system duplex at present mainly contains following three ways.
(1) GPS is synchronous, adopts the method for synchronization consistent with TD base station, according to the etalon time of GPS, carries out business demarcation, although this kind of mode is feasible, but during on-the-spot use, need to carry out source signal and measure to the time delay of equipment, by arranging to offset base station to the transmission delay of equipment.
(2) baseband decoding is synchronous, and descending pilot frequency time slot signal is carried out to related operation, and when there is relevant peak, representative is synchronous.
(3) detection synchronizing, claims again Window search synchronous, by the envelop forms of detection analytic signal, synchronously exports after searching characteristic window.
Wherein, the third mode is more often used, and is mainly that opening timing controls to realize switching by the catching of descending pilot frequency time slot (DwPTS).Yet catching of descending pilot frequency time slot (DwPTS) is the key point that those skilled in the art mainly study and need to break through always, prior art has proposed multiple catching or determination methods, but still needs to be further improved and improve.
Summary of the invention
The object of the invention is the repeater for TD-SCDMA, provide a kind of more reliably, more accurate, and descending pilot frequency time slot determination methods and system easy to implement.
To achieve these goals, the present invention is realized by following technical scheme:
A TD-SCDMA repeater descending pilot frequency time slot determination methods, is characterized in that, comprising:
(1) provide the descending rectified signal of TD and a reference level signal;
(2) the descending rectified signal of current TD is carried out to m point sampling, m >=3, the sampling interval is less than 50us;
(3) by m point sampling value and described reference level relatively and obtain corresponding comparative result;
(4) by comparative result and descending pilot frequency and the comparison of the due digitlization characteristic of adjacent part thereof;
(5) if comparative result conforms to descending pilot frequency and the due digitlization characteristic of adjacent part thereof, determine the preliminary position that this residing position of m point sampling sequence is descending pilot frequency, enter step (6); If do not conformed to, return to step (2);
(6), in the interval of the sampled point time delay 4875 ~ 4925us based on up-to-date, open the comparison to the descending rectified signal of TD and a reference level signal;
(7) detect to open the descending rectified signal of TD and a reference level signal relatively after output, while being output as low level, judge to be the trailing edge of descending pilot frequency this moment.
As concrete technical scheme, described m=10, the described sampling interval is 15.67us, described unlatching is 4909.5us to the time delay of the comparison of the descending rectified signal of TD and a reference level signal.
As concrete technical scheme, if a described m=10 sampled value and described reference level comparison, the comparative result of its first three sampled point be full the comparative result of low level, middle three sampled points entirely for the comparative result of high level, rear four sampled points is low level entirely, determine the preliminary position that this residing position of 10 point sampling sequence is descending pilot frequency.
As further technical scheme, described step (5) is substituted by following scheme: if comparative result conforms to descending pilot frequency and the due digitlization characteristic of adjacent part thereof, the identical sampling location to ensuing at least one subframe, repeating step (2) is to (4), if still conformed to, determine the preliminary position that the residing position of current m point sampling sequence is descending pilot frequency, enter step (6); If do not conformed to, return to step (2).
A system based on above-mentioned TD-SCDMA repeater descending pilot frequency time slot determination methods, is characterized in that, comprising:
Reference level signal input module, is used to analog comparator and logic comparator that default reference level signal is provided;
The descending rectified signal input module of TD, provides the descending rectified signal of TD to analog comparator and ADC sampling module;
ADC sampling module, samples to the descending rectified signal of TD, and sampled signal is offered to logic comparator;
Logic comparator, to the sampled signal of input and described default reference level signal are compared, output comparative result is to feature time slot judge module;
Feature time slot judge module, receives described comparative result, finds the corresponding sampled point sequence with descending pilot frequency characteristic, and start timing according to timer described in the residing location triggered of this sampled point sequence according to comparative result;
Timer, opens described analog comparator and interrupt output thereof while completing for timing;
Analog comparator, compares the descending rectified signal of TD and the reference level signal of input, output simulation interruption signal;
Descending pilot frequency trailing edge trapping module, detects the simulation interruption signal that analog comparator is exported.
Beneficial effect of the present invention is: to the catching more reliably of the descending pilot frequency time slot of the descending rectified signal of TD (DwPTS), more accurate, and easy to implement.
Accompanying drawing explanation
The TD-SCDMA repeater descending pilot frequency time slot that Fig. 1 provides for most preferred embodiment judges the formation block diagram of system.
The flow chart of the TD-SCDMA repeater descending pilot frequency time slot determination methods that Fig. 2 provides for most preferred embodiment.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is described in further detail.
As shown in Figure 1, the TD-SCDMA repeater descending pilot frequency time slot judgement system that the present embodiment provides comprises: reference level signal input module, the descending rectified signal input module of TD, ADC sampling module, logic comparator, feature time slot judge module, timer, analog comparator and descending pilot frequency trailing edge trapping module.
Wherein, reference level signal input module is used to analog comparator and logic comparator that default reference level signal is provided; The descending rectified signal input module of TD is used for providing the descending rectified signal of TD to analog comparator and ADC sampling module; ADC sampling module is used for the descending rectified signal of TD to sample, and sampled signal is offered to logic comparator; Logic comparator, for to the sampled signal of input and described default reference level signal are compared, is exported comparative result to feature time slot judge module; Feature time slot judge module is used for receiving described comparative result, finds the corresponding sampled point sequence with descending pilot frequency characteristic, and start timing according to timer described in the residing location triggered of this sampled point sequence according to comparative result; When completing for timing, opens by timer described analog comparator and interrupt output thereof; Analog comparator, for the descending rectified signal of TD and the reference level signal of input are compared, is exported simulation interruption signal; Descending pilot frequency trailing edge trapping module is for detection of the simulation interruption signal of analog comparator output.
The method that the present embodiment provides is in conjunction with shown in Fig. 2, first, consider that the descending pilot frequency width in the descending rectified signal of TD is 50us, so the sample frequency to TD signal the best of input is chosen to be: carry out ADC (10us) sampling at a high speed every 15.67us, after every sampling 10 times, the reference level signal value of sampled value value and setting is compared, higher than reference value, be judged to be low level, higher than reference value, be judged to be high level and process.When 10 sampled values and described reference level comparison, the comparative result of its first, second, third sampled point is low level entirely, four, the comparative result of the 5th, the 6th sampled point is high level entirely, and the comparative result of the 7th to the tenth sampled point is low level entirely, determine that this residing position of 10 point sampling sequence may be the preliminary position of descending pilot frequency.
In order further determining, and then to judge next two identical sampling locations of subframe (the delay 4837us shown in Fig. 2 is the identical sampling location of finding next subframe), to sample respectively 10 times, determination methods same as above.If the comparative result of three times is identical, the sampling location of really assert these 10 points is exactly the position that DwPTS tentatively catches.
Next, the position of catching based on DwPTS acquisition success postpones 4909.5us, guarantee to open analog comparator and interruption thereof between guaranteeing to drop between the rising edge of next subframe descending pilot frequency and trailing edge, generally can be chosen to be in the interval of 4875 ~ 4925us of the sampled point time delay based on up-to-date.
After analog comparator is opened, just detect its output after relatively to the descending rectified signal of TD and a reference level signal, while being output as low level, judge to be the trailing edge of descending pilot frequency this moment.
Claims (5)
1. a TD-SCDMA repeater descending pilot frequency time slot determination methods, is characterized in that, comprising:
(1) provide the descending rectified signal of TD and a reference level signal;
(2) the descending rectified signal of current TD is carried out to m point sampling, m >=3, the sampling interval is less than 50us;
(3) by m point sampling value and described reference level relatively and obtain corresponding comparative result;
(4) by comparative result and descending pilot frequency and the comparison of the due digitlization characteristic of adjacent part thereof;
(5) if comparative result conforms to descending pilot frequency and the due digitlization characteristic of adjacent part thereof, determine the preliminary position that this residing position of m point sampling sequence is descending pilot frequency, enter step (6); If do not conformed to, return to step (2);
(6), in the interval of the sampled point time delay 4875～4925us based on up-to-date, open the comparison to the descending rectified signal of TD and a reference level signal;
(7) detect to open the descending rectified signal of TD and a reference level signal relatively after output, while being output as low level, judge to be the trailing edge of descending pilot frequency this moment.
2. TD-SCDMA according to claim 1 repeater descending pilot frequency time slot determination methods, it is characterized in that, described m=10, the described sampling interval is 15.67us, described unlatching is 4909.5us to the time delay of the comparison of the descending rectified signal of TD and a reference level signal.
3. TD-SCDMA according to claim 2 repeater descending pilot frequency time slot determination methods, it is characterized in that, if a described m=10 sampled value and described reference level comparison, the comparative result of its first three sampled point be full the comparative result of low level, middle three sampled points entirely for the comparative result of high level, rear four sampled points is low level entirely, determine the preliminary position that this residing position of 10 point sampling sequence is descending pilot frequency.
4. according to the TD-SCDMA repeater descending pilot frequency time slot determination methods described in claims 1 to 3 any one, it is characterized in that, described step (5) is substituted by following scheme: if comparative result conforms to descending pilot frequency and the due digitlization characteristic of adjacent part thereof, the identical sampling location to ensuing at least one subframe, repeating step (2) is to (4), if still conformed to, determine the preliminary position that the residing position of current m point sampling sequence is descending pilot frequency, enter step (6); If do not conformed to, return to step (2).
5. the system based on TD-SCDMA claimed in claim 1 repeater descending pilot frequency time slot determination methods, is characterized in that, comprising:
Reference level signal input module, is used to analog comparator and logic comparator that default reference level signal is provided;
The descending rectified signal input module of TD, provides the descending rectified signal of TD to analog comparator and ADC sampling module;
ADC sampling module, samples to the descending rectified signal of TD, and sampled signal is offered to logic comparator;
Logic comparator, to the sampled signal of input and described default reference level signal are compared, output comparative result is to feature time slot judge module;
Feature time slot judge module, receives described comparative result, finds and the corresponding sampled point sequence of descending pilot frequency characteristic, and start timing according to the residing location triggered timer of this sampled point sequence according to comparative result;
Timer, opens described analog comparator and interrupt output thereof while completing for timing;
Analog comparator, compares the descending rectified signal of TD and the reference level signal of input, output simulation interruption signal;
Descending pilot frequency trailing edge trapping module, detects the simulation interruption signal that analog comparator is exported.
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| CN201210248387.3A CN102970081B (en) | 2012-07-17 | 2012-07-17 | Method and system for judging downlink pilot time slot of time division-synchronous code division multiple access (TD-SCDMA) repeater |
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| CN201210248387.3A CN102970081B (en) | 2012-07-17 | 2012-07-17 | Method and system for judging downlink pilot time slot of time division-synchronous code division multiple access (TD-SCDMA) repeater |
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| CN104619003B (en) * | 2013-11-04 | 2018-10-16 | 上海中兴易联通讯股份有限公司 | A kind of method and processing equipment that TDD-LTE is synchronized |
| CN107172638A (en) * | 2017-05-31 | 2017-09-15 | 福建三元达科技有限公司 | The acquisition methods and its system of TDD LTE up-downgoing switching time points |
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| CN1885744A (en) * | 2006-07-11 | 2006-12-27 | 京信通信技术(广州)有限公司 | Synchronization method for adapting FPGA realization in mobile communication system |
| CN101212246A (en) * | 2006-12-31 | 2008-07-02 | 深圳Tcl工业研究院有限公司 | Method for capturing downlink pilot time slot |
| CN101252370A (en) * | 2007-06-15 | 2008-08-27 | 浙江华立通信集团有限公司 | TD-SCDMA pilot capturing apparatus and method |
| WO2009155864A1 (en) * | 2008-06-24 | 2009-12-30 | 中兴通讯股份有限公司 | Method and device for downlink synchronization tracking |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885744A (en) * | 2006-07-11 | 2006-12-27 | 京信通信技术(广州)有限公司 | Synchronization method for adapting FPGA realization in mobile communication system |
| CN101212246A (en) * | 2006-12-31 | 2008-07-02 | 深圳Tcl工业研究院有限公司 | Method for capturing downlink pilot time slot |
| CN101252370A (en) * | 2007-06-15 | 2008-08-27 | 浙江华立通信集团有限公司 | TD-SCDMA pilot capturing apparatus and method |
| WO2009155864A1 (en) * | 2008-06-24 | 2009-12-30 | 中兴通讯股份有限公司 | Method and device for downlink synchronization tracking |
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