CN102970031A - Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable - Google Patents

Abstract

The invention discloses a phase-locked loop frequency synthesizer which comprises a phase detection discriminator, a charge pump, a low-pass loop filter, a voltage controlled oscillator, a frequency divider, an automatic frequency controller and a decoder. The input end of the decoder is connected with the frequency divider, and the output end of the decoder is connected with the charge pump to produce control signals according to frequency dividing ratio of the frequency divider to control current of the charge pump to enable a current value of the charge pump to be inversely contracted with the square of the frequency dividing ratio of the frequency divider. The invention further discloses a method for keeping bandwidth of the frequency synthesizer loop to be stable. By means of the phase-locked loop frequency synthesizer and the method for keeping the bandwidth of the frequency synthesizer loop to be stable, the phase-locked loop frequency synthesizer can be provided with the stable loop bandwidth.

Description

Phase-locked loop frequency integrator and the stable method of holding frequency synthesizer loop bandwidth

Technical field

The present invention relates to wireless communication field, be specifically related to a kind of phase-locked loop frequency integrator and the stable method of holding frequency synthesizer loop bandwidth.

Background technology

Typically based on the circuit diagram of the frequency synthesizer 100' of charge pump phase lock loop as shown in Figure 1, frequency synthesizer 100' comprises: phase detection discriminator (PFD) 102', charge pump (CP) 103', low-pass loop filter (LPF) 104', LC voltage controlled oscillator (VCO) 105', frequency divider 106' and automatic frequency controller 107'(AFC, Automatic frequency calibration).After frequency synthesizer 100' starts phase-locked loop operation, it is tuning that phase-locked loop is finished the precise frequency of LC voltage controlled oscillator 105', be phase detection discriminator 102' comparison reference signal frequencies omega ' frequency behind ref and the frequency divider 106' frequency division to be to be differed, charge pump 103' produces and differs corresponding discharging and recharging electric charge and convert control voltage to by low-pass loop filter 104', with increase or the reduction of control voltage controlled oscillator 105' output frequency, progressively to reduce reference signal ω ' _RefWith the frequency difference of feedback signal, until locking.

The transfer function LG(S of this frequency synthesizer 100') be:

$\mathrm{LG}\left(S\right)=\frac{I_{\mathrm{<figure-callout\; id="2"\; label="CP"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">CP</figure-callout>}}}{2\mathrm{\&pi;}}\&CenterDot;\mathrm{LF}\left(S\right)\&CenterDot;\frac{K_{\mathrm{VCO}}}{S}\&CenterDot;\frac{1}{N}$ (formula 1)

Wherein, I _CPBeing charge pump current, LF(S) is the transfer function of loop filter 104', K _VCOBe the sensitivity of LC voltage controlled oscillator 105', N is the divider ratio of frequency divider 106'.

Under normal circumstances, frequency synthesizer 100' is operated under the overdamping state, and its closed loop-three dB bandwidth is:

${\mathrm{\&omega;}}_{-3\mathrm{dB}}\&ap;\frac{I_{\mathrm{<figure-callout\; id="2"\; label="CP"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">CP</figure-callout>}}}{2\mathrm{\&pi;}}\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&CenterDot;\frac{K_{\mathrm{VCO}}}{N}$ (formula 2)

Wherein, R2 is the resistance value among the loop filter 104'.

The loop bandwidth of frequency synthesizer 100' has material impact to its performance, and loop bandwidth is too little can to cause phase lock loop lock on time long, and simultaneously, in-band phase noise is bad, and loop bandwidth is too large and can worsen the outer phase place noise of band of phase-locked loop.The loop bandwidth of an optimization can compromise and consider the content of these several respects, but the loop bandwidth of optimizing can change along with the variation of technique, temperature.In order to address this problem, obtain constant bandwidth, document [1] (Ting Wu, P.K.Hanumolu, K.Mayaram and Un-Ku Moon, ' Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers ' IEEE J.Solid-State Circuits, 2009,44, (2), P427 – P435) following methods proposed.

Consider $K_{\mathrm{VCO}}=\frac{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">L</figure-callout>}}{2}\&CenterDot;{{\mathrm{\&omega;}}^3}_{\mathrm{OSC}}\&CenterDot;\left|\frac{{\&PartialD;C}_{\mathrm{VAR}}}{{\&PartialD;V}_{\mathrm{CTRL}}}\right|$ (formula 3)

Convert formula 2 to following form:

$\frac{{\mathrm{\&omega;}}_{-3\mathrm{dB}}}{{\mathrm{\&omega;}}_{\mathrm{ref}}}=\frac{{\mathrm{<figure-callout\; id="2"\; label="I\; CP"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{CP}}}{2\mathrm{\&pi;}}\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&CenterDot;\frac{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">L</figure-callout>}}{2}\&CenterDot;{{\mathrm{\&omega;}}^2}_{\mathrm{OSC}}\&CenterDot;\left|\frac{{\&PartialD;C}_{\mathrm{VAR}}}{{\&PartialD;V}_{\mathrm{CTRL}}}\right|$ ... ... ... .(formula 4)

In formula 3,4, L is the resonant inductance of the resonant cavity of LC voltage controlled oscillator 105', C _VARBe the varactor of resonant cavity, V _CTRLBe the control voltage of voltage controlled oscillator 105', ω _OscBe frequency of oscillation.Inductance L can not considered along with the variation of technique is less.The variation of R2, can by with I _CPHave a resistance and offset.Thereby, in order to obtain constant bandwidth, need:

And $I_{\mathrm{CP}}\&Proportional;\frac{1}{{{\mathrm{\&omega;}}^2}_{\mathrm{OSC}}}.$

Document [1] is by arranging the mode of many biasing varactors to voltage controlled oscillator 105', so that the variation equalization of varactor, thereby obtain

For so that the electric current I of charge pump _CPBe inversely proportional to frequency of oscillation ω _OscSquare, voltage controlled oscillator 105' coarse adjustment and fine tuning loop are set, this voltage controlled oscillator 105' also is referred to as analog regulation VCO (analog tuned VCO), obtains the height of voltage controlled oscillator 105' frequency by the control voltage of coarse tuning loop, thus so that I _CPWith frequency of oscillation ω _OscBe inversely proportional to.

Yet the shortcoming of said method is, when the required coverage of the frequency of voltage controlled oscillator 105' is wide, needs very large varactor, so just can worsen the phase noise of frequency synthesizer 100'.

Summary of the invention

For the problems referred to above, the object of the present invention is to provide a kind of phase-locked loop frequency integrator and the stable method of holding frequency synthesizer loop bandwidth, stable loop bandwidth can be provided when not worsening the frequency synthesizer phase noise.

For achieving the above object, the present invention adopts following technical scheme:

Phase-locked loop frequency integrator, comprise phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider and automatic frequency controller, an input of described phase detection discriminator termination reference signal, first output of another input termination frequency divider, the input of the described charge pump of output termination of phase detection discriminator, the electric charge delivery side of pump connects the input of described low-pass loop filter, the input of the described voltage controlled oscillator of output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is used for the output control signal, the value of switched capacitor array control word with the control voltage controlled oscillator, described phase-locked loop frequency integrator also comprises decoder, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, be used for producing control signal according to the frequency dividing ratio of frequency divider, electric current with the control charge pump, so that the current value of charge pump be inversely proportional to the frequency divider frequency dividing ratio square, namely be inversely proportional to the voltage controlled oscillator frequency of oscillation square.

The stable method of a kind of holding frequency synthesizer loop bandwidth, be used for phase-locked loop frequency integrator, described phase-locked loop frequency integrator comprises phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider, automatic frequency controller and decoder, an input of described phase detection discriminator termination reference signal, first output of another input termination frequency divider, the input of the described charge pump of output termination of phase detection discriminator, the electric charge delivery side of pump connects the input of described low-pass loop filter, the input of the described voltage controlled oscillator of output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is used for the output control signal, the value of switched capacitor array control word with the control voltage controlled oscillator, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, and the stable method of described holding frequency synthesizer loop bandwidth comprises step:

Produce control signal by described decoder according to the frequency dividing ratio of frequency divider, with the electric current of control charge pump so that the current value of charge pump be inversely proportional to the frequency divider frequency dividing ratio square, namely be inversely proportional to the voltage controlled oscillator frequency of oscillation square.

Beneficial effect of the present invention is:

By decoder is set, produce the electric current of control signal control charge pump according to the frequency dividing ratio of frequency divider, so that the current value of charge pump be inversely proportional to the frequency divider frequency dividing ratio square, thereby cooperate the use of many biasing voltage controlled oscillators, so that phase-locked loop frequency integrator can have stable loop bandwidth.

Description of drawings

Fig. 1 is typically based on the circuit diagram of the frequency synthesizer of charge pump phase lock loop;

Fig. 2 is the electrical block diagram of phase-locked loop frequency integrator of the present invention;

Fig. 3 is the circuit structure diagram of voltage controlled oscillator among Fig. 2;

Fig. 4 is the circuit structure diagram of the many biasing MOS varactors in the voltage controlled oscillator of Fig. 3;

Fig. 5 is the circuit connection diagram between voltage controlled oscillator, frequency divider, phase detection discriminator, decoder and the charge pump among Fig. 2;

Fig. 6 is the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is 2.44GHZ;

Fig. 7 is the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is 2.56GHZ;

Fig. 8 is the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is 2.80GHZ.

Embodiment

Below, by reference to the accompanying drawings and embodiment, the present invention is described further:

As shown in Figure 2, the electrical block diagram of phase-locked loop frequency integrator 100 of the present invention, structure and the prior art of phase-locked loop frequency integrator 100 are roughly the same, yet, described phase-locked loop frequency integrator 100 also comprises decoder 107, the input of described decoder 107 connects the 3rd output of frequency divider 106, output connects charge pump 103, be used for producing control signal according to the frequency dividing ratio of frequency divider 106, electric current with control charge pump 103, so that the current value of charge pump 103 be inversely proportional to frequency divider 106 frequency dividing ratios square, namely be inversely proportional to voltage controlled oscillator 105 frequencies of oscillation square.In the present embodiment, by controlling charge pump 103 electric currents along with frequency dividing ratio is come electric current is controlled with the direction of binary variation.Described voltage controlled oscillator 105 adopts many biasing MOS varactors, is many biasing voltage controlled oscillators.Described frequency divider 106 is integer frequency divider, carries out integral frequency divisioil, perhaps is comprised of integer frequency divider and decimal modulator, carries out integer and decimal mixing frequency division.In the present embodiment, comprise that take frequency divider 106 integer frequency divider 1061 and decimal modulator 1062 describe (as shown in Figure 5) as example

See also Fig. 3 and Fig. 4, described voltage controlled oscillator 105 comprises the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, inductance L and the MOS varactor 1051 of setovering more.The grid of M1 is as Section Point B, and drain electrode connects reference voltage V _DD, source electrode is as first node A, and the grid of M2 connects first node A, and drain electrode connects reference voltage V _DDSource electrode connects Section Point B, inductance L is connected between first node A and the Section Point B, the grid of M5 connects automatic frequency controller 107, source electrode is connected to Section Point B by C4, drain electrode is connected to first node A by C3, and the grid of M6 connects automatic frequency controller 107, and source electrode is connected to Section Point B by C6, drain electrode is connected to first node A by C5, many biasing MOS varactors 1051 are connected between first node A and the Section Point B, and the grid of M3 connects Section Point B, grounded drain, source electrode connects first node A, the grid of M4 connects first node A, grounded drain, and source electrode connects Section Point B.

Many biasing MOS varactors 1051 comprise the 7th capacitor C 7, the 8th capacitor C 8, the 9th capacitor C 9, the tenth capacitor C 10, the 11 capacitor C 11, the 12 capacitor C 12, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the one MOS varactor Mos Var1, the 2nd MOS varactor MosVar2, the 3rd MOS varactor Mos Var3, the 4th MOS varactor Mos Var4, the 5th MOS varactor Mos Var5 and the 6th MOS varactor Mos Var6, Mos Var1 one end is connected to first node A by C7, the other end is connected to Section Point B by Mos Var2 and C8, Mos Var3 one end is connected to first node A by C9, the other end is connected to Section Point B by Mos Var4 and C10, Mos Var5 one end is connected to first node A by C11, the other end is connected to Section Point B by Mos Var6 and C12, the first reference voltage terminal Vbias1 is connected between C7 and the Mos Var1 by the 3rd resistance R 3, be connected between C8 and the Mos Var2 by the 4th resistance R 4, the second reference voltage terminal Vbias2 is connected between C9 and the Mos Var3 by the 5th resistance R 5, be connected between C10 and the Mos Var4 by the 6th resistance R 6, the 3rd reference voltage terminal Vbias3 is connected between C11 and the Mos Var5 by the 7th resistance R 7, be connected between C12 and the Mos Var6 by the 8th resistance R 8, the control voltage end Vtune of voltage controlled oscillator 105 is connected between Mos Var1 and the Mos Var2, be connected between Mos Var3 and the Mos Var4, also be connected between Mos Var5 and the Mos Var6.

Wherein, reference voltage terminal Vbias1, Vbias2 and Vbias3 provide respectively the size of reference voltage not fix, and for the voltage controlled oscillator of different situations (different such as situations such as supply voltage, techniques), their value is different.Their definite need to set according to actual needs, makes each MOS varactor along with the try one's best purpose of linearisation emulation of the variation of voltage to reach.

See also Fig. 5, in the present embodiment, the input word of described integer frequency divider 1061 adopts 8 bits to represent, be Div＜7:0 〉, the input word of decimal frequency divider 1062 adopts 19 bits to represent, be inputword＜18:0 〉, described charge pump 103 is 8 charge pump, described decoder 107 is 8 decoder, input word is Dinput＜7:0 〉, low 5 high 5 as the decoder input word of integer frequency divider 1061 input words, i.e. Div＜4:0 〉=Dinput＜7:3 〉, high 3 low 3 as the decoder input word of decimal frequency divider, i.e. inputword＜18:16 〉=Dinput＜2:0 〉.

Charge pump 103 comprises current source i _Cp, current source 2i _Cp, current source 4i _Cp, current source 8i _Cp, current source 16i _Cp, current source 32i _Cp, current source 64i _Cp, current source 128i _Cp, the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8, current source i _CpOne end ground connection, the other end is connected to node C by the first switch S 0, current source 2i _CpOne end ground connection, the other end is connected to node C by second switch S1, current source 4i _CpOne end ground connection, the other end is connected to node C by the 3rd switch S 2, current source 8i _CpOne end ground connection, the other end is connected to node C by the 4th switch S 3, current source 16i _CpOne end ground connection, the other end is connected to node C by the 5th switch S 4, current source 32i _CpOne end ground connection, the other end is connected to node C by the 6th switch S 5, current source 64i _CpOne end ground connection, the other end closes S6 by minion and is connected to node C, and the grid of M7 and drain electrode are connected to respectively node C, source ground, the grid of M8 is connected to node C, source ground, drain electrode is as the bias current output of charge pump 103.

The output of described decoder 107 is respectively applied to control conducting or the closure of the first switch S 0 to the 8th switch S7 in the charge pump 103 so that the current value of charge pump 103 be inversely proportional to the frequency divider frequency dividing ratio square.

In the present embodiment, concrete principle analysis is as follows, considers ω _-3dB=N ω _Ref, wherein, N is frequency dividing ratio corresponding to frequency divider, has according to corresponding formula 4 of the prior art:

${\mathrm{\&omega;}}_{-3\mathrm{dB}}=\frac{I_{\mathrm{<figure-callout\; id="2"\; label="CP"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">CP</figure-callout>}}}{2\mathrm{\&pi;}}\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&CenterDot;\frac{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">L</figure-callout>}}{2}\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">N</figure-callout>}}^2\&CenterDot;{{\mathrm{\&omega;}}^3}_{\mathrm{ref}}\&CenterDot;\left|\frac{{\&PartialD;C}_{\mathrm{VAR}}}{{\&PartialD;C}_{\mathrm{CTRL}}}\right|$ ... ... ... .(formula 5)

Wherein, inductance L can not considered along with the variation of technique is less in the LC voltage controlled oscillator 105.In the low-pass loop filter 104 variation of R2 can by with I _CPHave a resistance and disappear mutually and obtain.ω _RefBe reference frequency, in communication system, normally fixing, as in GPS, using the reference frequency of 16.386MHz, in LTE, can use the reference frequency of 30.72MHz, in GSM, can use the reference frequency of 26MHz.Voltage controlled oscillator 105 adopts the mode of many biasing varactors, then In order to obtain constant bandwidth, then need $I_{\mathrm{CP}}\&Proportional;\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">N</figure-callout>}}^2},$ Namely need $(I_{\mathrm{<figure-callout\; id="0"\; label="cp"\; filenames="HDA00002358763500051.png"\; state="\{\{state\}\}">cp</figure-callout>}0}+{\mathrm{\&Sigma;}}_{n=0}^M{2}^n\&CenterDot;i_{\mathrm{cp}})\&Proportional;\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="HDA00002358763500051.png,HDA00002358763500061.png"\; state="\{\{state\}\}">N</figure-callout>}}^2},$ Wherein, I _CPoBe the initial current of charge pump 103, i _CPUnit variable current for charge pump 103.And by determining I _CPo, i _CPWith the value of M to satisfy

Rear phase-locked loop frequency integrator of the present invention 100 can have constant bandwidth.

To I _CPo, i _CPAs follows with definite method of the value of M:

At reference frequency ω _Ref,

After R2 and L value were determined, frequency dividing ratio N was set to maximum, and at this moment, M=0 can get I _CPoFrequency dividing ratio N is set to minimum value, and the maximum current that can get charge pump is counted Imax.Determine that as for the M value depend on that negative three dB bandwidth changes the compromise between (this road variation is inadequate the causing of precision owing to M) and the M, wherein, the M value is larger, bandwidth changes less.After M determines, just can get: i _Cp=(I _Max-I _Cp0)/2 ^M

The circuit connecting relation of phase-locked loop frequency integrator 100 can satisfy the operating frequency of voltage controlled oscillator at 2.43 ~ 2.80GHz, reference frequency ω among Fig. 5 _RefInitial current I for 30.72MHz, charge pump _CPoBe 410uA, the variable current i of unit _CPWorking condition for 1uA.

By above analysis as seen, the parameters such as annexation of the figure place of the figure place of the input word figure place of frequency divider, charge pump, decoder and frequency divider input word pin and decoder all need to set flexibly according to actual needs among the present invention, all can as long as annexation finally can satisfy the realization principle of above-mentioned length narration.

Following table is phase-locked loop frequency integrator 100 frequency dividing ratios, output frequency, charge pump current and the deviation comparison diagram among Fig. 5, and what this deviation represented is because the precision of charge pump is limited, the difference contrast of loop theoretical bandwidth and actual bandwidth.Can find out that in frequency 2.43 ~ 2.9GHz, deviation is less than 2.8%.

Frequency dividing ratio	Output frequency (MHz)	Electric current (uA)	Deviation (%)
				79	2426.88	410	-2.29
79.125	2430.72	409	-2.22
				79.25	2434.56	408	-2.15
79.375	2438.4	407	-2.09
				79.5	2442.24	406	-2.02
79.625	2446.08	405	-1.95
				79.75	2449.92	404	-1.89
79.875	2453.76	403	-1.82
				80	2457.6	402	-1.76
80.125	2461.44	401	-1.70
				80.25	2465.28	400	-1.64

80.375	2469.12	399	-1.58
				80.5	2472.96	398	-1.52
80.625	2476.8	397	-1.46
				80.75	2480.64	396	-1.40
80.875	2484.48	395	-1.35
				81	2488.32	394	-1.29
81.125	2492.16	393	-1.24
				81.25	2496	392	-1.19
81.375	2499.84	391	-1.14
				81.5	2503.68	390	-1.09
81.625	2507.52	389	-1.04
				81.75	2511.36	388	-0.99
81.875	2515.2	387	-0.94
				82	2519.04	386	-0.89
82.125	2522.88	385	-0.85
				82.25	2526.72	384	-0.81
82.375	2530.56	383	-0.76
				82.5	2534.4	382	-0.72
82.625	2538.24	381	-0.68
				82.75	2542.08	380	-0.64
82.875	2545.92	379	-0.60
				83	2549.76	378	-0.57
83.125	2553.6	377	-0.53
				83.25	2557.44	376	-0.50
83.375	2561.28	375	-0.46
				83.5	2565.12	374	-0.43
83.625	2568.96	373	-0.40
				83.75	2572.8	372	-0.37
83.875	2576.64	371	-0.34
				84	2580.48	370	-0.31
84.125	2584.32	369	-0.29
				84.25	2588.16	368	-0.26
84.375	2592	367	-0.24
				84.5	2595.84	366	-0.21
84.625	2599.68	365	-0.19
				84.75	2603.52	364	-0.17
84.875	2607.36	363	-0.15
				85	2611.2	362	-0.13
85.125	2615.04	361	-0.11
				85.25	2618.88	360	-0.10
85.375	2622.72	359	-0.08
				85.5	2626.56	358	-0.07
85.625	2630.4	357	-0.06

85.75	2634.24	356	-0.05
				85.875	2638.08	355	-0.04
86	2641.92	354	-0.03
				86.125	2645.76	353	-0.02
86.25	2649.6	352	-0.01
				86.375	2653.44	351	-0.01
86.5	2657.28	350	0.00
				86.625	2661.12	349	0.00
86.75	2664.96	348	0.00
				86.875	2668.8	347	0.00
87	2672.64	346	0.00
				87.125	2676.48	345	0.00
87.25	2680.32	344	-0.01
				87.375	2684.16	343	-0.01
87.5	2688	342	-0.02
				87.625	2691.84	341	-0.03
87.75	2695.68	340	-0.03
				87.875	2699.52	339	-0.04
88	2703.36	338	-0.05
				88.125	2707.2	337	-0.07
88.25	2711.04	336	-0.08
				88.375	2714.88	335	-0.10
88.5	2718.72	334	-0.11
				88.625	2722.56	333	-0.13
88.75	2726.4	332	-0.15
				88.875	2730.24	331	-0.17
89	2734.08	330	-0.19
				89.125	2737.92	329	-0.21
89.25	2741.76	328	-0.24
				89.375	2745.6	327	-0.26
89.5	2749.44	326	-0.29
				89.625	2753.28	325	-0.32
89.75	2757.12	324	-0.35
				89.875	2760.96	323	-0.38
90	2764.8	322	-0.41
				90.125	2768.64	321	-0.44
90.25	2772.48	320	-0.48
				90.375	2776.32	319	-0.51
90.5	2780.16	318	-0.55
				90.625	2784	317	-0.59
90.75	2787.84	316	-0.63
				90.875	2791.68	315	-0.67
91	2795.52	314	-0.71

91.125	2799.36	313	-0.76
				91.25	2803.2	312	-0.80
91.375	2807.04	311	-0.85
				91.5	2810.88	310	-0.90
91.625	2814.72	309	-0.95
				91.75	2818.56	308	-1.00
91.875	2822.4	307	-1.05
				92	2826.24	306	-1.10
92.125	2830.08	305	-1.16
				92.25	2833.92	304	-1.22
92.375	2837.76	303	-1.27
				92.5	2841.6	302	-1.33
92.625	2845.44	301	-1.39
				92.75	2849.28	300	-1.46
92.875	2853.12	299	-1.52
				93	2856.96	298	-1.58
93.125	2860.8	297	-1.65
				93.25	2864.64	296	-1.72
93.375	2868.48	295	-1.79
				93.5	2872.32	294	-1.86
93.625	2876.16	293	-1.93
				93.75	2880	292	-2.00
93.875	2883.84	291	-2.08
				94	2887.68	290	-2.16
94.125	2891.52	289	-2.23
				94.25	2895.36	288	-2.31
94.375	2899.2	287	-2.39
				94.5	2903.04	286	-2.48
94.625	2906.88	285	-2.56
				94.75	2910.72	284	-2.65
94.875	2914.56	283	-2.73

Fig. 6, Fig. 7 and Fig. 8 are the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is respectively 2.44GHz, 2.56GHz and 2.80GHz.From these 3 figure, can find out that in the said frequencies scope, loop bandwidth remains on 90KHz, substantially constant, thus meet the demands.

For a person skilled in the art, can make other various corresponding changes and distortion according to technical scheme described above and design, and these all changes and distortion should belong within the protection range of claim of the present invention all.

Claims (9)

1. phase-locked loop frequency integrator, comprise phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider and automatic frequency controller, an input of described phase detection discriminator termination reference signal, first output of another input termination frequency divider, the input of the described charge pump of output termination of phase detection discriminator, the electric charge delivery side of pump connects the input of described low-pass loop filter, the input of the described voltage controlled oscillator of output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is used for the output control signal, the value of switched capacitor array control word with the control voltage controlled oscillator, it is characterized in that, described phase-locked loop frequency integrator also comprises decoder, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, be used for producing control signal according to the frequency dividing ratio of frequency divider, electric current with the control charge pump, so that the current value of charge pump be inversely proportional to the frequency divider frequency dividing ratio square, namely be inversely proportional to the voltage controlled oscillator frequency of oscillation square.

2. phase-locked loop frequency integrator as claimed in claim 1 is characterized in that, described frequency divider is integer frequency divider, perhaps is comprised of integer frequency divider and decimal modulator.

3. phase-locked loop frequency integrator as claimed in claim 2 is characterized in that, described voltage controlled oscillator adopts many biasing MOS varactors, is many biasing voltage controlled oscillators.

4. phase-locked loop frequency integrator as claimed in claim 3, it is characterized in that, described frequency divider is comprised of integer frequency divider and decimal modulator, the input word of integer frequency divider adopts 8 bits to represent, the input word of decimal frequency divider adopts 19 bits to represent, described charge pump is 8 charge pump, described decoder is 8 decoder, low 5 high 5 as the decoder input word of integer frequency divider input word, high 3 as the decoder input word low 3 of decimal frequency divider.

5. phase-locked loop frequency integrator as claimed in claim 4 is characterized in that, charge pump comprises current source i _Cp, current source 2i _Cp, current source 4i _Cp, current source 8i _Cp, current source 16i _Cp, current source 32i _Cp, current source 64i _Cp, current source 128i _Cp, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, current source i _CpOne end ground connection, the other end is connected to node C by the first switch S 0, current source 2i _CpOne end ground connection, the other end is connected to node C by second switch S1, current source 4i _CpOne end ground connection, the other end is connected to node C by the 3rd switch S 2, current source 8i _CpOne end ground connection, the other end is connected to node C by the 4th switch S 3, current source 16i _CpOne end ground connection, the other end is connected to node C by the 5th switch S 4, current source 32i _CpOne end ground connection, the other end is connected to node C by the 6th switch S 5, current source 64i _CpOne end ground connection, the other end closes S6 by minion and is connected to node C, and the grid of the 7th metal-oxide-semiconductor and drain electrode are connected to respectively node C, source ground, the grid of the 8th metal-oxide-semiconductor is connected to node C, source ground, drain electrode is as the bias current output of charge pump.

6. phase-locked loop frequency integrator as claimed in claim 5, it is characterized in that, the output of described decoder is respectively applied to control conducting or the closure of the first switch S 0 to the 8th switch S7 in the charge pump so that the current value of charge pump be inversely proportional to the frequency divider frequency dividing ratio square.

7. such as claim 1 or 6 described phase-locked loop frequency integrators, it is characterized in that, described voltage controlled oscillator comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, inductance and the MOS varactor of setovering more, the grid of the first metal-oxide-semiconductor is as Section Point B, and drain electrode connects reference voltage V _DD, source electrode is as first node A, and the grid of the second metal-oxide-semiconductor connects first node A, and drain electrode connects reference voltage V _DDSource electrode connects Section Point B, inductance is connected between first node A and the Section Point B, the grid of the 5th metal-oxide-semiconductor connects automatic frequency controller, source electrode is connected to Section Point B by the 4th electric capacity, drain electrode is connected to first node A by the 3rd electric capacity, the grid of the 6th metal-oxide-semiconductor connects automatic frequency controller, source electrode is connected to Section Point B by the 6th electric capacity, drain electrode is connected to first node A by the 5th electric capacity, many biasing MOS varactors are connected between first node A and the Section Point B, and the grid of the 3rd metal-oxide-semiconductor connects Section Point B, grounded drain, source electrode connects first node A, the grid of the 4th metal-oxide-semiconductor connects first node A, grounded drain, and source electrode connects Section Point B.

8. phase-locked loop frequency integrator as claimed in claim 7, it is characterized in that, many biasing MOS varactors comprise the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity, the 12 electric capacity, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the one MOS varactor, the 2nd MOS varactor, the 3rd MOS varactor, the 4th MOS varactor, the 5th MOS varactor and the 6th MOS varactor, the one MOS varactor one end is connected to first node A by the 7th electric capacity, the other end is connected to Section Point B by the 2nd MOS varactor and the 8th electric capacity, the 3rd MOS varactor one end is connected to first node A by the 9th electric capacity, the other end is connected to Section Point B by the 4th MOS varactor and the tenth electric capacity, the 5th MOS varactor one end is connected to first node A by the 11 electric capacity, the other end is connected to Section Point B by the 6th MOS varactor and the 12 electric capacity, the first reference voltage terminal is connected between the 7th electric capacity and the MOS varactor by the 3rd resistance, be connected between the 8th electric capacity and the 2nd MOS varactor by the 4th resistance, the second reference voltage terminal is connected between the 9th electric capacity and the 3rd MOS varactor by the 5th resistance, be connected between the tenth electric capacity and the 4th MOS varactor by the 6th resistance, the 3rd reference voltage terminal is connected between the 11 electric capacity and the 5th MOS varactor by the 7th resistance, be connected between the 12 electric capacity and the 6th MOS varactor by the 8th resistance, the control voltage end of voltage controlled oscillator is connected between a MOS varactor and the 2nd MOS varactor, be connected between the 3rd MOS varactor and the 4th MOS varactor, also be connected between the 5th MOS varactor and the 6th MOS varactor.

9. stable method of holding frequency synthesizer loop bandwidth, be used for phase-locked loop frequency integrator, described phase-locked loop frequency integrator comprises phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider, automatic frequency controller and decoder, an input of described phase detection discriminator termination reference signal, first output of another input termination frequency divider, the input of the described charge pump of output termination of phase detection discriminator, the electric charge delivery side of pump connects the input of described low-pass loop filter, the input of the described voltage controlled oscillator of output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is used for the output control signal, the value of switched capacitor array control word with the control voltage controlled oscillator, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, it is characterized in that the stable method of described holding frequency synthesizer loop bandwidth comprises step:

Produce control signal by described decoder according to the frequency dividing ratio of frequency divider, with the electric current of control charge pump so that the current value of charge pump be inversely proportional to the frequency divider frequency dividing ratio square, namely be inversely proportional to the voltage controlled oscillator frequency of oscillation square.

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