CN102969247B - Semiconductor structure and forming method thereof, transistor and transistor forming method - Google Patents
Semiconductor structure and forming method thereof, transistor and transistor forming method Download PDFInfo
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- CN102969247B CN102969247B CN201110255740.6A CN201110255740A CN102969247B CN 102969247 B CN102969247 B CN 102969247B CN 201110255740 A CN201110255740 A CN 201110255740A CN 102969247 B CN102969247 B CN 102969247B
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Abstract
The invention provides a semiconductor structure forming method, a transistor and a transistor forming method. The transistor forming method comprises the steps of providing a semiconductor substrate, wherein a gate structure is formed on the surface of the semiconductor substrate, and a bottom material and a lateral wall material of first grooves located on two sides of the gate structure are in a crystalline state; converting the crystalline state of the bottom material of the first grooves into an amorphous state; performing wet etching on the first grooves to form second grooves after the bottom material of first grooves is converted into the amorphous state, the bottom material in the amorphous state being exposed by the second grooves; removing the bottom material in the amorphous state after the second grooves are formed, to form third grooves located at the bottoms of the second grooves; forming silicon-germanium layers inside the second grooves and the third grooves and doping the silicon-germanium layers to form source electrodes and drain electrodes. By means of the semiconductor structure forming method, the transistor and the transistor forming method, the improvement of performance of semiconductor devices is facilitated.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of semiconductor structure and forming method thereof, a kind of transistor and forming method thereof.
Background technology
In existing semiconductor device fabrication process, because stress can change energy gap and the carrier mobility of silicon materials, the performance therefore improving transistor by stress becomes more and more conventional means.Particularly, by suitable proof stress, can carrier mobility be improved, and then improve drive current, and greatly improve the performance of transistor with this.
At present, normal embedded germanium silicon (Embedded GeSi) technology that adopts introduces stress to improve the performance of transistor.A kind of method adopting embedded germanium silicon (Embedded GeSi) technology to improve the performance of transistor is disclosed in the United States Patent (USP) of patent No. US7569443B2, namely need the region forming source region and drain region first to form germanium silicon layer, and then carry out source region and drain region that doping forms P-type crystal pipe; Forming described germanium silicon layer is to introduce the compression that between silicon and germanium silicon (SiGe), lattice mismatch is formed, to improve the performance of P-type crystal pipe.
In order to make P-type crystal pipe realize higher performance, a kind of way is the distance reducing to be formed between the germanium-silicon layer of source and drain and raceway groove, specifically please refer to Fig. 1 and Fig. 2.
First with reference to figure 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surface is formed with grid structure, described grid structure comprises the grid be made up of the gate dielectric layer 110 and gate electrode layer 120 that are formed in Semiconductor substrate 100 surface successively, and be formed in the side wall 130 of described grid both sides, be also formed with the first groove 140 being positioned at grid structure both sides in described Semiconductor substrate 100.
With reference to figure 2, wet etching is carried out to described first groove and forms second groove with sigma shape, the sidewall of described second groove has towards the depression of raceway groove, then the germanium-silicon layer 150 of filling full described second groove is formed, but by the impact of described wet etching Selection radio, wedge angle is formed on the bottom of the second groove formed, thus is unfavorable in subsequent technique, form the germanium-silicon layer of filling full described second groove.
A kind of solution is, after formation first groove, ion implantation is carried out to the bottom of described first groove, the backing material of bottom portion of groove is made to change amorphous silicon into by crystalline silicon, in wet-etching technology, the amorphous silicon of the first bottom portion of groove and the crystalline silicon of sidewall have larger wet etching Selection radio, can form sidewall cave in raceway groove by wet-etching technology, the second groove of bottom flat; But amorphous silicon surface is unfavorable for forming germanium-silicon layer.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure and forming method thereof, and a kind of transistor and forming method thereof, the bottom of the groove formed after avoiding wet etching on the one hand has wedge angle; Be conducive on the other hand forming the germanium-silicon layer of filling and completely etching the groove formed.
For solving the problem, a kind of method for forming semiconductor structure of the present invention, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with the first groove, and the base material of described first groove and side-wall material are crystalline state;
Be amorphous state by the base material of described first groove by crystalline transformation;
After the base material of described first groove changes amorphous state into, carrying out wet etching, form the second groove to described first groove, is the base material of amorphous state described in described second groove exposes;
After forming described second groove, be the base material of amorphous state described in removing, form the 3rd groove being positioned at the second bottom portion of groove;
Form the packed layer of filling full described second groove and the 3rd groove.
Alternatively, the described Semiconductor substrate silicon substrate that to be high preferred orientation be (100).
Alternatively, be the base material of amorphous state described in the removal of employing reactive ion etching process, form the 3rd groove.
Alternatively, the parameter of described reactive ion etching process is: pressure is 5-50T, and bias voltage is 50-300V, and etching gas is He, HBr, O
2, etch period is 2-60 second, and wherein the flow of He is the flow of 200-600sccm, HBr is 200-600sccm, O
2flow be 2-20sccm.
Alternatively, ion implantation technology is adopted to be amorphous state by the material of described first bottom portion of groove by crystalline transformation.
Alternatively, the shape of described second groove is sigma shape.
The present invention also provides a kind of semiconductor structure, comprising: Semiconductor substrate, is formed and is formed from top to down along semiconductor substrate surface in described Semiconductor substrate, and the second groove communicated and the 3rd groove; Fill the packed layer of full described second groove and the 3rd groove; Wherein, the shape of described second groove is sigma shape, and the shape of the 3rd groove is rectangle.
The present invention also provides a kind of Transistor forming method, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with grid structure, and is positioned at the first groove of described grid structure semiconductor substrates on two sides, and the base material of described first groove and side-wall material are crystalline state;
Be amorphous state by the base material of described first groove by crystalline transformation;
After the base material of described first groove changes amorphous state into, carrying out wet etching, form the second groove to described first groove, is the base material of amorphous state described in described second groove exposes;
After forming described second groove, be the base material of amorphous state described in removing, form the 3rd groove being positioned at the second bottom portion of groove;
In described second groove and the 3rd groove, form germanium-silicon layer, and described germanium-silicon layer is adulterated, form source, drain electrode.
Alternatively, the described Semiconductor substrate silicon substrate that to be high preferred orientation be (100).
Alternatively, be the base material of amorphous state described in the removal of employing reactive ion etching process, form the 3rd groove.
Alternatively, the parameter of described reactive ion etching process is: pressure is 5-50T, and bias voltage is 50-300V, and etching gas is He, HBr, O
2, etch period is 2-60 second, and wherein the flow of He is the flow of 200-600sccm, HBr is 200-600sccm, O
2flow be 2-20sccm.
Alternatively, ion implantation technology is adopted to be amorphous state by the material of described first bottom portion of groove by crystalline transformation.
Alternatively, the ion that described ion implantation technology is injected is germanium, and the energy 3-10kev of injection, dosage is 1E14-5E15atom/cm
2.
Alternatively, the shape of described second groove is sigma shape, and the degree of depth is 300-600 dust; The shape of described 3rd groove is rectangle, and the degree of depth is 10-200 dust.
The present invention also provides the transistor formed by said method, comprising: Semiconductor substrate, and described semiconductor substrate surface is formed with grid structure, is formed with groove in described grid structure semiconductor substrates on two sides; Be positioned at the germanium-silicon layer of described groove, the source of described germanium-silicon layer transistor formed, drain electrode; Described groove comprises and being formed from top to down along semiconductor substrate surface, and the second groove communicated and the 3rd groove.
Alternatively, the shape of described second groove is sigma shape, and the degree of depth is 300-600 dust; The shape of described 3rd groove is rectangle, and the degree of depth is 10-200 dust.
Compared with prior art, the present invention has the following advantages: the base material of the first groove, after formation first groove, is amorphous state by crystalline transformation by technical scheme of the present invention; In wet-etching technology afterwards, because to being positioned at the etching speed of amorphous state material of the first bottom portion of groove much smaller than being the etching speed of crystalline material to what be positioned at the first recess sidewall, so the second groove that wet etching is formed has smooth bottom, be conducive in described first groove and the second groove, forming germanium-silicon layer in subsequent technique; Meanwhile, after formation second groove, the material being positioned at the amorphous state of the second bottom portion of groove is removed, expose the material for crystalline state, and the material surface of described crystalline state is smooth, so be conducive to follow-up formation germanium-silicon layer;
Further, technical scheme of the present invention adopts the technique of reactive ion etching to remove the material being positioned at the amorphous state of the second bottom portion of groove, by adjusting the parameter of reactive ion etching process, it is the amorphous state material of the second bottom portion of groove that described reactive ion etching process only can be removed, and can not have an impact to other structures of transistor.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the cross-sectional view of existing transistor forming process;
Fig. 3 is the schematic flow sheet of the Transistor forming method that embodiments of the invention provide;
Fig. 4 to Fig. 8 is the cross-sectional view of the transistor forming process that embodiments of the invention provide.
Embodiment
With reference to figure 1 and Fig. 2, from background technology, when adopting wet-etching technology formation to have the second groove of sigma shape, by the impact of etching selection ratio, the second bottom portion of groove formed has wedge angle, and described wedge angle is unfavorable in subsequent technique, form the germanium-silicon layer 150 of filling full described second groove; After formation first groove 140, first adopt ion implantation technology to make the backing material bottom the first groove 140 be amorphous silicon by crystalline silicon, the Selection radio of wet etching can be improved, be conducive to the second groove forming bottom flat.But amorphous silicon surface not easily forms germanium-silicon layer.
Inventor after further research, provides a kind of method for forming semiconductor structure in an embodiment of the present invention, and a kind of transistor and forming method thereof.
Method for forming semiconductor structure provided by the present invention comprises: provide Semiconductor substrate, and described semiconductor substrate surface is formed with the first groove, and the base material of described first groove and side-wall material are crystalline state;
Be amorphous state by the base material of described first groove by crystalline transformation;
After the base material of described first groove changes amorphous state into, carrying out wet etching, form the second groove to described first groove, is the base material of amorphous state described in described second groove exposes;
After forming described second groove, be the base material of amorphous state described in removing, form the 3rd groove being positioned at the second bottom portion of groove; Form the packed layer of filling full described second groove and the 3rd groove.
The present invention also provides a kind of semiconductor structure, comprising: Semiconductor substrate, is formed and is formed from top to down along semiconductor substrate surface in described Semiconductor substrate, and the second groove communicated and the 3rd groove; Fill the packed layer of full described second groove and the 3rd groove; Wherein, the shape of described second groove is sigma shape, and the shape of the 3rd groove is rectangle.
Semiconductor structure that embodiments of the invention provide and forming method thereof, may be used for the source, the drain electrode that form PMOS transistor, also may be used for forming other structures, such as isolation structure.
Fig. 3 is the schematic flow sheet of the Transistor forming method that embodiments of the invention provide, and comprising:
Step S101, provides Semiconductor substrate, and described semiconductor substrate surface is formed with grid structure, and is positioned at the first groove of described grid structure semiconductor substrates on two sides, and the base material of described first groove and side-wall material are crystalline state; The material of described first bottom portion of groove is amorphous state by crystalline transformation by step S102;
Step S103, the material transition of described first bottom portion of groove is after amorphous state, carries out wet etching, form the second groove to described first groove, is the base material of amorphous state described in described second groove exposes;
Step S104, after forming described second groove, is the base material of amorphous state described in removing, forms the 3rd groove being positioned at the second bottom portion of groove;
Step S105, forms germanium-silicon layer, and adulterates to described germanium-silicon layer in described second groove and the 3rd groove, forms source, drain electrode.
Correspondingly, the present invention also provides the transistor formed by said method.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with drawings and Examples.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Fig. 4 to Fig. 8 is the cross-sectional view of the transistor forming process that embodiments of the invention provide.
With reference to figure 4, provide Semiconductor substrate 200, described Semiconductor substrate 200 surface is formed with grid structure, and is positioned at the first groove 240 of described grid structure both sides, and the material exposed with sidewall bottom described first groove 240 is crystalline state.
In the present embodiment, described Semiconductor substrate 200 for high preferred orientation be the silicon substrate of (100), described grid structure comprises grid and side wall 230, and described grid structure comprises the gate dielectric layer 210 and gate electrode layer 220 that are formed in Semiconductor substrate 200 surface successively.The material of described gate dielectric layer 210 is silicon dioxide or high-g value, and the material of described gate electrode layer 220 is polysilicon or metal.
In the present embodiment, the first groove 240 is formed by the technique of reactive ion etching, because the high preferred orientation of Semiconductor substrate 200 is (100), so etch the high preferred orientation of the bottom of the first groove 240 formed for (100), the high preferred orientation of sidewall is (110).
With reference to figure 5, adopt ion implantation technology to change the silicon materials bottom described first groove 240 into amorphous silicon by crystalline silicon, form amorphous si-layer 260.
In the present embodiment, the ion that described ion implantation technology is injected is germanium, and the energy 3-10kev of injection, dosage is 1E14-5E15atom/cm
2the object of described ion implantation passes through the crystalline state of injected ion damaged silicon materials, change crystalline silicon into amorphous silicon, energy and/or the dosage of described ion implantation are excessive, the complexity of the technique of follow-up removal amorphous silicon may be increased, energy and/or the dosage of described ion implantation are too small, possibly cannot change crystalline silicon into amorphous silicon.In the present embodiment, the benefit injecting ion selection germanium is: 1, and the atomic molar ratio of germanium is comparatively large, and the inertia after injection is large, is conducive to changing crystalline silicon into amorphous silicon; 2, the follow-up material formed in groove is silicon germanium material, so when the ion injected has residual, injecting ion is that the impact of germanium on the device of follow-up formation is smaller.
In other embodiments of the invention, can need according to technique the parameter adjusting ion implantation technology, a demand fulfillment changes the crystalline silicon bottom the first groove 240 into amorphous silicon, and amorphous silicon can be removed in subsequent technique.
In the present embodiment, the thickness of the amorphous si-layer 260 formed is 10-200 dusts, if the thickness of amorphous si-layer 260 is excessive, can increase the difficulty that follow-up employing reactive ion etching process removes amorphous si-layer 260; Thickness is too small, can be not enough to the function providing etching barrier layer.
With reference to figure 6, after forming amorphous si-layer 260, carry out wet etching to described first groove 240, form second groove 250 with sigma shape, described second groove 250 exposes described amorphous si-layer 260.
In the present embodiment, adopt Tetramethylammonium hydroxide (TMAH, Tetramethylammonium Hydroxide) wet etching is carried out to described first groove 240, TMAH is different along the etching speed of the crystal face of different orientation, being that the crystal face etching speed of (100) is the fastest along high preferred orientation, is that the crystal face etching speed of (111) is the slowest along high preferred orientation.
When the material of the first bottom portion of groove is crystalline state, described wet-etching technology is the fastest along the direction etching speed of the first bottom portion of groove, direction etching speed along sidewall is slow, so the sidewall of the groove formed after etching has the wedge angle that the Semiconductor substrate 200 to groove both sides is protruded.Because the direction etching speed along sidewall is slow, the etching speed along bottom direction is fast, so the bottom of the groove formed easily produces wedge angle.
In the technical scheme that the present embodiment provides, material due to the first bottom portion of groove is amorphous silicon, so TMAH is the slowest along the etching speed of bottom, so the etch amount along the first bottom portion of groove can be ignored, form second groove 250 with sigma shape, described second groove 250 bottom flat.
The degree of depth of the second groove 250 formed is 300-600 dust, and the degree of depth of described second groove 250 is too small, after epitaxial growth SiGe, to the understrressing that raceway groove produces; The degree of depth is excessive, may more than the epitaxially grown critical thickness of SiGe, and stress also can decline.
With reference to figure 7, after forming described second groove 250, remove described formation amorphous si-layer, form the 3rd groove 270 be positioned at bottom the second groove 250.
In the present embodiment, adopt reactive ion etching process to remove described amorphous si-layer, form the 3rd groove 270.The parameter of described reactive ion etching process is: pressure is 5-50T, and bias voltage is 50-300V, and etching gas is He, HBr, O
2, etch period is 2-60 second, and wherein the flow of He is the flow of 200-600sccm, HBr is 200-600sccm, O
2flow be 2-20sccm.
In the present embodiment, by regulating etching gas and bias voltage, the anisotropic of adjustment reactive ion etching process, makes described reactive ion etching process to the etch rate of the etch rate of bottom portion of groove much larger than oppose side wall.
In the present embodiment, the shape of described 3rd groove is rectangle, and the degree of depth is 10-200 dust.The thickness of described 3rd groove equals the thickness of bottom portion of groove amorphous si-layer, or slightly larger than the thickness of bottom portion of groove amorphous si-layer.
In the present embodiment, the technique of reactive ion etching is adopted to remove the amorphous si-layer being positioned at the second bottom portion of groove, by adjusting the parameter of reactive ion etching process, described reactive ion etching process only can remove the amorphous si-layer being positioned at the second bottom portion of groove, and can not other structures of transistor be had an impact, in addition, described reactive ion etching process is Low temperature processing techniques, fire damage can not be produced to the device formed on a semiconductor substrate, also can not cause the diffusion of the Doped ions in substrate.
With reference to figure 8, in described second groove and the 3rd groove, form germanium-silicon layer 280, and described germanium-silicon layer 280 is adulterated, form source, drain electrode.
In the present embodiment, selective epitaxial depositing operation is first adopted to form described germanium-silicon layer 280, described SiGe 280 fills full described second groove and the 3rd groove, then mixes P type ion to described germanium-silicon layer 280 and forms source, drain electrode, and carry out annealing in process to activate described Doped ions.
The base material of the first groove, after formation first groove, is amorphous state by crystalline transformation by embodiments of the invention; In wet-etching technology afterwards, because to being positioned at the etching speed of amorphous state material of the first bottom portion of groove much smaller than being the etching speed of crystalline material to what be positioned at the first recess sidewall, so the second groove that wet etching is formed has sigma shape, and there is smooth bottom, be conducive in described first groove and the second groove, forming germanium-silicon layer in subsequent technique; Meanwhile, after formation second groove, the material being positioned at the amorphous state of the second bottom portion of groove is removed, expose the material for crystalline state, and the material surface of described crystalline state is smooth, so be conducive to follow-up formation germanium-silicon layer;
Further, embodiments of the invention adopt the technique of reactive ion etching to remove the material being positioned at the amorphous state of the second bottom portion of groove, by adjusting the parameter of reactive ion etching process, described reactive ion etching process only can remove the amorphous state material of the second bottom portion of groove, can not have an impact to other structures of transistor.
Correspondingly, the transistor that the present invention also provides said method to be formed, please refer to Fig. 8, comprising: Semiconductor substrate 200, and described Semiconductor substrate 200 surface is formed with grid structure, is formed with groove in described grid structure semiconductor substrates on two sides; Be positioned at the germanium-silicon layer 280 of described groove, the source of described germanium-silicon layer 280 transistor formed, drain electrode; Described groove comprises and being formed from top to down along semiconductor substrate surface, and the second groove communicated and the 3rd groove.
Wherein, the shape of described second groove is sigma shape, and the degree of depth is 300-600 dust; The shape of described 3rd groove is rectangle, and the degree of depth is 10-200 dust.
To sum up, the base material of the first groove, after formation first groove, is amorphous state by crystalline transformation by technical scheme of the present invention; In wet-etching technology afterwards, because to being positioned at the etching speed of amorphous state material of the first bottom portion of groove much smaller than being the etching speed of crystalline material to what be positioned at the first recess sidewall, so the second groove that wet etching is formed has smooth bottom, be conducive in described first groove and the second groove, forming germanium-silicon layer in subsequent technique; Meanwhile, after formation second groove, the material being positioned at the amorphous state of the second bottom portion of groove is removed, expose the material for crystalline state, and the material surface of described crystalline state is smooth, so be conducive to follow-up formation germanium-silicon layer;
Further, technical scheme of the present invention adopts the technique of reactive ion etching to remove the material being positioned at the amorphous state of the second bottom portion of groove, by adjusting the parameter of reactive ion etching process, it is the amorphous state material of the second bottom portion of groove that described reactive ion etching process only can be removed, and can not have an impact to other structures of transistor.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (16)
1. a method for forming semiconductor structure, is characterized in that, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with the first groove, and described first bottom portion of groove material and side-wall material are crystalline state;
Be amorphous state by the material of described first bottom portion of groove by crystalline transformation;
The material transition of described first bottom portion of groove is after amorphous state, carries out wet etching, form the second groove to described first groove, is the base material of amorphous state described in described second groove exposes;
After forming described second groove, be the base material of amorphous state described in removing, expose crystalline material, form the 3rd groove being positioned at the second bottom portion of groove;
The 3rd smooth groove floor is formed the packed layer of filling full described second groove and the 3rd groove.
2. according to method for forming semiconductor structure according to claim 1, it is characterized in that, the described Semiconductor substrate silicon substrate that to be high preferred orientation be (100).
3. according to method for forming semiconductor structure according to claim 1, it is characterized in that, be the base material of amorphous state described in the removal of employing reactive ion etching process, form the 3rd groove.
4. according to method for forming semiconductor structure according to claim 3, it is characterized in that, the parameter of described reactive ion etching process is: pressure is 5-50T, and bias voltage is 50-300V, and etching gas is He, HBr, O
2, etch period is 2-60 second, and wherein the flow of He is the flow of 200-600sccm, HBr is 200-600sccm, O
2flow be 2-20sccm.
5. according to method for forming semiconductor structure according to claim 1, it is characterized in that, adopt ion implantation technology to be amorphous state by the material of described first bottom portion of groove by crystalline transformation.
6. according to method for forming semiconductor structure according to claim 1, it is characterized in that, the shape of described second groove is sigma shape.
7. a semiconductor structure, comprising: Semiconductor substrate, is formed and is formed from top to down along semiconductor substrate surface in described Semiconductor substrate, and the second groove communicated and the 3rd groove; Fill the packed layer of full described second groove and the 3rd groove; It is characterized in that, the shape of described second groove is sigma shape, and the shape of the 3rd groove is rectangle, and described 3rd bottom portion of groove exposes crystalline material.
8. a Transistor forming method, is characterized in that, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with grid structure, and is positioned at the first groove of described grid structure semiconductor substrates on two sides, and the base material of described first groove and side-wall material are crystalline state;
Be amorphous state by the base material of described first groove by crystalline transformation;
After the base material of described first groove changes amorphous state into, carrying out wet etching, form the second groove to described first groove, is the base material of amorphous state described in described second groove exposes;
After forming described second groove, be the base material of amorphous state described in removing, expose crystalline material, form the 3rd groove being positioned at the second bottom portion of groove;
The 3rd smooth groove floor forms germanium-silicon layer in described second groove and the 3rd groove, and described germanium-silicon layer is adulterated, form source, drain electrode.
9. according to Transistor forming method according to claim 8, it is characterized in that, the described Semiconductor substrate silicon substrate that to be high preferred orientation be (100).
10. according to Transistor forming method according to claim 8, it is characterized in that, be the base material of amorphous state described in the removal of employing reactive ion etching process, form the 3rd groove.
11., according to Transistor forming method according to claim 10, is characterized in that, the parameter of described reactive ion etching process is: pressure is 5-50T, and bias voltage is 50-300V, and etching gas is He, HBr, O
2, etch period is 2-60 second, and wherein the flow of He is the flow of 200-600sccm, HBr is 200-600sccm, O
2flow be 2-20sccm.
12., according to Transistor forming method according to claim 8, is characterized in that, adopt ion implantation technology to be amorphous state by the base material of described first groove by crystalline transformation.
13., according to Transistor forming method according to claim 12, is characterized in that, the ion that described ion implantation technology is injected is germanium, and the energy 3-10kev of injection, dosage is 1E14-5E15atom/cm
2.
14., according to Transistor forming method according to claim 8, is characterized in that, the shape of described second groove is sigma shape, and the degree of depth is 300-600 dust; The shape of described 3rd groove is rectangle, and the degree of depth is 10-200 dust.
15. 1 kinds of transistors, comprising: Semiconductor substrate, and described semiconductor substrate surface is formed with grid structure, are formed with groove in described grid structure semiconductor substrates on two sides; Be positioned at the germanium-silicon layer of described groove, the source of described germanium-silicon layer transistor formed, drain electrode; It is characterized in that, described groove comprises and being formed from top to down along semiconductor substrate surface, and the second groove communicated and the 3rd groove, the shape of wherein said second groove is sigma shape, the shape of described 3rd groove is rectangle, and described 3rd bottom portion of groove exposes crystalline material.
16., according to transistor according to claim 15, is characterized in that, the degree of depth of described second groove is 300-600 dust; The degree of depth of described 3rd groove is 10-200 dust.
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