CN102968970A - Driving device and driving method for display panel - Google Patents
Driving device and driving method for display panel Download PDFInfo
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- CN102968970A CN102968970A CN2012104305423A CN201210430542A CN102968970A CN 102968970 A CN102968970 A CN 102968970A CN 2012104305423 A CN2012104305423 A CN 2012104305423A CN 201210430542 A CN201210430542 A CN 201210430542A CN 102968970 A CN102968970 A CN 102968970A
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Abstract
The invention discloses a driving device and driving method for a display panel. The driving device for the display panel comprises a time sequence controller, a grid driver and a logic driver. The logic driver is used for receiving grid control signals output by the time sequence controller, obtaining level signals on display panel grid lines, obtaining resistance-capacitance (RC) Delay signals, compensating the grid control signals by utilizing the RC Delay signals, and outputting the compensated grid control signals to the grid driver. The grid driver is used for generating grid driving signals according to the compensated grid control signals and outputting the grid control signals to the display panel grid lines. Due to the fact that the logic driver is added to obtain the RC Delay signals on the grid lines and compensate the grid control signals, the problem that data signals of a thin film transistor (TFT) corresponding to each line of grid line are confused due to RC Delay is effectively solved.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of drive unit and driving method of display panel.
Background technology
TFT(Thin Film Transistor, Thin Film Transistor (TFT))-and LCD(Liquid Crystal Display, a kind of liquid crystal display) mainly formed by liquid crystal panel, gate drivers (also claiming gate driver circuit), data driver (also claiming data drive circuit), time schedule controller, gamma electric voltage maker and backlight.Liquid crystal panel is made of array base palte and color membrane substrates and liquid crystal.Data line and grid line are formed on the array base palte, and the TFT that is arranged on data line and grid line infall is used for the data-signal of data driver output is sent to the pixel electrode of array base palte, to drive liquid crystal corresponding to pixel electrode.
Shown in Figure 1 is the structural representation that existing a kind of TFT-LCD of realization drives.Wherein, time schedule controller 10 is used for generating grid control signal and source control signal according to the synchronizing signal of input, and to gate drivers 40 output grid control signals, to data driver 30 output source control signal.This grid control signal is used for control gate driver 40, includes but not limited to CPV(Clock Pulse Vertical, gate clock) signal and grid OE(Output Enable, output enable) signal; This source control signal is used for control data driver 30.Gamma electric voltage maker 20 is used for generating a plurality of voltage signals that determine the gamma GTG, and exports a plurality of voltage signals of the decision gamma GTG that generates to data driver 30.The grid control signal that gate drivers 40 is used for according to time schedule controller 10 outputs generates gate drive signal, and the TFT that this gate drive signal connects for the control grid line opens or closes.The source control signal that data driver 30 is used for according to time schedule controller 10 outputs generates and drives the required data-signal of liquid crystal, and by the pixel electrode outputting data signals of TFT to liquid crystal panel 50.
Realize in the circuit structure of TFT-LCD driving that gate drivers 40 begins to export gate drive signal at the negative edges of grid OE signal usually.And when gate drivers 40 outputs were used for starting the gate drive signal GATE1 of the capable grid line of n, data driver 30 outputed to the data-signal DATA that each pixel electrode is corresponding on this row grid line on each TFT corresponding to this row grid line.Shown in Figure 2 is the desirable sequential relationship synoptic diagram of gate drive signal, overlapping to not existing between the gate drive signal of every row grid line output.That is to say that all close at each TFT corresponding to lastrow grid line and have no progeny, the TFT that the next line grid line is corresponding just can open.
Actual conditions are that on a grid line, from initial segment to the end section, each position gate drive signal all exists RC Delay(resistance capacitance to postpone), cause the rising edge of gate drive signal and negative edge that certain time-delay is arranged.The gate drive signal of TFT-LCD actual time order relation as shown in Figure 3.If the time-delay of gate drive signal is more serious, when the gate drive signal GATE1 of the capable grid line of n was in negative edge, the gate drive signal GATE2 of the capable grid line of n+1 had begun to rise so.Each TFT that then the capable grid line of n is corresponding does not also all turn-off, each TFT on the capable grid line of n+1 has opened, data driver begins each TFT outputting data signals on the capable grid line of n+1, cause the data-signal of each TFT corresponding with outputing to the capable grid line of n to obscure, affect picture disply.
Summary of the invention
The Drive And Its Driving Method that the purpose of this invention is to provide a kind of display panel is to solve the delay issue of gate drive signal.
The objective of the invention is to be achieved through the following technical solutions:
A kind of drive unit of display panel comprises:
Time schedule controller is used for sending grid control signal to logical drive;
Logical drive, be used for receiving the grid control signal of described time schedule controller output, obtain the level signal on the display panel grid line, the capacitance resistance that obtains on the described grid line according to the level signal on the described grid line postpones RC Delay signal, utilize the RC Delay signal on the described grid line that described grid control signal is compensated, and the grid control signal after the described gate drivers output compensation;
Described gate drivers is used for generating gate drive signal according to the grid control signal after the described compensation, and exports described gate drive signal to described display panel grid line.
Preferably, described logical drive comprises:
Analog to digital converter is used for the RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Totalizer is used for converting the grid control signal of digital signal to and the RC Delay signal of described grid line carries out additive operation, generates the grid control signal after compensating;
Digital to analog converter is used for the grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
Preferably, described logical drive comprises:
Analog to digital converter is used for the RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The XOR module is used for converting the grid control signal of digital signal to and the RC Delay signal of described grid line carries out XOR, generates the grid control signal after compensating;
Digital to analog converter is used for the grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
Preferably, described logical drive also comprises:
Feedback signal line is connected with each grid line on the described display panel, is used for obtaining the level signal on the display panel grid line.
A kind of driving method of display panel comprises:
Logical drive receives the grid control signal of time schedule controller output;
Described logical drive obtains the level signal on the display panel grid line;
Described logical drive obtains the RC Delay signal of described grid line according to the level signal on the described grid line;
Described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation;
The grid control signal of described gate drivers after according to described compensation generates gate drive signal, and exports described gate drive signal to described display panel grid line.
Preferably, described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Carry out additive operation with converting the grid control signal of digital signal and the RC Delay signal of described grid line to, generate the grid control signal after compensating;
Grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
Preferably, described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Carry out XOR with converting the grid control signal of digital signal and the RC Delay signal of described grid line to, generate the grid control signal after compensating;
Grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
Because having increased logical drive obtains grid line RC Delay signal and grid control signal is compensated, thereby effectively reduced the RC Delay impact that output causes on signal, avoid the data-signal of TFT corresponding to each row grid line to obscure, affected the problem of picture disply.
Description of drawings
Fig. 1 is the structural representation that existing techniques in realizing TFT-LCD drives;
Fig. 2 is the desirable sequential relationship synoptic diagram of prior art gate drive signal;
Fig. 3 is order relation synoptic diagram actual time of prior art gate drive signal;
The driving device structure synoptic diagram of the display panel that Fig. 4 provides for the embodiment of the invention;
The structural representation of a kind of logical drive that Fig. 5 provides for the embodiment of the invention;
The structural representation of the another kind of logical drive that Fig. 6 provides for the embodiment of the invention;
Order relation synoptic diagram actual time of the gate drive signal that Fig. 7 provides for the embodiment of the invention;
The method flow diagram that Fig. 8 provides for the embodiment of the invention.
Embodiment
In order to solve the delay issue of gate drive signal, the embodiment of the invention provides a kind of drive unit of display panel, comprises at least: time schedule controller, gate drivers and logical drive.Wherein, time schedule controller sends grid control signal to logical drive.Logical drive receives the grid control signal of time schedule controller output, obtain the level signal on the display panel grid line, obtain RC Delay signal on the described grid line according to the level signal on the described grid line, utilize the RC Delay signal on the described grid line that described grid control signal is compensated, and the grid control signal after the described gate drivers output compensation.The grid control signal of gate drivers after according to described compensation generates gate drive signal, and exports described gate drive signal to described display panel grid line.Because having increased logical drive obtains grid line RC Delay signal and grid control signal is compensated, thereby effectively reduced the RC Delay impact that output causes on signal, avoid the data-signal of TFT corresponding to each row grid line to obscure, affected the problem of picture disply.
In the embodiment of the invention, described display panel comprises color membrane substrates and array base palte.The grid line of described display panel can refer to, is arranged on the grid line on the array base palte of display panel.
Below in conjunction with accompanying drawing the technical scheme that the embodiment of the invention provides is elaborated.
The drive unit of a kind of preferred display panel that the embodiment of the invention provides, its implementation structure comprises as shown in Figure 4 at least: time schedule controller 10, gamma electric voltage maker 20, data driver 30, gate drivers 40 and logical drive 60.
This drive unit is used for driving display panel 70.Described display panel 70 comprises array base palte, color membrane substrates and liquid crystal.Array base palte comprises grid line, the data line of ranks cross-distribution, the pixel switch of every grid line and data line infall.Described display panel 70 can but be not limited only to display panels.Concrete:
Time schedule controller 10 such as clock signal, horizontal-drive signal, vertical synchronizing signal and data enable signal etc., has also been inputted RGB(Red Green Blue, RGB from outside input sync signal) the demonstration data.
Time schedule controller 10 uses the synchronizing signal of input to generate grid control signal and source control signal, and to logic controller 60 output grid control signals, data controlling signal is exported to data driver.The grid control signal that generates can but be not limited only to CPV signal and grid OE signal.
Gamma electric voltage maker 20 generates a plurality of voltage signals that determine the gamma GTG, and exports a plurality of voltage signals of the decision gamma GTG that generates to data driver 30.
Gate drivers 40 generates gate drive signal according to the grid control signal of input, and this gate drive signal is used for the pixel switch of the grid line connection of control display panel 70 and opens or close.Concrete, gate drive signal begins to export gate drive signal at the negative edge of grid OE signal, in the cycle, only exports gate drive signal to a grid line of display panel 70 at each CPV.
Data driver 30 generates the required data-signal of pixel that drives display panel according to the source control signal of time schedule controller 10 outputs, and by the pixel data output signal of pixel switch to display panel 70.
Logical drive 60 receives the grid control signal of time schedule controller 10 outputs, obtain the level signal of the grid line that the current C PV cycle enables from the array base palte of display panel 70, obtain RC Delay signal on this grid line according to the level signal on this grid line, utilize the RC Delay signal of this grid line that above-mentioned grid control signal is compensated, and the grid control signal after the gate drivers 40 output compensation.
Concrete, can compare by the level signal that will obtain from this grid line and the gate drive signal of this grid line, obtain the RC Delay signal on this grid line.
Wherein, the level signal of obtaining from grid line i.e. the gate drive signal that postpones of this row grid line.In order to obtain the level signal of grid line, logical drive 60 also comprises feedback signal line, and this feedback signal line is connected with each grid line on the array base palte.Because grid line all has RC Delay everywhere, and RC Delay everywhere is cumulative, and therefore, at the end of grid line, the RC Delay of its level signal is the most serious, and feedback signal line can be connected with the end of each grid line.So-called grid line end refers to, an end that is connected with gate drivers 30 away from grid line.
Because having increased logical drive obtains grid line RC Delay signal and grid control signal is compensated, and then control is to the time of every row grid line output gate drive signal, so that the gate drive signal on lastrow grid line in next line grid line output gate drive signal disappears, thereby effectively reduced the RC Delay impact that output causes on signal, avoid the data-signal of pixel switch (such as TFT) corresponding to each row grid line to obscure, affected the problem of picture disply.
In the embodiment of the invention, specifically can compensate grid control signal by additive operation, also can compensate grid control signal by XOR.Can also by other means, utilize the RCDelay signal that grid control signal is compensated.Accordingly, the embodiment of the invention provides the implementation structure of two kinds of preferred logical drives.
The preferred implementation structure of the first as shown in Figure 5, logical drive 60 comprises at least: ADC(Analog-to-Digital Converter, analog to digital converter), be used for the RC Delay signal of grid control signal and current grid line is converted to digital signal; The Adder(totalizer), is used for to convert the grid control signal of digital signal to and the RC Delay signal of current grid line carries out additive operation, generates the grid control signal after the compensation; DAC(Digital-to-Analog Converter, analog to digital converter), the grid control signal after being used for compensating is converted to simulating signal and exports to gate drivers 30.
Concrete, Adder will carry out additive operation respectively with through analog-to-digital CPV signal and OE signal through analog-to-digital RC Delay signal.CPV signal after process Adder processes and OE signal are as shown in Figure 7.
The preferred implementation structure of the second as shown in Figure 6, logical drive comprises at least: ADC is used for grid control signal and grid RC Delay signal are converted to digital signal; XOR module 80 is carried out XOR for grid control signal and the grid RC Delay signal that will convert digital signal to, generates the grid control signal after compensating; DAC, the grid control signal after being used for compensating is converted to simulating signal and exports to gate drivers.
Concrete, the ADC module is carried out analog-to-digital conversion process with RC Delay signal, CPV signal and OE signal respectively, XOR module 80 will be carried out additive operation respectively with through analog-to-digital CPV signal and OE signal through analog-to-digital RC Delay signal, and the CPV1 signal that DAC will obtain after will processing through Adder and OE1 signal carry out digital-to-analog conversion to be processed.CPV1 signal after process XOR module 80 is processed and OE1 signal are as shown in Figure 7.Wherein, GATE1 is the gate drive signal of current line grid line, and GAT2 is the gate drive signal of next line grid line.
The present invention also provides a kind of driving method of display panel, and its implementation specifically comprises following operation as shown in Figure 8:
Preferably, described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Carry out additive operation with converting the grid control signal of digital signal and the RC Delay signal of described grid line to, generate the grid control signal after compensating;
Grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
Preferably, described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Carry out converting the grid control signal of digital signal and the RC Delay signal of described grid line to, generate the grid control signal after compensating;
Grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. the drive unit of a display panel is characterized in that, this device comprises:
Time schedule controller is used for sending grid control signal to logical drive;
Logical drive, be used for receiving the grid control signal of described time schedule controller output, obtain the level signal on the display panel grid line, the capacitance resistance that obtains on the described grid line according to the level signal on the described grid line postpones RC Delay signal, utilize the RC Delay signal on the described grid line that described grid control signal is compensated, and the grid control signal after the described gate drivers output compensation;
Described gate drivers is used for generating gate drive signal according to the grid control signal after the described compensation, and exports described gate drive signal to described display panel grid line.
2. drive unit according to claim 1 is characterized in that, described logical drive comprises:
Analog to digital converter is used for the RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Totalizer is used for converting the grid control signal of digital signal to and the RC Delay signal of described grid line carries out additive operation, generates the grid control signal after compensating;
Digital to analog converter is used for the grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
3. drive unit according to claim 1 is characterized in that, described logical drive comprises:
Analog to digital converter is used for the RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The XOR module is used for converting the grid control signal of digital signal to and the RCDelay signal of described grid line carries out XOR, generates the grid control signal after compensating;
Digital to analog converter is used for the grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
4. according to claim 2 or 3 described drive units, it is characterized in that described logical drive also comprises:
Feedback signal line is connected with each grid line on the described display panel, is used for obtaining the level signal on the display panel grid line.
5. the driving method of a display panel is characterized in that, comprising:
Logical drive receives the grid control signal of time schedule controller output;
Described logical drive obtains the level signal on the display panel grid line;
Described logical drive obtains the RC Delay signal of described grid line according to the level signal on the described grid line;
Described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation;
The grid control signal of described gate drivers after according to described compensation generates gate drive signal, and exports described gate drive signal to described display panel grid line.
6. driving method according to claim 5 is characterized in that, described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Carry out additive operation with converting the grid control signal of digital signal and the RC Delay signal of described grid line to, generate the grid control signal after compensating;
Grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
7. driving method according to claim 5 is characterized in that, described logical drive utilizes the RC Delay signal of described grid line that described grid control signal is compensated, and the grid control signal after the gate drivers output compensation, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
Carry out XOR with converting the grid control signal of digital signal and the RC Delay signal of described grid line to, generate the grid control signal after compensating;
Grid control signal after the described compensation is converted to simulating signal and exports to described gate drivers.
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