CN102967791B - Inspection method for judging contact of digital circuit board test pen and test pen - Google Patents
Inspection method for judging contact of digital circuit board test pen and test pen Download PDFInfo
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- CN102967791B CN102967791B CN201210457590.1A CN201210457590A CN102967791B CN 102967791 B CN102967791 B CN 102967791B CN 201210457590 A CN201210457590 A CN 201210457590A CN 102967791 B CN102967791 B CN 102967791B
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- 238000012360 testing method Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000007689 inspection Methods 0.000 title claims abstract description 12
- 239000000523 sample Substances 0.000 claims description 64
- 230000000052 comparative effect Effects 0.000 claims description 5
- 238000012550 audit Methods 0.000 claims description 2
- 238000003745 diagnosis Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 101000579647 Penaeus vannamei Penaeidin-2a Proteins 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
The invention discloses an inspection method for judging contact of a digital circuit board test pen and a digital circuit board test pen with a contact inspection function, which are applied to the field of testing of the digital circuit boards. According to the inspection method disclosed by the invention, a method for comparing preset voltage with voltage is utilized to judge and display whether the test pen contacts well with a test point on the circuit board or not on the condition of not affecting a digital signal collected or received by the test pen, thereby avoiding misjudgment of the test result due to poor contact of the test pen.
Description
Technical field
The present invention relates to digital circuit board field tests, be specifically related to a kind of inspection method of the contact for judging digital circuit board test pen and realize the test probe pen of described probe pen contact inspection.
Background technology
In today of informationized society high speed development; digital circuit has been widely used in the every field such as computing machine, network, digital entertainment and Industry Control; in the process of the development of these electronic equipments, production, test and use; all there is the on-line testing demand of a series of digital circuit board; usually the equipment such as logic analyser can be used; when using these equipment, need the probe pen of equipment to access well in digital circuit board.
Patented claim " under a kind of test probe pen pin point calibration method " (applying date 2012.04.24, application number is 201210121618.4) disclose a kind of camera that utilizes to point calibration under the pin of test probe pen and accurate method of locating, after point calibration under pin, as long as watch tracking cross on the computer screen to aim at measured target point, and drop test probe pen need not make probes touch circuit board, can judge that test probe pen reaches measured target point, thus test probe pen can be made accurately to fall measured target point.But current most of circuit board surface all covers one deck insullac, even if time during detection on probes touch to circuit board, because insullac is sometimes thicker, probe is insulation-piercing enamelled coating not necessarily, at this moment probe seems and electrical contact, but reality is good contact not, now by probe collection to signal truly can not reflect actual signal, thus cause the erroneous judgement to circuit signal.
Summary of the invention
The object of the invention is to, a kind of inspection method and the test probe pen that judge the contact of digital circuit board test pen are provided, to realize judging in the digital circuit of the access circuit-under-test plate whether probe pen is good, and when not affecting signal on circuit board the signal of accurate acquisition circuit board test point, thus fault diagnosis is carried out to circuit board.
For reaching above-mentioned purpose, the inspection method of the contact of judgement digital circuit board test pen provided by the invention comprises:
Under preset non-contact condition, the logic state of probe pen is the third logic state outside digital circuit logic state;
Judge the circuit logic state at probe pen and digital circuit board contact point place;
Judge whether good contact is in digital circuit board in contact according to the logic state of probe pen contact.
The digital circuit board test pen with contact audit function provided by the invention, is characterized in that comprising contact point voltage initialization circuit, logical one lower voltage limit arranges circuit, logical zero upper voltage limit arranges circuit, contact point voltage comparator circuit, decision circuitry and indicating circuit:
Contact point voltage initialization circuit: for the voltage initialization of probe pen contact is become preset voltage, this preset voltage is the intermediate value voltage of logical one lower voltage limit value and logical zero upper voltage limit value, when probe pen is not with circuit board contacts, the voltage of probe pen contact is just this preset voltage, once probe pen and circuit board contacts, then the voltage at the voltage of probe pen contact contact circuit plate place by becoming;
Logical one lower voltage limit arranges circuit: for generation of logical one lower voltage limit, as the discrimination standard of logical one voltage on circuit board;
Logical zero upper voltage limit arranges circuit: for generation of logical zero upper voltage limit, as the discrimination standard of logical zero voltage on circuit board;
Contact point voltage comparator circuit: the voltage of contact point is compared with logical one lower voltage limit, logical zero upper voltage limit and exports comparative result respectively respectively;
Decision circuitry: two comparative results that contact point voltage comparator circuit exports are carried out logical combination, judges whether contact point accesses in digital circuit;
Indicating circuit: be used to indicate judged result.
Utilize the present invention, when using probe pen (as circuit fault diagnosis system probe pen, logic analyser probe pen) to contact the test point on digital circuit board, can ensure that the contact of probe pen can not affect the original signal amount of test point, whether good with measured number circuit board contacts clearly can show probe pen simultaneously, thus avoid the data causing because of probe pen loose contact and read mistake.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that test probe pen detects on digital circuit board;
Fig. 2 is the probe pen contact check circuit schematic diagram that the specific embodiment of the invention realizes.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Be illustrated in figure 1 the schematic diagram that test probe pen detects on digital circuit board.In test process, by digital signal acquiring equipment 1(as logic analyser, circuit fault diagnosis system etc.) probe pen 2 access in circuit-under-test plate 3, under the state of circuit working, the signal of test point is gathered.
As shown in Figure 2, for the digital circuit board of Transistor-Transistor Logic level, circuit adopts direct supply 4(as button cell) power supply.Resistance 5 and resistance 6 form logical zero upper voltage limit and arrange circuit, and dividing potential drop produces logical zero upper voltage limit standard value (i.e. 0.8V).Resistance 7 and resistance 8 form logical one lower voltage limit and arrange circuit, and dividing potential drop produces logical one lower voltage limit standard value (i.e. 2.4V).Resistance 9 and resistance 10 form contact point voltage initialization circuit, dividing potential drop produces preset voltage time probe pen unsettled (i.e. non-contact circuit plate), under preset non-contact condition, the logic state of probe pen is the third logic state outside digital circuit logic state, this preset voltage is neither in logical one voltage range, also, not in logical zero voltage range, be the intermediate value voltage (i.e. 1.6V) of logical zero upper voltage limit standard value and logical one lower voltage limit standard value.First comparer 11 and the second comparer 12 form contact point voltage comparator circuit, for judging the circuit logic state at probe pen and digital circuit board contact point place.Logical one lower voltage limit is accessed the end of oppisite phase of the first comparer 11, logical zero upper voltage limit accesses the in-phase end of the second comparer 12.Now, the end of oppisite phase voltage of the first comparer 11 is 2.4V, and the in-phase end voltage of the second comparer 12 is 0.8V.The output terminal of the first comparer 11 and the second comparer 12 is connected respectively to or the input end of door 13.Or door 13 forms decision circuitry, for according to the circuit logic condition adjudgement contact of probe pen contact, whether good contact is in digital circuit board, or the output terminal of door 13 is connected with LED 15 through current-limiting resistance 14, control the lighting and extinguish of LED 15, thus instruction probe pen whether with circuit board test point good contact.
When probe pen 2 is unsettled, the in-phase end voltage of the first comparer 11 is 1.6V, is less than end of oppisite phase voltage, so the output of the first comparer 11 is 0; Now, the end of oppisite phase voltage of the second comparer 12 is 1.6V, is greater than in-phase end voltage, so the output of the second comparer 12 is 0; Through or door 13 after export be 0, LED 15 is in OFF state.
Touch the test point on circuit board when probe pen 3 after, and now circuit board is in running order, and the voltage now on probe pen contact is the voltage of test point, and the semaphore for digital circuit on-board circuitry only has logical one state and logical zero state.If test point is logical one state, now test point voltage is greater than 2V, then the in-phase end voltage of the first comparer 11 is greater than end of oppisite phase voltage, export as " 1 " (close to 5V), the in-phase end voltage of the second comparer 12 is less than end of oppisite phase voltage, exports as " 0 ", thus through or door 13 after, export as " 1 ", LED lamp 15 is lighted.
In like manner, when probe pen touches test point, test point is logical zero state, and when now test point voltage is less than 1V, the in-phase end voltage of the first comparer 11 is less than end of oppisite phase voltage, exports as " 0 "; The in-phase end voltage of the second comparer 12 is greater than end of oppisite phase voltage, exports as " 1 "; Through or door 13 after export be 1, LED 15 is also lighted.
Can find out whether probe pen is linked in circuit by the state of LED, if namely LED 15 light represent probe pen be linked in circuit, if LED 15 extinguish represent probe pen do not contact with circuit.
As shown in Figure 2, while the signal of circuit board test point is connected to contact check circuit, is also connected to digital signal acquiring equipment 1 simultaneously, therefore can be implemented in the contact situation of ray examination probe pen.
Although depict the present invention by embodiment, those of ordinary skill in the art know, the present invention has many distortion and change and do not depart from spirit of the present invention, and the claim appended by wishing comprises these distortion and change.
Claims (6)
1. judge an inspection method for the contact of digital circuit board test pen, it is characterized in that comprising:
Under preset non-contact condition, the logic state of probe pen is the third logic state outside digital circuit logic state; The third logic state described refers to neither in logical one voltage range, also not in logical zero voltage range;
Judge the circuit logic state at probe pen and digital circuit board contact point place; Concrete steps are: compared by the logical one lower voltage limit in probe pen contact voltage and measured number circuit board, judge whether contact logic state is 1; Logical zero upper voltage limit in probe pen contact voltage and measured number circuit board is compared, judges whether contact logic state is 0;
According to the circuit logic condition adjudgement contact of probe pen contact, whether good contact is in digital circuit board.
2. judge the inspection method of the contact of digital circuit board test pen as claimed in claim 1, it is characterized in that whether good contact to the method in digital circuit board is according to the circuit logic condition adjudgement contact of probe pen contact: according to the logic state judged result of probe pen contact, if the logic state of contact is " 1 " or " 0 ", then show that probe pen contact is well accessed in measured number circuit board; If the voltage of contact is neither logical one voltage neither logical zero voltage, then show that probe pen contact is not and measured number circuit board contacts.
3. there is a digital circuit board test pen for contact audit function, it is characterized in that comprising contact point voltage initialization circuit, logical one lower voltage limit arranges circuit, logical zero upper voltage limit arranges circuit, contact point voltage comparator circuit, decision circuitry and indicating circuit:
Contact point voltage initialization circuit: for the voltage initialization of probe pen contact is become preset voltage, this preset voltage is the intermediate value voltage of logical one lower voltage limit value and logical zero upper voltage limit value, when probe pen is not with circuit board contacts, the voltage of probe pen contact is just this preset voltage, once probe pen and circuit board contacts, then the voltage at the voltage of probe pen contact contact circuit plate place by becoming;
Logical one lower voltage limit arranges circuit: for generation of logical one lower voltage limit, as the discrimination standard of logical one voltage on circuit board;
Logical zero upper voltage limit arranges circuit: for generation of logical zero upper voltage limit, as the discrimination standard of logical zero voltage on circuit board;
Contact point voltage comparator circuit: the voltage of contact point is compared with logical one lower voltage limit, logical zero upper voltage limit and exports comparative result respectively respectively;
Decision circuitry: two comparative results that contact point voltage comparator circuit exports are carried out logical combination, judges whether contact point accesses in digital circuit;
Indicating circuit: be used to indicate judged result.
4. test probe pen as claimed in claim 3, it is characterized in that described contact point voltage comparator circuit comprises the first comparer and the second comparer:
First comparer is used for the lower voltage limit of contact point voltage and logical one to compare;
Second comparer is used for the upper voltage limit of contact point voltage and logical zero to compare.
5. test probe pen as claimed in claim 3, it is characterized in that described decision circuitry comprises one or door: two comparative results for contact point voltage comparator circuit is exported get or, described in get or after result be used for judging whether contact point accesses in digital circuit.
6. test probe pen as claimed in claim 3, it is characterized in that described indicating circuit adopts the result of LED instruction inspection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210457590.1A CN102967791B (en) | 2012-11-15 | 2012-11-15 | Inspection method for judging contact of digital circuit board test pen and test pen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210457590.1A CN102967791B (en) | 2012-11-15 | 2012-11-15 | Inspection method for judging contact of digital circuit board test pen and test pen |
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| Publication Number | Publication Date |
|---|---|
| CN102967791A CN102967791A (en) | 2013-03-13 |
| CN102967791B true CN102967791B (en) | 2015-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210457590.1A Expired - Fee Related CN102967791B (en) | 2012-11-15 | 2012-11-15 | Inspection method for judging contact of digital circuit board test pen and test pen |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104316864B (en) * | 2014-10-30 | 2018-06-22 | 通富微电子股份有限公司 | Semiconductor test jig |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2147548Y (en) * | 1992-09-15 | 1993-11-24 | 四川大学 | Digital IC testing instrument and testing probe |
| CN2438273Y (en) * | 2000-06-12 | 2001-07-04 | 麦肯积体电路股份有限公司 | Circuit for testing mains voltage across points |
| CN2874512Y (en) * | 2006-01-14 | 2007-02-28 | 比亚迪股份有限公司 | High voltage detection warning instrument for battery |
| CN102621482A (en) * | 2012-04-24 | 2012-08-01 | 河南正泰信创新基地有限公司 | Testing pen needle lower point correcting method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001194407A (en) * | 2000-01-17 | 2001-07-19 | Nec Ibaraki Ltd | Method and apparatus of electrical inspection for pattern wiring board |
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2012
- 2012-11-15 CN CN201210457590.1A patent/CN102967791B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2147548Y (en) * | 1992-09-15 | 1993-11-24 | 四川大学 | Digital IC testing instrument and testing probe |
| CN2438273Y (en) * | 2000-06-12 | 2001-07-04 | 麦肯积体电路股份有限公司 | Circuit for testing mains voltage across points |
| CN2874512Y (en) * | 2006-01-14 | 2007-02-28 | 比亚迪股份有限公司 | High voltage detection warning instrument for battery |
| CN102621482A (en) * | 2012-04-24 | 2012-08-01 | 河南正泰信创新基地有限公司 | Testing pen needle lower point correcting method |
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| CN102967791A (en) | 2013-03-13 |
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