CN102963862A - Manufacturing method of net-shaped mono-crystalline silicon nano-wire array structure - Google Patents
Manufacturing method of net-shaped mono-crystalline silicon nano-wire array structure Download PDFInfo
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- CN102963862A CN102963862A CN2012105147376A CN201210514737A CN102963862A CN 102963862 A CN102963862 A CN 102963862A CN 2012105147376 A CN2012105147376 A CN 2012105147376A CN 201210514737 A CN201210514737 A CN 201210514737A CN 102963862 A CN102963862 A CN 102963862A
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
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- C—CHEMISTRY; METALLURGY
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
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- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Abstract
The invention provides a manufacturing method of a net-shaped mono-crystalline silicon nano-wire array structure. The manufacturing method comprises the following steps of: manufacturing an anti-oxidization mask and forming mask windows on a crystal-face-type silicon sheet (111); etching mono-crystalline silicon to a pre-set depth by an ICP (Inductively Coupled Plasma) etching method; carrying out anisotropism wet-method corrosion on the mono-crystalline silicon under each mask window, thus forming a plurality of corrosion grooves with upper and lower hexagonal surfaces and forming a mono-crystalline silicon thin-wall between the side walls of each two adjacent corrosion grooves; carrying out heat oxidization on the mono-crystalline silicon thin-walls by a self-limitation oxidization process, thus forming mono-crystalline silicon nano-wires in the central regions of the tops of the mono-crystalline silicon thin-walls; and removing the anti-oxidization mask and silicon oxide, thus forming the net-shaped mono-crystalline silicon nano-wire array structure. The manufacturing method disclosed by the invention has a simple and efficient process; a key step of the method only relates to the common photoetching and corrosion processes as well as the anti-oxidization mask and the anisotropism corrosion; and under the regular mask preparation condition and the regular photoetching condition, the manufacturing method can be used for manufacturing mono-crystalline silicon nano-wire combined patterns in a large scale on the silicon sheet by virtue of a crystal face distribution characteristic in the crystal-face-type silicon sheet (111).
Description
Technical field
The present invention relates to a kind of preparation method of silicon nanowires, particularly relate to a kind of preparation method of monocrystalline silicon nano line mesh array structure.
Background technology
Development along with nanoscale science and technology, the nanostructured of material because usually show from its macrostate under different characteristic and more and more be subject to the researcher and pay attention to, people wish by nanostructured being launched the research of performances such as electricity, calorifics, optics and mechanics, thereby can better understand the various effects under the nanoscale, therefore realize the deeper relation of understanding between material microstructure and its character, and design and manufacture and have the more application device of excellent properties.Standard material as CMOS technique and MEMS technology especially is subject to people's favor to the research of monocrystalline silicon nanometer structure and nano-device.Studies show that under the nano thread structure of (standard) one dimension, monocrystalline silicon presents multiple valuable physical characteristic.For example, the piezoresistance coefficient of silicon nanowires has improved more than 50% than body silicon materials; Thermoelectric figure of merit coefficient ZT is along with the silicon nanowires diameter reduces, at room temperature even surpassed 1; Realize that through the silicon nanowires that erbium mixes wavelength is photoluminescence property of 1.54um etc. under the room temperature.In addition, along with the increase of specific area, monocrystalline silicon nano line electrology characteristic effects on surface state such as the variations such as electric charge, quality become very responsive, thereby make it be suitable as very much the sensing element of multiple high sensitive sensor.Just because of these new physical characteristics, silicon nanowires is considered to requisite part in following nano electron device, nano-photon device and the nano energy switching device.
Present method (top-down) by making the monocrystalline silicon nanometer structure line from top to bottom, namely remove unwanted part on the material by the location, stay the nanostructured that meets design, comprise electron-beam direct writing, deep-UV lithography, the nanometer etching technologies such as nano impression, although technological principle is comparatively simple, preparation technology's costliness is time-consuming, very is not applicable to general research in nanotechnology work.In recent years, it is found that when monocrystalline silicon nanometer structure carried out oxidation, the skin of nanostructured is owing to volumetric expansion after the oxidation is pushed the unoxidized zone of internal layer, thereby the internal layer in nanostructured produces larger stress, and because the existence of this stress, the oxidation rate of internal layer silicon atom is starkly lower than outer silicon atom, and this phenomenon is called as " certainly limiting oxidation ", and usually is used for the preparation of monocrystalline silicon nano line structure as a kind of cheaply size technology of dwindling.Thus, at present part research has realized on the Multi-layer silicon of the individual layer silicon chip of (100) crystal face type, (110) crystal face type, (111) crystal face type or soi structure, crystal face characteristic distributions according to corresponding monocrystalline silicon piece, use and based on anisotropic wet etching and the method that certainly limits oxidation the monocrystalline silicon figure is carried out size and dwindle, thereby prepare single or follow monocrystalline silicon nano line along particular crystal orientation more.This class has lower cost of manufacture based on the method that anisotropic wet corrosion and oxidizing process prepare monocrystalline silicon nano line, is fit to prepare in enormous quantities.Yet the monocrystalline silicon nano line of these methods preparation is separate structure parallel to each other often, forms complicated combining structure, has therefore limited its potential application in field of nanometer technology.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of preparation method of monocrystalline silicon nano line mesh array structure, be used for to solve often separate structure parallel to each other of prior art monocrystalline silicon nano line, be difficult to form the problem of complicated combining structure.
Reach for achieving the above object other relevant purposes, the invention provides a kind of preparation method of monocrystalline silicon nano line mesh array structure, described preparation method may further comprise the steps at least:
1) provides the monocrystal silicon substrate of one (111) crystal face, make anti-oxidant mask in this monocrystal silicon substrate surface;
2) adopt photoetching process in described anti-oxidant mask, to form a plurality of mask windows of the default queueing discipline with preset shape;
3) adopt the ICP etching method, the monocrystalline silicon of this mask window below respectively is etched to a predetermined depth;
4) monocrystalline silicon of this mask window below is respectively carried out the anisotropic wet corrosion, forming upper and lower surface is hexagonal a plurality of etching tank, forms the monocrystalline silicon thin-walled between the sidewall of adjacent two etching tanks;
5) employing is carried out thermal oxide from limiting oxidation technology to above-mentioned resulting structures, makes the gradually oxidation of described monocrystalline silicon thin-walled, forms along the monocrystalline silicon nano line of monocrystalline silicon thin-walled length direction extension in described monocrystalline silicon thin-walled center of top zone at last;
6) remove the silica that forms in described anti-oxidant mask and the oxidizing process, form monocrystalline silicon nano line mesh array structure.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, described anti-oxidant mask is that thickness is that silicon nitride film or the thickness of 10nm ~ 2 μ m is the silica of 100nm ~ 5 μ m.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, the minimum range between two adjacent mask windows is 1 μ m ~ 10 μ m.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, described predetermined depth is 100nm ~ 100 μ m.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, in the step 4), the time of anisotropic wet corrosion is 10 minutes ~ 100 hours.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, described hexagonal each interior angle is 120 °, and each limit is all along＜110〉crystal orientation, respectively the sidewall of this etching tank is all { in the 111} family of crystal planes.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, respectively the angle of this monocrystalline silicon thin-walled and described monocrystal silicon substrate upper surface is 69.5 ° ~ 71.5 °.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, respectively the width of this monocrystalline silicon thin-walled is 1nm ~ 999nm, and length is 100nm ~ 1mm, and the width of any two monocrystalline silicon thin-walleds differs and is no more than 500nm.
A kind of preferred version as the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, it is 120 ° hexagon mesh array that a plurality of monocrystalline silicon thin-walleds form angle in twos, and it is 120 ° hexagon mesh array that a plurality of monocrystalline silicon nano lines form angle in twos.
As a kind of preferred version of the preparation method of the monocrystalline silicon nano line mesh array structure in the present embodiment, the end points of three adjacent monocrystalline silicon nano lines is connected in a monocrystalline silicon supporting construction, and the distance between any two ends point is 10nm ~ 20 μ m.
As mentioned above, the invention provides a kind of preparation method of monocrystalline silicon nano line mesh array structure, prior to making anti-oxidant mask on one (111) the crystal face type silicon chip and forming mask window; Then adopt the ICP etching method, monocrystalline silicon is etched to a predetermined depth; Then the monocrystalline silicon of this mask window below is respectively carried out the anisotropic wet corrosion, forming upper and lower surface is hexagonal a plurality of etching tank, forms the monocrystalline silicon thin-walled between the sidewall of adjacent two etching tanks; Then utilize from limiting oxidation technology and carry out thermal oxide, form monocrystalline silicon nano line in described monocrystalline silicon thin-walled center of top zone; Remove at last anti-oxidant mask and silica, form monocrystalline silicon nano line mesh array structure.Technique of the present invention is simply efficient, core procedure only relates to conventional photoetching, etching process, anti-oxidant mask and anisotropic etch, under the mask plate preparation condition and etching condition of routine, crystal face characteristic distributions in (111) the crystal face type of the utilization silicon chip can be made large-scale monocrystalline silicon nano line composite figure at silicon chip.
Description of drawings
Fig. 1 is shown as the preparation method of monocrystalline silicon nano line mesh array structure of the present invention, under the flute profile corrosion window of (111) crystal face type monocrystal silicon substrate certain depth, arbitrary shape, the etching tank floor map that Silicon Crystal Anisotropic Etching forms, the upper and lower surface of etching tank is the hexagon of 120 ° at interior angle, hexagonal every limit is all along＜110〉crystal orientation family, hexagonal sidewall is all { in the 111} family of crystal planes.
Fig. 2 is shown as the preparation method of monocrystalline silicon nano line mesh array structure of the present invention, (111) mutual close a plurality of anisotropic etch groove floor map on the crystal face type monocrystal silicon substrate, adjacent etching tank sidewall forms monocrystalline silicon monocrystalline silicon thin-walled, and each etching tank has at least two adjacent sidewalls to form the monocrystalline silicon thin-walled with the sidewall of adjacent etching tank respectively.
Fig. 3 a ~ Fig. 3 b is shown as the preparation method of monocrystalline silicon nano line mesh array structure of the present invention, and upper surface covers the monocrystalline silicon thin-walled oxidizing process schematic diagram of anti-oxidant mask.When monocrystalline silicon thin-walled upper surface has anti-oxidant mask, after oxidation to a certain degree, volumetric expansion occurs on these monocrystalline silicon thin-walleds because in the oxidizing process cause the inner inhomogeneous stress of size that produces, at stress maximum (being positioned at the thin-walled center of top near the zone of anti-oxidant mask) because oxidation rate is the slowest, when other position complete oxidation of thin-walled was silica, this zone still stayed the less monocrystal silicon structure in cross section.
Fig. 4 is shown as the preparation method of monocrystalline silicon nano line mesh array structure of the present invention, a plurality of monocrystalline silicon thin-walleds are after oxidation, remove the monocrystalline silicon nano line mesh array structural plan schematic diagram that obtains behind the silica of growing in anti-oxidant mask and the oxidizing process, only drawn minimum mesh array unit among the figure, i.e. three structures that monocrystalline silicon nano line links to each other.
Fig. 5 ~ Figure 10 is shown as the structural representation that the preparation method step 1) ~ step 6) of monocrystalline silicon nano line mesh array structure of the present invention presents.
The element numbers explanation
101 monocrystal silicon substrate
102 anti-oxidant masks
103 mask windows
104 flute profile corrosion windows
105 etching tanks
106 monocrystalline silicon thin-walleds
107 monocrystalline silicon nano lines
108 silica
109 supporting constructions
The specific embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by the other different specific embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 1 ~ Figure 10.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
Present embodiment provides a kind of method of monocrystalline silicon nano line mesh array structure to make, the method according to the length of monocrystalline silicon nano line 107 in the aimed single crystal silicon nanowires network structure array, with the distance at 105 ends of etching tank, calculate the form parameter, queueing discipline of default etching mask window 103 arrays and to the degree of depth of monocrystalline silicon ICP etching in the window, thereby control corresponding technological parameter, the monocrystalline silicon nano line network structure array of realize target shape.
Fig. 1 is shown as the monocrystalline anisotropic etch of silicon schematic diagram of (111) crystal face, as shown in the figure, monocrystal silicon substrate 101 surfaces in (111) crystal face type, when the flute profile corrosion window 104 of arbitrary shape, certain depth is arranged, be hexagonal etching tank 105 through forming upper and lower surface after the corrosion of monocrystalline silicon anisotropic, each hexagonal all interior angle is 120 °.Wherein, AB limit, BC limit, CD limit, DE limit, EF limit, FA limit consist of the upper surface hexagon of etching tank 105, A ' B ' limit, B ' C ' limit, C ' D ' limit, D ' E ' limit, E ' F ' limit, F ' A ' consist of the lower surface hexagon of etching tank 105, and these 12 limits are all along＜110〉crystal orientation family.Wherein, the hexagon that surrounds of AB limit, B ' C ' limit, CD limit, D ' E ' limit, EF limit, F ' A ' limit upright projection is 120 ° minimum external hexagon for the interior angle of default arbitrary shape etching tank 105.Six sidewalls of etching tank 105 all in the 111} family of crystal planes, and with the angle theta of upper surface be 70.5 ° ± 1 °.Between AB limit and A ' B ' limit, BC limit and B ' C ' limit, CD limit and C ' D ' limit, DE limit and D ' E ' limit, EF limit and E ' F ' limit, FA limit and the F ' A ' limit at the projector distance d of upper surface
1Identical, and can be calculated as:
d
1＝τ·ctgθ
Wherein, τ is the default corrosion window degree of depth.
When default a plurality of groove shape corrosion window 104 was adjacent to each other, after the corrosion of monocrystalline silicon anisotropic wet, 105 of adjacent etching tanks formed monocrystalline silicon thin-walled 106 by sidewall parallel to each other, and as shown in Figure 2, the width w of monocrystalline silicon thin-walled 106 can be calculated as:
w＝d
0-d
1
Wherein, d
0For adjacent corrosion window planar perpendicular to the minimum range on this thin-walled length direction.
105 at least two adjacent sidewalls of described etching tank simultaneously and form width adjacent to 105 of other two etching tanks of this etching tank 105 and differ at 500nm with interior monocrystalline silicon thin-walled 106.When monocrystalline silicon thin-walled 106 upper surfaces have anti-oxidant mask 102, according to certainly limiting oxidation mechanisms, it is the slowest owing to oxidation rate near the zone of anti-oxidant mask 102 to be positioned at center of top at these monocrystalline silicon thin-walleds 106, when other position complete oxidation of thin-walled is silica 108, this zone still stays the less monocrystal silicon structure in cross section, shown in Fig. 3 a ~ Fig. 3 b.Along thin-walled length direction expansion, these monocrystal silicon structures that stay then form monocrystalline silicon nano line 107, and along its length angle is 120 ° between adjacent nano wire, as shown in Figure 4.If a large amount of described etching tanks 105 is densely arranged with identical rule, then obtain the most at last monocrystalline silicon nano line mesh array structure.
According to above-mentioned design, such as Fig. 1 ~ shown in Figure 10, present embodiment provides a kind of preparation method of monocrystalline silicon nano line mesh array structure, and described preparation method may further comprise the steps at least:
As shown in Figure 5, at first carry out step 1), the monocrystal silicon substrate 101 of one (111) crystal face is provided, make anti-oxidant mask 102 in these monocrystal silicon substrate 101 surfaces.
In the present embodiment, described anti-oxidant mask 102 is that silicon nitride film or the thickness of 10nm ~ 2 μ m is the silica of 100nm ~ 5 μ m for thickness.In a concrete implementation process, adopt the low stress nitride silicon thin film of LPCVD growth, the thickness of described silicon nitride film is 1 μ m.
Such as Fig. 1 and Fig. 6 ~ shown in Figure 8, then carry out step 2) ~ step 4).Step 2), adopt photoetching process in described anti-oxidant mask 102, to form a plurality of mask windows 103 of the default queueing discipline with preset shape; Step 3) adopts the ICP etching method, the monocrystalline silicon of these mask window 103 belows respectively is etched to a predetermined depth forms flute profile corrosion window 104; Step 4) is carried out the anisotropic wet corrosion to the monocrystalline silicon of these mask window 103 belows respectively, and forming upper and lower surface is hexagonal a plurality of etching tank 105, forms monocrystalline silicon thin-walled 106 between the sidewall of adjacent two etching tanks 105;
Step 2 at present embodiment) in,, the minimum range between two adjacent mask windows 103 is 1 μ m ~ 10 μ m.
In the step 3) of present embodiment, described predetermined depth is 100nm ~ 100 μ m.
In the step 4) of present embodiment, adopt the Silicon Crystal Anisotropic Etching solution such as KOH, TMAH to carry out the anisotropic wet corrosion as corrosive liquid, etching time is 10 minutes ~ 100 hours.Each limit of hexagon of gained is all along＜110 after the corrosion〉crystal orientation, respectively the sidewall of this etching tank 105 is all { in the 111} family of crystal planes.Respectively this monocrystalline silicon thin-walled 106 is 69.5 ° ~ 71.5 ° with the angle of described monocrystal silicon substrate 101 upper surfaces.
The width of respectively this monocrystalline silicon thin-walled 106 of step 4) gained is 1nm ~ 999nm, and length is 100nm ~ 1mm, and the width of any two monocrystalline silicon thin-walleds 106 differs and is no more than 500nm.
In the step 4), it is 120 ° hexagon mesh array that a plurality of monocrystalline silicon thin-walleds 106 form angle in twos.
In a concrete implementation process, at first the form parameter of Offered target monocrystalline silicon nano line mesh array structure is as follows: all monocrystalline silicon nano line 107 identical length etc. and length are 100 μ m, and monocrystalline silicon nano line 107 is 10 μ m from the distance of etching tank 105 bottoms.See also Fig. 1, if will satisfy this target, the upper surface of each etching tank 105 should be hexagon, and namely AB limit, BC limit, CD limit, DE limit, EF limit, FA limit surround hexagon, and the length of side is 100 μ m; Projector distance at upper surface between AB limit and A ' B ' limit, BC limit and B ' C ' limit, CD limit and C ' D ' limit, DE limit and D ' E ' limit, EF limit and E ' F ' limit, FA limit and the F ' A ' limit can be calculated as:
d
1＝τ·ctgθ＝10μm·ctg70.5°＝3.54μm，
Thus, can determine etching tank 105 lower surfaces projection of shape and parameter in the plane.The common factor of note hexagon ABCDEF and hexagon A ' B ' C ' D ' E ' F ' projection in the plane is that hexagon abcdef(does not give diagram), then making default etching mask window 103 figures satisfy the minimum external hexagon that its interior angle is 120 ° is hexagon abcdef.
In the present embodiment, described a plurality of mask window 103 carries out array with same shape size and arranges, and after the predetermined depth of mask window 103 shapes and etching tank 105 determines, the shape of hexagon ABCDEF also will be determined, adjust to the position of a plurality of mask windows 103 satisfied: with at least two of any one mask window 103 its relevant hexagon ABCDEF adjacent limits respectively and plane projection parallel with the limit of other two adjacent hexagons ABCDEF apart from w in 10nm ~ 999nm interval, accordingly, can calculate each mask window 103 on perpendicular to the direction on these limits apart from d
0For:
d
0＝w+3.45μm。
Such as Fig. 9 ~ shown in Figure 10, then carry out step 5) ~ step 6).Step 5), utilize from limiting oxidation technology above-mentioned resulting structures is carried out thermal oxide, make the gradually oxidation of described monocrystalline silicon thin-walled 106, form the monocrystalline silicon nano line 107 that extends along monocrystalline silicon thin-walled 106 length directions in described monocrystalline silicon thin-walled 106 center of top zone at last; Step 6) is removed the silica 108 that forms in described anti-oxidant mask 102 and the oxidizing process, forms monocrystalline silicon nano line mesh array structure.
When monocrystalline silicon thin-walled 106 upper surfaces have anti-oxidant mask 102, according to certainly limiting oxidation mechanisms, it is the slowest owing to oxidation rate near the zone of anti-oxidant mask 102 to be positioned at center of top at these monocrystalline silicon thin-walleds 106, when other position complete oxidation of thin-walled is silica 108, this zone still stays the less monocrystal silicon structure in cross section, and this monocrystal silicon structure extends into monocrystalline silicon nano line 107 along monocrystalline silicon thin-walled 106 length directions.Need to prove, be positioned at the monocrystalline silicon in the centre of the junction of this monocrystalline silicon thin-walled 106 respectively because oxidation rate is also slower, so after removing described silica 108, respectively the junction of this monocrystalline silicon nano line 107 can have monocrystalline silicon supporting construction 109, as shown in Figure 4.
In the present embodiment, it is 120 ° hexagon mesh array that a plurality of monocrystalline silicon nano lines 107 form angle in twos, and the end points of three adjacent monocrystalline silicon nano lines 107 is connected in a monocrystalline silicon supporting construction 109, and the distance between any two ends point is 10nm ~ 20 μ m.
In sum, the invention provides a kind of preparation method of monocrystalline silicon nano line mesh array structure, prior to making anti-oxidant mask on one (111) the crystal face type silicon chip and forming mask window; Then adopt the ICP etching method, monocrystalline silicon is etched to a predetermined depth; Then the monocrystalline silicon of this mask window below is respectively carried out the anisotropic wet corrosion, forming upper and lower surface is hexagonal a plurality of etching tank, forms the monocrystalline silicon thin-walled between the sidewall of adjacent two etching tanks; Then utilize from limiting oxidation technology and carry out thermal oxide, form monocrystalline silicon nano line in described monocrystalline silicon thin-walled center of top zone; Remove at last anti-oxidant mask and silica, form monocrystalline silicon nano line mesh array structure.Technique of the present invention is simply efficient, core procedure only relates to conventional photoetching, etching process, anti-oxidant mask and anisotropic etch, under the mask plate preparation condition and etching condition of routine, crystal face characteristic distributions in (111) the crystal face type of the utilization silicon chip can be made large-scale monocrystalline silicon nano line composite figure at silicon chip.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (10)
1. the preparation method of a monocrystalline silicon nano line mesh array structure is characterized in that, described preparation method may further comprise the steps at least:
1) provides the monocrystal silicon substrate of one (111) crystal face, make anti-oxidant mask in this monocrystal silicon substrate surface;
2) adopt photoetching process in described anti-oxidant mask, to form a plurality of mask windows of the default queueing discipline with preset shape;
3) adopt the ICP etching method, the monocrystalline silicon of this mask window below respectively is etched to a predetermined depth;
4) monocrystalline silicon of this mask window below is respectively carried out the anisotropic wet corrosion, forming upper and lower surface is hexagonal a plurality of etching tank, forms the monocrystalline silicon thin-walled between the sidewall of adjacent two etching tanks;
5) employing is carried out thermal oxide from limiting oxidation technology to above-mentioned resulting structures, makes the gradually oxidation of described monocrystalline silicon thin-walled, forms along the monocrystalline silicon nano line of monocrystalline silicon thin-walled length direction extension in described monocrystalline silicon thin-walled center of top zone at last;
6) remove the silica that forms in described anti-oxidant mask and the oxidizing process, form monocrystalline silicon nano line mesh array structure.
2. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1 is characterized in that: described anti-oxidant mask is that thickness is that silicon nitride film or the thickness of 10nm ~ 2 μ m is the silica of 100nm ~ 5 μ m.
3. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1, it is characterized in that: the minimum range between two adjacent mask windows is 1 μ m ~ 10 μ m.
4. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1, it is characterized in that: described predetermined depth is 100nm ~ 100 μ m.
5. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1 is characterized in that: in the step 4), the time of anisotropic wet corrosion is 10 minutes ~ 100 hours.
6. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1, it is characterized in that: described hexagonal each interior angle is 120 °, and each limit is all along＜110〉crystal orientation, respectively the sidewall of this etching tank is all { in the 111} family of crystal planes.
7. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1, it is characterized in that: respectively the angle of this monocrystalline silicon thin-walled and described monocrystal silicon substrate upper surface is 69.5 ° ~ 71.5 °.
8. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1, it is characterized in that: respectively the width of this monocrystalline silicon thin-walled is 1nm ~ 999nm, length is 100nm ~ 1mm, and the width of any two monocrystalline silicon thin-walleds differs and is no more than 500nm.
9. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 1, it is characterized in that: it is 120 ° hexagon mesh array that a plurality of monocrystalline silicon thin-walleds form angle in twos, and it is 120 ° hexagon mesh array that a plurality of monocrystalline silicon nano lines form angle in twos.
10. the preparation method of monocrystalline silicon nano line mesh array structure according to claim 9, it is characterized in that: the end points of three adjacent monocrystalline silicon nano lines is connected in a monocrystalline silicon supporting construction, and the distance between any two ends point is 10nm ~ 20 μ m.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210514737.6A CN102963862B (en) | 2012-12-04 | 2012-12-04 | A kind of preparation method of monocrystalline silicon nano line mesh array structure |
| PCT/CN2013/070357 WO2014086105A1 (en) | 2012-12-04 | 2013-01-11 | Method for manufacturing net-shaped array structure of mono-crystalline silicon nano-wires |
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Cited By (4)
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| CN104049112A (en) * | 2014-06-27 | 2014-09-17 | 中国科学院上海微***与信息技术研究所 | Method for manufacturing silicon nanowire probe structure |
| CN105540531A (en) * | 2015-12-25 | 2016-05-04 | 上海应用技术学院 | Preparation method for mesh silicon nitride film micro-bridge array |
| CN109270082A (en) * | 2018-08-09 | 2019-01-25 | 宁夏中晶半导体材料有限公司 | A method of monocrystalline silicon wafer line is determined using caustic solution and microcosmic detection |
| CN111153379A (en) * | 2018-11-08 | 2020-05-15 | 深圳先进技术研究院 | Method for manufacturing size-controllable nanochannel through angle deposition film |
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| CN1935632A (en) * | 2005-09-22 | 2007-03-28 | 电子部品研究院 | Method of manufacturing a nanowire device |
| CN102040192A (en) * | 2009-10-20 | 2011-05-04 | 中国科学院理化技术研究所 | Method for preparing sequentially arranged bent silicon nano-wire array |
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| CN102800567B (en) * | 2012-08-27 | 2014-09-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | Deep silicon etching method |
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| CN1935632A (en) * | 2005-09-22 | 2007-03-28 | 电子部品研究院 | Method of manufacturing a nanowire device |
| CN102040192A (en) * | 2009-10-20 | 2011-05-04 | 中国科学院理化技术研究所 | Method for preparing sequentially arranged bent silicon nano-wire array |
| CN102398893A (en) * | 2011-09-30 | 2012-04-04 | 中国科学院上海微***与信息技术研究所 | Method for preparing nanometer structures from top to bottom on surfaces of (110) type silicon chips |
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| CN104049112A (en) * | 2014-06-27 | 2014-09-17 | 中国科学院上海微***与信息技术研究所 | Method for manufacturing silicon nanowire probe structure |
| CN105540531A (en) * | 2015-12-25 | 2016-05-04 | 上海应用技术学院 | Preparation method for mesh silicon nitride film micro-bridge array |
| CN109270082A (en) * | 2018-08-09 | 2019-01-25 | 宁夏中晶半导体材料有限公司 | A method of monocrystalline silicon wafer line is determined using caustic solution and microcosmic detection |
| CN111153379A (en) * | 2018-11-08 | 2020-05-15 | 深圳先进技术研究院 | Method for manufacturing size-controllable nanochannel through angle deposition film |
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| WO2014086105A1 (en) | 2014-06-12 |
| CN102963862B (en) | 2015-09-16 |
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