CN102956630B

CN102956630B - Three-dimensionally integrated semiconductor system and the method forming this three-dimensionally integrated semiconductor system

Info

Publication number: CN102956630B
Application number: CN201210282670.8A
Authority: CN
Inventors: 比什-因·阮; 玛丽亚姆·萨达卡
Original assignee: Soitec SA
Current assignee: Sony Semiconductor Solutions Corp
Priority date: 2011-08-09
Filing date: 2012-08-09
Publication date: 2016-06-29
Anticipated expiration: 2032-08-09
Also published as: CN102956630A

Abstract

The present invention relates to three-dimensionally integrated semiconductor system and the method forming this three-dimensionally integrated semiconductor system.Three-dimensionally integrated semiconductor system includes the light-sensitive device being operatively coupled to the current/voltage converter on semiconductor-on-insulator (SeOI) substrate.Optical interconnection is operatively coupled to light-sensitive device.Semiconductor device is engaged with in SeOI substrate, and electric pathway at current/voltage converter and is bonded between the semiconductor device in SeOI substrate and extends.The method forming this system comprises the following steps: forms light-sensitive device in SeOI substrate, and is operatively coupled to waveguide and this light-sensitive device.Current/voltage converter can be formed in SeOI substrate, and light-sensitive device and current/voltage converter can be operatively coupled to each other.Semiconductor device can be bonded in SeOI substrate, and be operatively coupled to current/voltage converter.

Description

Three-dimensionally integrated semiconductor system and the method forming this three-dimensionally integrated semiconductor system

Technical field

It relates to utilize the joint semiconductor structure of three-dimensional (3D) integrated technology, and relate to the joint semiconductor structure formed by this method.More specifically, it relates to include at least one light-sensitive device and at least one of three-dimensionally integrated semiconductor system of semiconductor-on-insulator (SeOI) substrate, and the method relating to forming this three-dimensionally integrated semiconductor system.

Background technology

The three-dimensional (3D) of two or more semiconductor structures is integrated can produce many benefits to microelectronic applications.Such as, the integrated electrical property that can obtain improvement of 3D of micromodule and power consumption, reduce the area of device footprints (footprint) simultaneously." TheHandbookof3DIntegration, " Wiley-VCH(2008 for example, with reference to P.Garrou et al.).(namely semiconductor element (die) is attached to one or more additional semiconductor dies by integrated can the passing through of the 3D of semiconductor structure, tube core is to tube core (D2D)), (namely semiconductor element is attached to one or more semiconductor wafer, tube core is to wafer (D2W)) and semiconductor wafer is attached to one or more additional semiconductor wafer (namely, wafer is to wafer (W2W)), or their combination and occur.

Although three-dimensional integration technology has been applied successfully to electronic integrated circuit, but this area still suffers from the needs to three-dimensionally integrated photonic integrated circuits system and the method forming this system.

Summary of the invention

There is provided present invention, to introduce the selection of design by reduced form.Below, in the detailed description that embodiment of the disclosure embodiment, these designs are described in more detail.Present invention part is not intended to identify key feature or the essential feature of purport required for protection, neither be intended to the scope being used to limit purport required for protection.

In some embodiments, the disclosure includes three-dimensionally integrated semiconductor system.This system includes: semiconductor-on-insulator (SeOI) substrate, and this SeOI substrate includes semiconductor material layer and electrical insulation material layer, and the first type surface of this electrical insulation material layer and semiconductor material layer is disposed adjacently.This system also includes: at least one light-sensitive device, and this at least one light-sensitive device is formed on the semiconductor material layer of SeOI substrate；With at least one optical interconnection, this at least one optical interconnection includes a part for the semiconductor material layer of SeOI substrate.This at least one optical interconnection is operatively coupled to this at least one light-sensitive device.This system also includes: at least one current/voltage converter, and this at least one current/voltage converter is formed on the semiconductor material layer of SeOI substrate.At least one electric pathway extends between at least one light-sensitive device and at least one current/voltage converter.At least one semiconductor device is bonded in SeOI substrate, and at least one electric pathway extends between at least one current/voltage converter and at least one semiconductor device being bonded in SeOI substrate.

In Additional embodiments, the method that the disclosure includes manufacturing this three-dimensionally integrated semiconductor system.Such as, the method manufacturing three-dimensionally integrated semiconductor system may comprise steps of: forms at least one light-sensitive device on the semiconductor material layer of quasiconductor (SeOI) substrate on insulator.Can forming at least one waveguide, this at least one waveguide includes a part for the semiconductor material layer of SeOI substrate.This at least one waveguide can be operatively coupled to at least one light-sensitive device.At least one current/voltage converter can be formed on the semiconductor material layer of SeOI substrate, and this at least one light-sensitive device and this at least one current/voltage converter can be operatively coupled to each other.At least one semiconductor device can be bonded in SeOI substrate, and this at least one current/voltage converter and this at least one semiconductor device being bonded in SeOI substrate can be operatively coupled to each other.

Accompanying drawing explanation

Although this specification terminates with the claims particularly pointing out and being distinctly claimed the content being counted as embodiment of the present invention; but when read in conjunction with the accompanying drawings; the description of the concrete example according to embodiment of this disclosure, the advantage of embodiment of the present disclosure can more easily be determined.Wherein:

Fig. 1 is the cross-sectional side view of the simplification of semiconductor-on-insulator (SeOI) substrate and schematic illustration；

Fig. 2 is the cross-sectional side view of light-sensitive device and the simplification of current/voltage converter and the schematic illustration being illustrated in the SeOI substrate of Fig. 1 to manufacture；

Fig. 3 is the axonometric chart of the simplification of waveguide and schematic illustration, and this waveguide includes a part for the semi-conducting material of the SeOI substrate of Fig. 2；

Fig. 4 is the cross-sectional side view of simplification and the schematic illustration illustrating three-dimensionally integrated semiconductor system, and this three-dimensionally integrated semiconductor system includes multiple semiconductor device that engage in the structure of Fig. 2 and with Fig. 2 structure is operatively coupled to；

Fig. 5 is the cross-sectional side view of simplification and the schematic illustration illustrating another the three-dimensionally integrated semiconductor system similar to the three-dimensionally integrated semiconductor system of Fig. 4, but wherein, a part for SeOI substrate, light-sensitive device, and the structure that current/voltage converter is relative to Fig. 4 is inverted；

Fig. 6 is the cross-sectional side view of simplification and the schematic illustration illustrating another the three-dimensionally integrated semiconductor system similar to the three-dimensionally integrated semiconductor system of Fig. 4, but also includes the additional optical sensing device that manufacture is operatively coupled in SeOI substrate and with the first light-sensitive device；

Fig. 7 is the cross-sectional side view of the simplification of germanium on silicon emitter device and schematic illustration, and it can be adopted to the additional optical sensing device shown in Fig. 6；

Fig. 8 is the cross-sectional side view of simplification and the schematic illustration illustrating another the three-dimensionally integrated semiconductor system similar to the three-dimensionally integrated semiconductor system of Fig. 5, but the additional optical sensing device also including vertically being bonded in the structure of Fig. 5 and being operatively coupled to the first light-sensitive device；

Fig. 9 is the cross-sectional side view of simplification and the schematic illustration illustrating another the three-dimensionally integrated semiconductor system similar to the three-dimensionally integrated semiconductor system of Fig. 8, but also includes the additional optical sensing device that manufacture as shown in Figure 6 is operatively coupled in SeOI substrate and with the first light-sensitive device；And

Figure 10 is the rough schematic view of the three-dimensionally integrated semiconductor system including electromagnetism transceiver.

Detailed description of the invention

Illustration presented herein is not meant as the actual view of any particular semiconductor structure, device, system or method, and the idealization being only used for describing embodiment of the present disclosure represents.

Any title used herein is all not construed as restriction such as the scope of claims below and the embodiment of legal equivalents invention defined thereof.Generally can run through entire disclosure in the design described in any specific title to apply in other parts.

Many lists of references cited herein, its complete disclosure is fully incorporated herein by reference, for all purposes.And, which type of feature herein no matter there is, cited list of references is not recognized as the prior art relative with the present invention of theme claimed herein.

As it is used herein, term " semiconductor structure " means and includes any structure used in the formation of semiconductor device.Semiconductor structure such as includes tube core and wafer (such as, bearing substrate and device substrate), and includes composite construction or the assembly of two or more three-dimensionally integrated each other tube cores and/or wafer.Semiconductor structure also includes the semiconductor structure (that is, semiconductor device) manufactured completely and the intermediate structure formed during manufacturing semiconductor device.

As it is used herein, term " having processed semiconductor structure " means and includes comprising any semiconductor structure of one or more device architecture being at least partially formed.Process the subset that semiconductor structure is semiconductor structure, and all semiconductor structures of having processed have been all semiconductor structures.

As it is used herein, term " joint semiconductor structure " means and includes comprising any structure of two or more semiconductor structures being attached together.Engage the subset that semiconductor structure is semiconductor structure, and all joint semiconductor structures are all semiconductor structures.And, the joint semiconductor structure having processed semiconductor structure including one or more is also processed semiconductor structure.

As used herein, term " device architecture " means and includes processing the following any part of semiconductor structure, this any part as, include or define at least some of to be formed on this semiconductor structure or to be formed in this semiconductor structure of the active of semiconductor device or passive block.Such as, device architecture includes the active of integrated circuit and passive block, such as transistor, transducer, capacitor, resistor, conducting wire, conductive through hole and conductive contact pads.

As it is used herein, term " semiconductor device " means and includes any that process completely and exercisable semiconductor structure, as included semiconductor chip or the encapsulation of operable integrated circuit.Semiconductor device such as includes: E-signal processor (for example, such as laser instrument or other emitter device and electrooptic modulator driver), electronic memory device, and includes the semiconductor device of light-sensitive device.

As it is used herein, term " three-dimensionally integrated semiconductor system " means and includes containing the semiconductor structure of any joint of two or more semiconductor device being operatively coupled to each other.

As it is used herein, term " electric interconnection " means and includes combination in semiconductor structure, at least some of any conductive features by this at least two device architecture electric interconnection or feature by providing current path between at least two device architecture in this semiconductor structure.

As it is used herein, term " through wafer interconnection (throughwaferinterconnect) " or " TWI " mean and include through the first semiconductor structure at least some of that extend, for providing any conductive through hole of structure and/or electric interconnection between the first semiconductor structure and the second semiconductor structure across the interface the first semiconductor structure and the second semiconductor structure.Through wafer is interconnected in this area and also calls with other term, such as " through silicon through hole ", " through substrate through hole ", " through wafer via ", or the writing a Chinese character in simplified form of this term, such as " TSV " or " TWV ".TWI typically generally runs through this semiconductor structure along the direction (that is, along the direction being parallel to " Z " axle) of the first type surface being generally flat being perpendicular to semiconductor structure and extends.The interconnection of through wafer is a kind of type of electric interconnection.

As it is used herein, term " optical interconnection " mean and include in semiconductor structure, between at least two optic structure in this semiconductor structure provide can by any features of the path of one or more wavelength conducting electromagnetic radiation.Although using term " optics ", but one or more wavelength that optical interconnection is used against electromagnetic radiation provides path, these wavelength may be within the visible region of this electromagnetic radiation spectrum or outside (such as, be in the visible region of electromagnetic radiation spectrum and ultrared one or two within).Optical interconnection includes: waveguide, optical through-hole (OV) and through wafer optical through hole (TWOV).

As used herein, term " light-sensitive device " means and includes any such device architecture, and this device architecture is configured in response to applying to launch to the curtage of this device architecture electromagnetic radiation and/or producing curtage in response to electromagnetic radiation impact on this device architecture.Thus, light-sensitive device includes the optical transmitting set of such as light emitting diode, laser instrument etc. and photodetector, solaode, and is configured to detection or receives other device architecture of electromagnetic radiation.

As it is used herein, term " current/voltage converter " means and includes being configured to convert electric current input to voltage signal output to, or voltage input is converted any device of current signal output.Such as, current/voltage converter can include in electrical integrated circuit, be configured to electric current input converts to voltage signal output or converts voltage input to current signal output, multiple device architectures of being operatively coupled to each other, such as transistor, capacitor, and resistor.The current/voltage converter being configured to convert electric current input to voltage signal output is generally referred in the art as " transimpedance amplifier ".

As used herein, term " metal layer " means and includes processing semiconductor structure, this processed semiconductor structure include at least some of conduction electric current along electric pathway following in one or more: conducting wire, conductive through hole and conductive contact pads.

In some embodiments, the disclosure includes three-dimensionally integrated semiconductor system, and this three-dimensionally integrated semiconductor system includes at least one light-sensitive device being operatively coupled to at least one current/voltage converter in SeOI substrate.

Fig. 1 is the simplification cross-sectional side view of the SeOI substrate 100 that can adopt in embodiment of the present disclosure.As it is shown in figure 1, SeOI substrate 100 includes semiconductor material layer 102, and electrically insulating material (that is, the dielectric material) layer 104 being disposed adjacently with the first type surface 103 of semiconductor material layer 102.

In some embodiments, semiconductor material layer 102 can be at least the semi-conducting material of substantially monocrystalline.The unrestriced mode by example, semiconductor material layer 102 can include monocrystal silicon, germanium or IIIV race semi-conducting material, and can be doped or undoped.In Additional embodiments, semi-conducting material 102 can include polycrystalline or non-crystalline material.In some embodiments, semiconductor material layer 102 can include the epitaxial layer of semi-conducting material.And, in some embodiments, semi-conducting material 102 can include the lamination of multiple semiconductor material layer.Including in the embodiment of silicon at semiconductor material layer 102, SeOI substrate 100 can include this area and be referred to as the substrate of " silicon-on-insulator " (SOI) substrate.

Semiconductor material layer 102 can be relatively thin.Such as, in some embodiments, semiconductor material layer 102 can have the average total thickness of the average total thickness of about a micron (1 μm) or less, about 500 nanometers (500nm) or less or the average total thickness of even about 10 nanometers (10nm) or less.

Electrically insulating material 104 such as can include ceramic material, such as nitride (silicon nitride (such as, Si₃N₄)), or oxide (such as, silicon dioxide (SiO₂)) or such as aluminium oxide (Al₂O₃) metal-oxide.In some embodiments, electrically insulating material 104 can include the lamination of these material layers.Including in the embodiment of oxide at electrically insulating material 104, electrical insulation material layer 104 can include this area and be referred to as the layer of " buried oxide layer (BOL) ".

In some embodiments, electrical insulation material layer 104 can have the average total thickness of the average total thickness of about 500 nanometers (500nm) or less, about 200 nanometers (200nm) or less or the average total thickness of even about 20 nanometers (10nm) or less.

Optionally, semiconductor material layer 102 and electrical insulation material layer 104 can be arranged in the substrate 106 of bulk substrate material and be carried by substrate 106.Electrical insulation material layer 104 can be arranged between semiconductor material layer 102 and substrate 106.The unrestriced mode by example, substrate 106 may include that semi-conducting material, any one in the those described above material relevant with semi-conducting material 102；Or insulant, any one in the those described above material relevant with electrically insulating material 104.In some embodiments, substrate 106 can also include multiple structure, and this multiple structure includes two or more different materials.

As a non-limitmg examples, the SeOI substrate 100 shown in Fig. 1 can utilize this area to be referred to as SMART-CUT^TMThe technique of technique is formed.This technique has such as been described in detail in following patent: the U.S. Patent No. RE39 of Bruel, 484(2007 issued February 6), the U.S. Patent No. 6 of Aspar et al., 303, 468(2001 issued October 16), the U.S. Patent No. 6 of Aspar et al., 335, 258(2002 issued January 1), the U.S. Patent No. 6 of Moriceau et al., 756, 286(2004 issued June 29), the U.S. Patent No. 6 of Aspar et al., 809, 044(2004 issued October 26), and the U.S. Patent No. 6 of Aspar et al., 946, 365(2005 JIUYUE is issued on the 20th), disclosure of which is all integrated with by reference in this.

Briefly, it is possible to relatively thick semiconductor material layer is engaged the first type surface 105 to electrical insulation material layer 104.Relatively thick semiconductor material layer can have the composition identical with the composition of the semiconductor material layer 102 being arranged on electrical insulation material layer 104, semiconductor material layer 102 may finally be formed by first type surface 105, the semiconductor material layer relatively thick layer engaged to electrical insulation material layer 104, and includes its relatively thin part.

After by relatively thick semiconductor material layer joint to electrical insulation material layer 104, it is possible to make relatively thick semiconductor material layer thinning, to form the relatively thin semiconductor material layer 102 of Fig. 1.A part for relatively thick semiconductor material layer can be removed from relatively thin semiconductor material layer 102, after on the surface 105 of electrically insulating material 104 remaining relatively thin semiconductor material layer 102.

In order to relatively thin semiconductor material layer 102 is separated with the remainder of relatively thick semiconductor material layer, can along the ion implanting plane with the major surfaces in parallel ground orientation of semiconductor material layer, by different kinds of ions (such as, hydrion, helium ion, or one or more of in inert gas ion) it is injected in relatively thick semiconductor material layer.In some embodiments, semiconductor material layer joint can be injected in this semiconductor material layer by this different kinds of ions to electrical insulation material layer 104 and substrate 106.

Ion can inject along with semiconductor material layer generally perpendicular direction.As it is known in the art, the degree of depth implanted ions in semiconductor material layer is at least partly for the function by the energy in these ion implantings to this semiconductor material layer.In general, will inject with the relatively shallower degree of depth with the ion of relatively low energy injection, and the ion injected with higher-energy will inject with the relatively deep degree of depth.

Ion can be injected in semiconductor material layer with predetermined power, and this predetermined power is selected to inject in this semiconductor material layer to a desired depth ion, and this degree of depth will determine the thickness of semiconductor material layer 102.As known in the art, at least some ion can be injected with other degree of depth except the desired injection degree of depth, and can show with the desired injection degree of depth, the curve being generally bell (symmetrically or non-symmetrically) with maximum as the figure of the ion concentration of the function of the degree of depth in from the surface of semiconductor material layer to this semiconductor material layer.

After implanting ions in semiconductor material layer, these ions can limit the ion implanting plane in this semiconductor material layer.This ion implanting plane can include layer or the region of the planar registration (such as, centered by it) with maximum ion concentration in this semiconductor material layer and this semiconductor material layer.This ion implanting plane can limit the weak area in this semiconductor material layer, and this semiconductor material layer can be rived along this weak area or split in technique subsequently.For example, it is possible to semiconductor material layer is heated, so that this semiconductor material layer is rived along ion implanting plane or splits.Optionally, it is possible to apply mechanical force to semiconductor material layer, so that or helping this semiconductor material layer to rive along ion implanting plane.

In Additional embodiments, can pass through by relatively thick semiconductor material layer (such as, there is the layer of the average thickness more than about 100 microns) engage to electrical insulation material layer 104 and substrate 106, and followed by chemical technology (such as, wet chemical etch or chemical dry etching technics), mechanical technology is (such as, polishing (grinding) or grinding (lapping) technique), or it is by chemically mechanical polishing (chemical-mechanicalpolishing:CMP) technique, this relatively thick semiconductor material layer is thinning from itself and substrate 106 side on the contrary, relatively thin semiconductor material layer 102 is arranged in electrical insulation material layer 104 and substrate 106.

In yet, it is possible to relatively thin semiconductor material layer 102 is formed on the spot above the surface 105 of electrical insulation material layer 104 (such as, on it).Such as, the SeOI substrate 100 of Fig. 1 can be passed through by such as silicon, polysilicon, or the semiconductor material deposition of non-crystalline silicon on the surface 105 of electrical insulation material layer 104 extremely desired thickness formed.It is, for example possible to use plasma enhanced chemical vapor deposition forms relatively thin semiconductor material layer 102.

In some embodiments, it is possible to after relatively thin semiconductor material layer 102 is transferred on electrical insulation material layer 104, the semiconductor material layer 102 that this is relatively thin is thickened.For example, it is possible to grow on the first type surface of the exposure of relatively thin semiconductor material layer 102 or otherwise deposit additional semiconducting material (such as, Si, SiGe, Ge, III-V group semi-conductor material etc.).The final thickness of semiconductor material layer 102 can depend on the lattice mismatch between semiconductor material layer 102 and electrical insulation material layer 104, and will on semiconductor material layer 102 or among the thickness requirement of device that manufactures.

Three-dimensionally integrated system can utilize SeOI substrate 100 to manufacture, as discussed in more detail below.

Fig. 2 is the cross-sectional side view illustrating simplification and the schematic illustration processing semiconductor structure 110, and this has processed at least one light-sensitive device 112 and at least one current/voltage converter 114 that semiconductor structure includes having manufactured in the SeOI substrate 100 of Fig. 1.This light-sensitive device 112 can be formed on the semiconductor material layer 102 of SeOI substrate 100.This current/voltage converter 114 can also be formed in the different range of semiconductor material layer 102 or region of SeOI substrate 100.

In some embodiments, light-sensitive device 112 can include photodetector, and this photodetector is configured to, and generates electric current in response to electromagnetic radiation impact on this photodetector.The electric current generated by this photodetector can be transported to current/voltage converter 114.In Additional embodiments, light-sensitive device 112 can include optical transmitting set, and this optical transmitting set is configured to, and generates ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and the input of this signal of telecommunication can be provided by current/voltage converter 114.Such as, this optical transmitting set can include light emitting diode (LED) or laser device, and this laser device is configured at least launch substantially relevant electromagnetic radiation.

As a non-limitmg examples, light-sensitive device can include photodiode, and this photodiode includes at least one PN junction being configured as photodetector work.As in figure 2 it is shown, photodetector can include the first district 120, this firstth district includes being adulterated by relatively light P the silicon (such as, doped with in boron or gallium one or more of) of (P+).This silicon can include a part for the semiconductor material layer 102 of SeOI substrate 100.One or more electrical contact district 122 of the silicon included by relatively heavy P doping (P++) can be formed in the first district 120.Photodetector can include the second district 124, and this secondth district 124 includes the block intrinsic germanium being arranged in the first district 120 and contacting with the first district 120 direct physical, as shown in Figure 2.It is arranged on second area 124 including adulterate (N++) the 3rd district 126 of (such as, doped with one or more of with in bismuth of nitrogen, phosphorus, arsenic, antimony) of relatively heavy N and contacts with second area 124 direct physical.

The conventional lithographic techniques that photodetector shown in Fig. 2 can utilize field of manufacturing semiconductor devices known manufactures.For example, it is possible to the first type surface of the exposure of semiconductor material layer 102 is applied mask, then mask can be patterned, with the hole that the position that formed wherein with wish to be formed the first district 120 is corresponding.Then, it is possible to by this mask, P-type dopant is utilized gently to be adulterated by the expose portion of semiconductor material layer 102.This mask can be removed, and the second mask can be deposited and the second mask is patterned, so that the second mask includes wishing to form, by it, the hole electrically contacting district 122.Then, by the second mask, additional P-type dopant is utilized to be adulterated further by the expose portion in the first district 120, to form electrical contacts.Then, it is possible to by second mask remove, and can semiconductor material layer 102, photodetector the first district 120 and electrical contact district 122 on dielectric layer 128.Dielectric layer 128 such as can include oxide skin(coating) and/or nitride layer.After dielectric layer 128, it is possible to the first type surface of the exposure of dielectric layer 128 is applied mask, then mask can be patterned, with the hole that the position in the second district 124 formed wherein and wish to be formed photodetector and the 3rd district 126 is corresponding.Dielectric layer 128 can be performed etching by the mask layer of institute's composition, to form recess in this dielectric layer 128.Optionally, it is possible in the first district 120, grow light P doped silicon on the spot, formed in the recess in dielectric layer 128 by etching technics so that the first district 120 is extended to.Then, it is possible in the remainder of the recess being deposited in dielectric layer 128 by intrinsic germanium, which defines the second district 124.For forming the 3rd district 126, then, it is possible to by a part for intrinsic germanium doped with n-type doping agent.

In above-mentioned structure, light-sensitive device 112 can include photodetector, when the electromagnetic radiation of a specific wavelength or multiple wavelength is impacted on the regional of light-sensitive device 112, this photodetector produces electric current between electrical contact district 122 and the 3rd district 126 of light-sensitive device 112, this specific wavelength or multiple wavelength are the functions of the special component of regional, as known in the art.

Above-mentioned structure and manufacturing process for light-sensitive device 112 provide as a non-limitmg examples.Various other type of light-sensitive devices and the manufacturing process being used for being formed these light-sensitive devices are to it known in the art, and can adopt in embodiment of the present disclosure.As another example, in Additional embodiments, light-sensitive device 112 can include germanium on silicon emitter apparatus, as described in referring to Fig. 7.

Manufacturing before light-sensitive device 112, after forming light-sensitive device 112 or can combine at least in part with the manufacture of light-sensitive device 112, manufacture current/voltage converter 114 in the zones of different of semiconductor material layer 102.Many dissimilar and structure current/voltage converter 114 is to it known in the art, and can adopt in embodiment of the present disclosure.These current/voltage converters 114 generally include the multiple transistors, capacitor and the resistor that are operatively coupled to each other, it is configured to convert electric current input to voltage signal output to provide, or voltage input is converted to the circuit (such as, integrated circuit) of current signal output.In some embodiments, as wherein light-sensitive device 112 includes being configured to the embodiment producing the photodetector of electric current in response to electromagnetic radiation impact on light-sensitive device 112, current/voltage converter 114 can include transimpedance amplifier, and this transimpedance amplifier is configured to convert the electric current provided by light-sensitive device 112 input to voltage signal output.

It is that field of semiconductor manufacture is known for manufacturing the technique of each assembly (including transistor, capacitor and resistor) of current/voltage converter 114.And, one or more (channel region such as field-effect transistor) in each assembly of current/voltage converter 114 can include the part of semiconductor material layer 102.

In Additional embodiments, current/voltage converter 114 can be formed in another substrate layer, and this another substrate layer can be stacking and be bonded on semiconductor material layer 102.Form the electric interconnection between conductive features and this current/voltage converter 114 on semiconductor material layer 102 or in semiconductor material layer 102 to be limited by vertically extending conductive through hole and horizontal-extending conductive trace (such as, the conducting wire of redistribution layer (RDL)).

Having processed semiconductor structure 100 and can also include at least one optical interconnection, such as waveguide 116, this optical interconnection includes a part for the semiconductor material layer 102 of SeOI substrate 100.Waveguide 116 can be operatively coupled to light-sensitive device 112, and it is provided in light-sensitive device 112 and includes electromagnetic radiation is delivered to by the embodiment of photodetector light-sensitive device 112, or include the electromagnetic radiation launched by light-sensitive device 112 is carried with away from this light-sensitive device 112 by the embodiment of optical transmitting set at light-sensitive device 112.

Waveguide 116 can include the part of the isolation of semiconductor material layer 102.Fig. 3 is the simplification axonometric chart of a part for the structure 110 of Fig. 2, and this part includes the cross section of waveguide 116.Waveguide 116 can be formed by following technique: removes the part adjacent with the parts transversely being used for limiting and including waveguide 116 of this semiconductor material layer 102 of semiconductor material layer 102, and replaces the removed part of this semiconductor material layer 102 with another material compared with semiconductor material layer 102 with different refractivity.It is, for example possible to use mask and etching technics, to remove the part of semiconductor material layer 102, and formed and recess that waveguide 116 is laterally adjacent.Then, it is possible to by oxide 130 or other dielectric deposition in these recesses, with the restriction of lateral isolation semiconductor material layer 102 part including waveguide 116.

As known in the art, the cross-sectional dimension (such as, the width of waveguide 116 and height) of waveguide 116 can guide and carry the wavelength without notable loss or radiation wavelength by this waveguide 116 by least partially determining together with the composition of waveguide 116 and adjacent material.Thus, it will be considered that the material (such as oxide 130, electrical insulation material layer 104, and dielectric layer 128) that will pass through the wavelength of this waveguide 116 conveying or radiation wavelength and encirclement waveguide 116 selects the particular dimensions of waveguide 116.

Although the axonometric chart according to Fig. 2, waveguide 116 is illustrated as the cross side extending to light-sensitive device 112 in fig. 2, but in Additional embodiments, waveguide 116 extends in the plane of Fig. 2 or extends this plane, and can extend to and contact the center of light-sensitive device 112 between electrical contact district 122.This structure can improve the electromagnetic radiation carried by waveguide 116 and impact the efficiency on the material of light-sensitive material or light-sensitive device 112.

Referring again to Fig. 2, including in the embodiment of photodetector at light-sensitive device 112, electromagnetic radiation can externally enter waveguide 116 from structure 110 simply.Such as, electromagnetic radiation can be impacted at light-sensitive device 112 and/or be configured to carry in the waveguide 116 of electromagnetic radiation to light-sensitive device 112.Light-sensitive device can produce electric current in response to electromagnetic radiation impact thereon.In other embodiments, electromagnetic radiation can enter waveguide 116 from another device coupled optically with waveguide 116, then passes through waveguide 116 and is delivered to light-sensitive device 112.

With reference to Fig. 4, three-dimensionally integrated semiconductor system 140 can be formed in the following manner by the semiconductor structure 110 of Fig. 2: is coupled together electrically and operationally by least one light-sensitive device 112 and at least one current/voltage converter 114, one or more semiconductor device 142A, 142B are bonded in SeOI substrate 100, and are coupled together with one or more semiconductor device 142A, the 142B being bonded in SeOI substrate 100 electrically and operationally by least one current/voltage converter 114.

For example, it is possible to one or more metal layer 144 is formed on dielectric layer 128, light-sensitive device 112 and current/voltage converter 114.These metal layers 144 include multiple conductive features 146.The plurality of conductive features 146 can include one or more in vertically extending conductive through hole, horizontal-extending conductive trace and conductive contact pads.At least some in these conductive features 146 can with character pair portion (such as electrical contact district 122 and the 3rd district 126) electrical contact of light-sensitive device 112.At least some in these conductive features 146 can with the character pair portion of current/voltage converter 114 (such as resistor, capacitor, with the source area of transistor, drain region, and grid structure) electrical contact.These conductive features 146 can be formed by metal and include metal.Said one or more metal layer 144 can be formed by successively technique (layer-by-layerprocess), wherein, depositing, by this mode forming conductive features 146, the metal level and dielectric materials layer that also composition replaces, this conductive features 146 can be embedded in dielectric material 148 and be surrounded by this dielectric material 148.At least one electric pathway that conductive features 146 can be used to form and provide between this at least one light-sensitive device 112 and this at least one current/voltage converter 114 to extend, and be used to form and provide at this at least one current/voltage converter 114 and to be bonded on SeOI substrate 100(on it and define light-sensitive device 112 and current/voltage converter 114) on semiconductor device 142A, 142B between at least one electric pathway that extends.In some embodiments, conductive features 146 can be used to provide between two or more in semiconductor device 142A, 142B extend one or more bar electric pathways so that this semiconductor device 142A, 142B can be coupled to each other electrically and operationally.In this embodiment, two or more in semiconductor device 142A, 142B can not be and directly couple electrically and operationally with current/voltage converter 114.In some embodiments, one or more metal layer 144 can include the layer that this area is referred to as redistribution layer (RDL).

Each in one or more semiconductor device 142A, 142B can include one or more in E-signal processor device, electronic memory device, additional optical sensing device etc..In some embodiments, one or more being bonded in semiconductor device 142A, the 142B in SeOI substrate 100 can include E-signal processor.Such as, the first semiconductor device 142A can include E-signal processor.In this embodiment, the second semiconductor device 142B can also include E-signal processor, or the second semiconductor device 142B can include different types of semiconductor device, such as electronic memory device or additional optical sensing device.

Each in multiple semiconductor device 142A, 142B can such as by by the conductive features structure of the such as bond pad etc on semiconductor device 142A, 142B and be coupled to electrically one or more metal layer 144 such as bond pad etc corresponding conductive features 146, and be bonded in SeOI substrate 100.The conductive features of semiconductor device 142A, 142B can such as utilize conductive projection as known in the art or conducting sphere to engage the conductive features 146 to one or more metal layer 144.In Additional embodiments, the conductive features of semiconductor device 142A, 142B can utilize direct joint technology to engage the conductive features 146 to one or more metal layer 144.

Can classify differently a semiconductor structure is engaged the joining technique used to second half conductor structure, one is whether intermediate layer of material to be arranged between two semiconductor structures they to be bonded together, and the second whether be joint interface allow electronics (that is, electric current) is through this interface.So-called " direct joint method " is to set up direct solid between two semiconductor structures to be bonded to Solid-state Chemistry they to be bonded together, without the method utilizing inter-engagement material they to be bonded together between two semiconductor structures.Have been developed for direct metal to metal bonding method, for the metal material of the surface of the first semiconductor structure being engaged the metal material of the surface to the second semiconductor structure." hot press " method is direct joint method, wherein, with the high temperature of (and generally between about 300 degrees Celsius (300 DEG C) and about 400 degrees Celsius (400 DEG C)) between 200 degrees Celsius (200 DEG C) and about 500 degrees Celsius (500 DEG C), between composition surface, apply pressure.Additional direct joint method can perform with 200 degrees Celsius (200 DEG C) or lower temperature.This direct joint technology performed with 200 degrees Celsius (200 DEG C) or lower temperature is referred to herein as " ultralow temperature (ultra-lowtemperature) " directly joint method.The direct joint method of ultralow temperature can pass through careful surface impurity and the surface compound (such as, native oxide) removed, and is performed by the close contact area increased between two surfaces by atomic scale.Close contact area between two surfaces usually by polishing composition surface reduce the through value close to atomic scale of surface roughness, by applying pressure between composition surface to produce plastic deformation, or by polishing composition surface and apply pressure and realize to obtain this both plastic deformations.

After arranging two surfaces by direct physical contact, engaging ripple (bondingwave) can start and propagate along the interface between these two adjoining surfaces in the interface between two adjoining surfaces.Along with wave surface joint interface between two adjoining surfaces spreads, between the two adjoining surfaces, set up direct chemical bonding by wave surface.The direct joint method of some ultralow temperature can need not execute execution in stressed situation in the joint interface place between composition surface, although in the direct joint method of other ultralow temperature, pressure can be applied in joint interface place between composition surface, in order to realize suitable bond strength at this joint interface place.Between composition surface, execute the direct joint method of stressed ultralow temperature be generally referred in the art as " surface auxiliary engages " or " SAB " method.Thus, as used herein, term " surface auxiliary engage " and " SAB " mean and include by making the first material against the second material, and the first material is bound directly to any direct joint technology of the second material with 200 degrees Celsius (200 DEG C) or lower temperature joint interface place applying pressure between composition surface.

With continued reference to Fig. 4, the conductive features of semiconductor device 142A, 142B can utilize metal to engage the conductive features 146 to one or more metal layer 144 to the direct joint technology of metal (such as thermal compression bonding process or the direct joint technology of ultralow temperature, the direct joint technology of this ultralow temperature can include or can not include surface auxiliary and engage (SAB) technique).

In the three-dimensionally integrated semiconductor system 140 of Fig. 4, at least one light-sensitive device 112 and one or more semiconductor device 142A, the 142B being bonded in SeOI substrate 100 are arranged on the public side of electrical insulation material layer 104 of this SeOI substrate 100.It addition, at least one current/voltage converter 114 is arranged on the same public side of the electrical insulation material layer 104 of SeOI substrate 100, this public side is provided with the side of semiconductor material layer 102, and is the side contrary with substrate 106.But, in Additional embodiments, at least one light-sensitive device 112 and one or more semiconductor device 142A, the 142B being bonded in SeOI substrate 100 can be arranged on the two opposite sides of electrical insulation material layer 104 of this SeOI substrate 100.

Such as, Fig. 5 is exemplified with the Additional embodiments of substantially similar to the three-dimensionally integrated semiconductor system 140 of Fig. 4 three-dimensionally integrated semiconductor system 150, and this three-dimensionally integrated semiconductor system 150 includes: light-sensitive device 112, current/voltage converter 114 and waveguide 116.Three-dimensionally integrated semiconductor system 150 also utilizes the SeOI substrate 100 of Fig. 1 to be formed, and includes semiconductor material layer 102 and electrical insulation material layer 104.But, in the embodiment of Fig. 5, the substrate 106 of SeOI substrate 100 is removed during manufacture.It is inverted from the axonometric chart of Figure 4 and 5, semiconductor material layer 102, electrical insulation material layer 104, light-sensitive device 112, and the three-dimensionally integrated semiconductor system that current/voltage converter 114 is relative to Fig. 4.

As shown in Figure 5, at least one light-sensitive device 112 and one or more semiconductor device 142A, 142B of being bonded in SeOI substrate 100 can be arranged on the contrary both sides of electrical insulation material layer 104 of this SeOI substrate 100, and at least one light-sensitive device 112 and at least one current/voltage converter 114 be arranged on SeOI substrate 100 electrical insulation material layer public side on (Fig. 1).

As it is shown in figure 5, three-dimensionally integrated semiconductor system 150 includes one or more metal layer 144' similar with aforementioned metal layer 144, and include the conductive features 146' being embedded in dielectric material 148' and being surrounded by dielectric material 148'.One or more metal layer 144' is set on the semiconductor material layer 102 on the public side of electrical insulation material layer 104, light-sensitive device 112 and current/voltage converter 114.But, in the embodiment of Fig. 5, from its side on semiconductor material layer 102 (namely through wafer interconnection 152 for will pass through the electric pathway of three-dimensionally integrated semiconductor system 150, from the active side of three-dimensionally integrated semiconductor system 150 or surface) it is transferred to its side (that is, to the dorsal part of three-dimensionally integrated semiconductor system 150) on electrical insulation material layer 104.

One or more additional metallization layers 154 can be formed on the side contrary with one or more metal layer 144' of semiconductor system 150 on electrical insulation material layer 104, three-dimensionally integrated.One or more additional metallization layers 154 can be approximately similar to aforementioned metal layer 144,144', and multiple conductive features 156 can be included, such as horizontal-extending conductive trace, extending vertically conductive through hole and conductive welding disk, these conductive features can be embedded in dielectric material 158 and by dielectric material envelops.In some embodiments, one or more metal layer 154 can include redistribution layer (RDL).

Multiple semiconductor device 142A, 142B, 142C can be engaged to the conductive features 156 of one or more metal layer 154 of (that is, electrical insulation material layer 104 and semiconductor material layer 102 on) (Fig. 1) on the remainder of SeOI substrate 100 and/or dielectric material 158.Each in multiple semiconductor device 142A, 142B, 142C can include previously with reference to one or more in Fig. 4 different types of semiconductor device mentioned.

The conductive features 146' of one or more metal layer 144' may be used for forming or additionally provide at least one electric pathway extended between at least one light-sensitive device 112 and at least one current/voltage converter 114.It addition, the conductive features 146' of one or more metal layer 144', through wafer interconnection 152 and/or the conductive features 156 of one or more metal layer 154 may be used for being formed or additionally providing at least one current/voltage converter 114 and electrical insulation material layer 104 and semiconductor material layer 102(Fig. 1 of being bonded on SeOI substrate 100) on multiple semiconductor device 142A, 142B, 142C in one or more semiconductor device between at least one electric pathway that extends.

For forming the three-dimensionally integrated semiconductor system 150 of Fig. 5, one or more metal layer 144' can be formed on the light-sensitive device 112 processing semiconductor structure 110 of Fig. 2, current/voltage converter 114 and dielectric layer 128.Then, it is possible to bearing substrate (such as, bearing wafer) is bonded on one or more metal layer 144' temporarily, and then, it is possible to substrate 106 is removed from structure 110 at least in part.Then, one or more metal layer 154 can be formed on electrical insulation material layer 104, and through wafer interconnection 152 can run through one or more metal layer 154, electrical insulation material layer 104, semiconductor material layer 102 and one or more metal layer 144' and be formed.Then, it is possible to multiple semiconductor device 142A, 142B, 142C are engaged the conductive features 156 to one or more metal layer 154 and/or dielectric material 158.

In Additional embodiments, the present invention includes such three-dimensionally integrated semiconductor system, i.e. it includes two or more light-sensitive devices being operatively coupled to each other.Such as, this three-dimensionally integrated semiconductor system may include that and is configured at least one optical transmitting set launching electromagnetic radiation, at least one photodetector being configured to receive the electromagnetic radiation launched by optical transmitting set, and couples optical transmitting set and photodetector optically and be configured at least one optical interconnection of the electromagnetic radiation launched by optical transmitting set to photodetector conveying.

Fig. 6 is exemplified with the example of such a embodiment of three-dimensionally integrated semiconductor system 160.The three-dimensionally integrated semiconductor system 160 of Fig. 6 is approximately similar to the three-dimensionally integrated semiconductor system 140 of Fig. 4, and includes being formed the light-sensitive device 112, the current/voltage converter 114 that carry in SeOI substrate 100 and by SeOI substrate 100 and waveguide 116.Three-dimensionally integrated semiconductor system 160 also includes one or more metal layer 144 and multiple semiconductor device 142A, 142B of being bonded in one or more metal layer 144 and SeOI substrate 100.Three-dimensionally integrated semiconductor system 160 also includes the additional optical sensing device 162 operationally coupled with the first light-sensitive device 112.Such as, additional optical sensing device 162 can include optical transmitting set, and this optical transmitting set is configured to launch electromagnetic radiation.Optionally, three-dimensionally integrated semiconductor system 160 can include the manipulator 164 that schematically illustrates and can be used for optionally to modulate the electromagnetic radiation launched by additional optical sensing device 162 in figure 6.Waveguide 166 can extend from additional optical sensing device 162 to manipulator 166, and waveguide 116 can extend from manipulator 166 to the first light-sensitive device 112, and this first light-sensitive device 112 can include the photodetector being configured to receive modulated electromagnetic radiation.Waveguide 166 can include the waveguide that the waveguide 116 of Fig. 3 as previously explained describes.Many different configurations of the photonic modulator that can manufacture in SeOI type of substrate are to it known in the art, and can adopt in embodiment of the present disclosure.

Additional optical sensing device 162 such as can include light emitting diode (LED) or laser device.By the mode of non-limitmg examples, additional optical sensing device 162 can include germanium on silicon (germanium-on-silicon) emitter apparatus 168, as shown in Figure 7.This germanium on silicon emitter apparatus 168 has such as been described in more detail in the following documents: X.Sun et al., OpticsLett.34 (8) the 1198th page (on April 15th, 2009) and X.Sun et al., OpticsLett.34 (9) the 1345th page (on May 1st, 2009), each section in these documents all passes through this and quotes and be wholly incorporated in this.

With reference to Fig. 7, germanium on silicon emitter apparatus 168 can include block P doped silicon 170 and the block N doped germanium 172 being arranged on this P doped silicon 170.P doped silicon 170 can include a part for semiconductor material layer 102 doped with one or more of P-type dopant (such as, doped with in boron and gallium one or more of).Block germanium 172 doped with one or more n-type doping agent (such as, doped with in nitrogen, phosphorus, arsenic, antimony and bismuth one or more of), and can be adulterated on the spot during growing this block germanium 172.

Under the state that block N doped germanium 172 may be at elongation strain.Such as, block germanium 172 may be at from the state of the elongation strain of about 0.20% to about 0.25%.This elongation strain can be passed through under high temperature (elevatedtemperature) with chemical vapor deposition (CVD) technique at P doped silicon 170 Epitaxial growth relaxation state block germanium 172, and cools down this block germanium 172 subsequently and offer this block germanium 172 in.This block germanium 172 can grow by the high temperature (such as, about 650 DEG C) between about 600 DEG C and about 700 DEG C, and can during growth technique complete relaxation.This elongation strain can after deposition, be brought out in this block germanium 172 when this block germanium 172 is cooled to room temperature.Optionally, it is possible to being used for repairing the value of the elongation strain in block germanium 172 by thermal anneal process after growth, it will affect the band gap of block germanium 172.

Dielectric material 174 can be deposited on block germanium 172 and block P doped silicon 170.Dielectric material 174 can include as previously at dielectric material 128 described herein.N DOPOS doped polycrystalline silicon contact portion 176 can be arranged in block N doped germanium 172 and contact with block N doped germanium 172 direct physical.As it is shown in fig. 7, electrical contacts 178 can pass dielectric material 174 extends respectively to N DOPOS doped polycrystalline silicon contact site 176 and block P doped silicon 170, this electrical contacts 178 can include conductive features 146(Fig. 6 of one or more metal layer 144).

In such configuration, by applying voltage between electrical contacts 178, and thus, voltage is applied across the PN junction between block P doped silicon 170 and block N doped germanium 172, germanium on silicon emitter can be made to launch electromagnetic radiation, and the electromagnetic radiation launched can have such as wavelength between about 1560 nanometers and about 1620 nanometers.

In Additional embodiments, three-dimensionally integrated semiconductor system can include additional optical sensing device, this additional optical sensing device is bonded in SeOI substrate 100, and is operatively coupled to the first light-sensitive device 112 formed on the semiconductor material layer 102 of SeOI substrate 100.

Such as, Fig. 8 is exemplified with the three-dimensionally integrated semiconductor system 180 substantially similar with the three-dimensionally integrated semiconductor system 150 of Fig. 5, and this three-dimensionally integrated semiconductor system 180 includes the light-sensitive device 112, current/voltage converter 114 and the waveguide 116 that are arranged on semiconductor material layer 102 and electrical insulation material layer 104.This three-dimensionally integrated semiconductor system 180 also includes the conductive features 146' that one or more metal layer 144', this metal layer 144' include being embedded in dielectric material 148' and being surrounded by dielectric material 148'.From its side on semiconductor material layer 102 (namely through wafer interconnection 152 for will pass through the electric pathway of three-dimensionally integrated semiconductor system 180, from the active side of three-dimensionally integrated semiconductor system 180 or surface) it is transferred to its side (that is, to the dorsal part of three-dimensionally integrated semiconductor system 180) on electrical insulation material layer 104.Can one or more additional metallization layers 154 be formed on electrical insulation material layer 104', and one or more additional metallization layers 154 can include the multiple conductive features 156 being embedded in dielectric material 158 and being surrounded by dielectric material 158, as described previously with reference to described in Fig. 5.Multiple semiconductor device 142A, 142B, 142C can be engaged to the conductive features 156 of one or more metal layer 154 of (Fig. 1) on the remainder of SeOI substrate 100 and/or dielectric material 158.

In the embodiment of Fig. 8, additional semiconductor device 142D is bonded on the remainder (Fig. 1) upper (that is, being bonded on electrical insulation material layer 104 and semiconductor material layer 102) of SeOI substrate 100.This additional semiconductor device 142D includes light-sensitive device.Such as, this additional semiconductor device 142D can include light emitting diode (LED) or laser device.By the mode of non-limitmg examples, additional optical sensing device 162 can include germanium on silicon emitter apparatus 168, as described previously with reference to described in Fig. 7.

(that is, optically) light-sensitive device 142D operationally can couple with the first light-sensitive device 112 formed on the semiconductor material layer 102 of SeOI substrate 100.Such as, additional semiconductor device 142D can include optical transmitting set, and this optical transmitting set is configured to launch electromagnetic radiation.Optionally, this three-dimensionally integrated semiconductor system 180 can include the manipulator (not shown) as the manipulator 164 that previously reference Fig. 6 described, and it may be used for optionally modulating the electromagnetic radiation launched by additional semiconductor device 142D.First light-sensitive device 112 can include photodetector, and this photodetector is configured to receive the electromagnetic radiation launched by the additional semiconductor device 142D including optical transmitting set.

This three-dimensionally integrated semiconductor system 180 also includes multiple optical interconnection, and these optical interconnections are provided between the light-sensitive device of additional semiconductor device 142D and at least one light-sensitive device 112 formed on the semiconductor material layer 102 of SeOI substrate and carry electromagnetic radiation.The plurality of optical interconnection such as can include waveguide 116, and this waveguide 116 includes a part for the semiconductor material layer 102 of SeOI substrate 100, as described previously with reference to described in Fig. 2 and 3.Multiple optical interconnections can include at least one through wafer optical interconnection 182, this through wafer optical interconnection 182, along the direction vertical with semiconductor material layer 102 and electrical insulation material layer 104, perpendicularly extends through the three-dimensionally integrated semiconductor system 180(axonometric chart according to Fig. 8).One end of through wafer optical interconnection 182 can extend to waveguide 116 and be operatively coupled to waveguide 116, and the contrary end of this through wafer optical interconnection 182 can extend to another waveguide 184 and be operatively coupled to another waveguide 184, this another waveguide 184 interconnects 182 light-sensitive devices extending to additional semiconductor device 142D from this through wafer optical, as shown in Figure 8.

Additional waveguide 184 can include a part for additional semiconducting material layer 186.This additional semiconducting material layer 186 can include previously and semiconductor material layer 102 about any material of describing.This additional semiconducting material layer 186 can be formed separately and be transferred to and be deposited on the dielectric material 188 processed on semiconductor device 142A, 142B, 142C, as shown in Figure 8.In Additional embodiments, this additional semiconducting material layer 186 can form (such as, deposition) on the spot on dielectric material 188.

Optionally, additional semiconductor device 142 can be attached dielectric material 190 at least in part and surrounds.And, the additional waveguide 192 including a part for additional semiconducting material layer 186 can extend to another through wafer optical interconnection 194 from additional semiconductor device 142D.This through wafer interconnection 194 may be used on three-dimensionally integrated semiconductor system 180 vertically another additional semiconductor device three-dimensionally integrated, and operationally (such as, optically) couple the light-sensitive device of the light-sensitive device of this additional semiconductor device and the three-dimensionally integrated semiconductor system of Fig. 8.

Fig. 9 is exemplified with the three-dimensionally integrated semiconductor system 195 substantially similar with the three-dimensionally integrated semiconductor system 180 of Fig. 8, and this three-dimensionally integrated semiconductor system 195 includes the light-sensitive device 112, current/voltage converter 114 and the waveguide 116 that are arranged on semiconductor material layer 102 and electrical insulation material layer 104.Three-dimensionally integrated semiconductor system 195 also includes the additional optical sensing device 162 operationally coupled and optional manipulator 164 with the first light-sensitive device 112, as described previously with reference to described in Fig. 6.Such as, additional optical sensing device 162 can include optical transmitting set, and this optical transmitting set is configured to launch electromagnetic radiation.Waveguide 166 can extend from additional optical sensing device 162 to manipulator 166, and waveguide 116 can extend from manipulator 166 to the first light-sensitive device 112, and this first light-sensitive device 112 can include the photodetector being configured to receive modulated electromagnetic radiation.

This three-dimensionally integrated semiconductor system 195 can also include multiple optical interconnection, these optical interconnections are provided between additional optical sensing device 162 and at least one light-sensitive device 112 formed on the semiconductor material layer 102 of SeOI substrate 100 and carry electromagnetic radiation, and carry electromagnetic radiation between additional optical sensing device 162 and other optical module any of three-dimensionally integrated semiconductor system 195.Multiple optical interconnections such as can include waveguide 116, and this waveguide 116 includes a part for the semiconductor material layer 102 of SeOI substrate 100, as described previously with reference to described in Fig. 2 and 3.The plurality of optical interconnection can include at least one through wafer optical interconnection 182, this through wafer optical interconnection 182, along the direction vertical with semiconductor material layer 102 and electrical insulation material layer 104, perpendicularly extends through the three-dimensionally integrated semiconductor system 195(axonometric chart according to Fig. 9).One end of through wafer optical interconnection 182 can extend to waveguide 116 and be operatively coupled to waveguide 116, and the contrary end of this through wafer optical interconnection 182 can be operatively coupled to another waveguide optical device (not shown).

Although non-particular instantiation in these figure schematically illustrated, but the various assemblies of photonic integrated circuits are all known in the art, such as, including toroidal cavity resonator, Mach-Zender(MZ) interferometer, array waveguide grating (AWG) multiplexer and demultiplexer, and delay line.This class component may also be included in that in three-dimensionally integrated semiconductor system described hereinbefore, and can be formed in SeOI substrate 100.And, this class component can utilize optical interconnection as previously described herein to couple optically each other.

Three-dimensionally integrated semiconductor system described hereinbefore can be configured so that any one in much different types of optics or electro-optical system.As non-limitmg examples, these three-dimensionally integrated semiconductor systems can be configured so that and include electromagnetic radiation transmitter and/or electromagnetic radiation receiver, electromagnetic radiation transmitter is configured to export ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and electromagnetic radiation receiver is configured to export the signal of telecommunication in response to ELECTROMAGNETIC RADIATION SIGNATURE input.Thus, in some embodiments, these three-dimensionally integrated semiconductor systems can include electromagnetic radiation transceiver, and this electromagnetic radiation transceiver is configured to export ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and exports the signal of telecommunication in response to ELECTROMAGNETIC RADIATION SIGNATURE input.

Figure 10 is the schematic diagram of the three-dimensionally integrated semiconductor system 200 including electromagnetism transceiver.This transceiver includes electromagnetic radiation transmitter 202 and electromagnetic radiation receiver 208, this electromagnetic radiation transmitter 202 is configured to input 206 in response to the signal of telecommunication and export ELECTROMAGNETIC RADIATION SIGNATURE 204, and this electromagnetic radiation receiver 208 is configured to input 212 in response to ELECTROMAGNETIC RADIATION SIGNATURE and export the signal of telecommunication 210.Thus, this three-dimensionally integrated semiconductor system 200 includes: electric component, and optics and/or photoelectric subassembly, such as aforesaid three-dimensionally integrated semiconductor system.The optics of three-dimensionally integrated semiconductor system 200 and/or photoelectric subassembly are included in those in the frame 214 in Figure 10.Those assemblies outside frame 214 that are in of three-dimensionally integrated semiconductor system 200 are electric components.

As shown in Figure 10, electromagnetic radiation transmitter 202 includes: emitter of electromagnetic radiation 216(is such as, laser instrument), for monitoring the monitoring photodetector 218 of the electromagnetic radiation launched by emitter 216, and for control transmitter 216 operation drive assembly 220(such as, laser driver).Emitter 216, monitoring photodetector 218 and drive assembly 220 can have closed-loop configuration, wherein, waveguide 222 is for carrying, to monitoring photodetector 218, the electromagnetic radiation launched by emitter 216, at least one electric pathway 224 extends between monitoring photodetector 218 and drive assembly 220 and electric coupling monitors photodetector 218 and drive assembly 220, to allow drive assembly 220 to receive input electrical signal (being generated by the monitoring photodetector 218) feature of the electromagnetic radiation launched by emitter 216, and at least one electric pathway 226 extends between drive assembly 220 and emitter 216 and electric coupling drive assembly 220 and emitter 216, to allow the operation of drive assembly 220 control transmitter 216.

Another waveguide 228 extends to electrooptic modulator 230 from emitter 216.This electrooptic modulator may be used for optionally modulating the electromagnetic radiation launched by emitter 216 in response to signal of telecommunication input 206.The operation that another drive assembly 232 may be used for inputting 206 in response to the signal of telecommunication and controls electrooptic modulator 230.Drive assembly 232 may be configured to input 206 radio circuits generating rf signal according to the signal of telecommunication, and this radiofrequency signal to be passed through at least one electric pathway 234 and input to electrooptic modulator 230.

Modulated electromagnetic radiation 230 can be passed through waveguide 236 and carry, and with away from electrooptic modulator 230, this waveguide 236 couples alternately through waveguide fiber coupler 238 and fibre-optic catheter.

Electromagnetic radiation receiver 208 includes the photodetector 242 for receiving and detect ELECTROMAGNETIC RADIATION SIGNATURE input 212.This ELECTROMAGNETIC RADIATION SIGNATURE input 212 can pass through another fibre-optic catheter 244 and waveguide 246 is delivered to photodetector 242, and this another fibre-optic catheter 244 and waveguide 246 can be passed through waveguide fiber coupler 248 and be coupled together.This photodetector 242 can be configured to input 212 impacts thereon in response to ELECTROMAGNETIC RADIATION SIGNATURE and generate electric current.The electric current generated by photodetector 242 can pass through electric pathway 252 and be delivered to current/voltage converter 250.Current/voltage converter 250 can include transimpedance amplifier, and this transimpedance amplifier is configured to generate voltage signal output in response to being generated by photodetector 242 and inputted from the electric current that this photodetector 242 receives by electric pathway 252.This signal of telecommunication output 210 can include the voltage signal generated by current/voltage converter 250.

Any one in previously described three-dimensionally integrated semiconductor system 140,150,160,180 can be configured to include such as Figure 10 three-dimensionally integrated semiconductor system 200 schematically illustrated.

Below, the additional non-limitmg examples embodiment of the present invention is described.

Embodiment 1: a kind of three-dimensionally integrated semiconductor system, this three-dimensionally integrated semiconductor system includes: semiconductor-on-insulator (SeOI) substrate, this semiconductor-on insulator-substrate includes semiconductor material layer, with the first type surface of electrical insulation material layer, this electrical insulation material layer and described semiconductor material layer is disposed adjacently；At least one light-sensitive device, this at least one light-sensitive device is formed on the described semiconductor material layer of SeOI substrate；With at least one optical interconnection, this at least one optical interconnection includes a part for the described semiconductor material layer of SeOI substrate, and this at least one optical interconnection is operatively coupled at least one light-sensitive device described；At least one current/voltage converter, this at least one current/voltage converter is formed on the semiconductor material layer of SeOI substrate；At least one electric pathway extended between at least one light-sensitive device described and at least one current/voltage converter described；At least one semiconductor device, this at least one semiconductor device is bonded in SeOI substrate；And at least one electric pathway extended between at least one current/voltage converter described and at least one semiconductor device described in being bonded in SeOI substrate.

Embodiment 2: the three-dimensionally integrated semiconductor system according to embodiment 1, wherein, at least one light-sensitive device described and at least one semiconductor device described being bonded in SeOI substrate are arranged on the public side of described electrical insulation material layer of SeOI substrate.

Embodiment 3: the three-dimensionally integrated semiconductor system according to embodiment 2, wherein, at least one current/voltage converter described is arranged on the described public side of the described electrical insulation material layer of SeOI substrate.

Embodiment 4: the three-dimensionally integrated semiconductor system according to embodiment 1, wherein, at least one light-sensitive device described and at least one semiconductor device described being bonded in SeOI substrate are arranged on the contrary both sides of described electrical insulation material layer of SeOI substrate.

Embodiment 5: the three-dimensionally integrated semiconductor system according to embodiment 4, wherein, at least one light-sensitive device described and at least one current/voltage converter described are arranged on the public side of described electrical insulation material layer of described SeOI substrate.

Embodiment 6: according to the three-dimensionally integrated semiconductor system that any one in embodiment 1 to 5 is described, wherein, at least one light-sensitive device described includes photodetector, and this photodetector is configured to generate electric current in response to electromagnetic radiation impact on described photodetector.

Embodiment 7: the three-dimensionally integrated semiconductor system according to embodiment 6, wherein, at least one optical interconnection described is configured to be delivered to electromagnetic radiation described photodetector.

Embodiment 8: the three-dimensionally integrated semiconductor system according to embodiment 6, wherein, at least one current/voltage converter described includes transimpedance amplifier.

Embodiment 9: according to the three-dimensionally integrated semiconductor system that any one in embodiment 1 to 8 is described, wherein, at least one light-sensitive device described includes optical transmitting set, this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.

Embodiment 10: the three-dimensionally integrated semiconductor system according to embodiment 9, wherein, at least one optical interconnection described is configured to the electromagnetic radiation that conveying is launched by described optical transmitting set.

Embodiment 11: according to the three-dimensionally integrated semiconductor system described in embodiment 9 or embodiment 10, wherein, described optical transmitting set includes germanium on silicon emitter.

Embodiment 12: according to the three-dimensionally integrated semiconductor system that any one in embodiment 1 to 11 is described, wherein, at least one semiconductor device described being bonded in described SeOI substrate includes E-signal processor.

Embodiment 13: the three-dimensionally integrated semiconductor system according to embodiment 12, wherein, at least one semiconductor device described being bonded in described SeOI substrate includes the multiple semiconductor device being bonded in described SeOI substrate.

Embodiment 14: the three-dimensionally integrated semiconductor system according to embodiment 13, wherein, at least one semiconductor device being bonded in the plurality of semiconductor device in described SeOI substrate includes electronic memory device.

Embodiment 15: according to the three-dimensionally integrated semiconductor system that any one in embodiment 1 to 11 is described, wherein, at least one semiconductor device described being bonded in described SeOI substrate includes the multiple semiconductor device being bonded in described SeOI substrate.

Embodiment 16: the three-dimensionally integrated semiconductor system according to embodiment 15, wherein, at least one semiconductor device being bonded in the plurality of semiconductor device in described SeOI substrate includes additional optical sensing device.

Embodiment 17: the three-dimensionally integrated semiconductor system according to embodiment 16, wherein, described additional optical sensing device operationally with formed on the described semiconductor material layer of described SeOI substrate described at least one light-sensitive device couple.

Embodiment 18: the three-dimensionally integrated semiconductor system according to embodiment 17, described three-dimensionally integrated semiconductor system also includes: multiple optical interconnections, the plurality of optical interconnection is provided in described additional optical sensing device and forms conveying electromagnetic radiation between at least one light-sensitive device described on the described semiconductor material layer of described SeOI substrate, the plurality of optical interconnection includes at least one waveguide, and at least one waveguide described includes the described part of the described semiconductor material layer of described SeOI substrate.

Embodiment 19: the three-dimensionally integrated semiconductor system according to embodiment 18, wherein, the plurality of optical interconnection includes the interconnection of at least one through wafer optical.

Embodiment 20: according to the three-dimensionally integrated semiconductor system that any one in embodiment 17 to 19 is described, wherein, described additional optical sensing device includes optical transmitting set, this optical transmitting set is configured to launch electromagnetic radiation, and forming at least one light-sensitive device described on the described semiconductor material layer of described SeOI substrate and include photodetector, this photodetector is configured to the transmitting of the electromagnetic radiation that detection is launched by described optical transmitting set.

Embodiment 21: the three-dimensionally integrated semiconductor system according to embodiment 20, wherein, described optical transmitting set includes laser device.

Embodiment 22: the three-dimensionally integrated semiconductor system according to embodiment 20, wherein, described optical transmitting set includes germanium on silicon emitter apparatus.

Embodiment 23: according to the three-dimensionally integrated semiconductor system that any one in embodiment 1 to 22 is described, wherein, described three-dimensionally integrated semiconductor system includes electromagnetic radiation transmitter, and this electromagnetic radiation transmitter is configured to export ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.

Embodiment 24: according to the three-dimensionally integrated semiconductor system that any one in embodiment 1 to 22 is described, wherein, described three-dimensionally integrated semiconductor system includes electromagnetic radiation receiver, and this electromagnetic radiation receiver is configured to export the signal of telecommunication in response to ELECTROMAGNETIC RADIATION SIGNATURE input.

Embodiment 25: according to the three-dimensionally integrated semiconductor system described in embodiment 23 or embodiment 24, wherein, described three-dimensionally integrated semiconductor system includes electromagnetic radiation transceiver, this electromagnetic radiation transceiver is configured to export ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and exports the signal of telecommunication in response to ELECTROMAGNETIC RADIATION SIGNATURE input.

Embodiment 26: a kind of method manufacturing three-dimensionally integrated semiconductor system, the method comprises the following steps: form at least one light-sensitive device on the semiconductor material layer of quasiconductor (SeOI) substrate on insulator；Form at least one waveguide of a part for the described semiconductor material layer including described SeOI substrate, and be operatively coupled at least one waveguide described and at least one light-sensitive device described；The described semiconductor material layer of described SeOI substrate is formed at least one current/voltage converter；At least one light-sensitive device described in electric coupling and at least one current/voltage converter described；Described SeOI substrate engages at least one semiconductor device；And at least one current/voltage converter described in electric coupling and at least one semiconductor device described of being bonded in described SeOI substrate.

Embodiment 27: according to the method described in embodiment 26, described method is further comprising the steps of: forms at least one light-sensitive device described on the first side of the electrical insulation material layer of described SeOI substrate, and engages at least one semiconductor device described on described first side of the described electrical insulation material layer of described SeOI substrate.

Embodiment 28: according to the method described in embodiment 27, at least one during described method is further comprising the steps of: form at least one current/voltage converter described on described first side of the described electrical insulation material layer of SeOI substrate, and engage at least one current/voltage converter described on described first side of the described electrical insulation material layer of SeOI substrate.

Embodiment 29: according to the method described in embodiment 26, wherein, the step forming at least one light-sensitive device described includes being formed the step of photodetector, and this photodetector is configured to generate electric current in response to electromagnetic radiation impact on described photodetector.

Embodiment 30: according to the method that any one in embodiment 26 to 29 is described, wherein, the step forming at least one current/voltage converter described includes being formed the step of transimpedance amplifier.

Embodiment 31: according to the method that any one in embodiment 26 to 30 is described, wherein, the step forming at least one light-sensitive device described includes being formed the step of optical transmitting set, and this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.

Embodiment 32: according to the method described in embodiment 31, wherein, the step forming described optical transmitting set includes being formed the step of laser device, and this laser device is configured at least launch substantially relevant electromagnetic radiation in response to the input of the described signal of telecommunication.

Embodiment 33: according to the method described in embodiment 31 or embodiment 32, wherein, the step forming described optical transmitting set includes being formed the step of germanium on silicon emitter.

Embodiment 34: according to the method that any one in embodiment 26 to 33 is described, wherein, the step engaging at least one semiconductor device in described SeOI substrate includes engaging the step of E-signal processor in described SeOI substrate.

Embodiment 35: according to the method that any one in embodiment 26 to 34 is described, wherein, the step engaging at least one semiconductor device in described SeOI substrate is additionally included in the step engaging electronic memory device in described SeOI substrate.

Embodiment 36: according to the method that any one in embodiment 26 to 35 is described, wherein, the step engaging at least one semiconductor device in described SeOI substrate includes engaging the step of multiple semiconductor device in described SeOI substrate.

Embodiment 37: according to the method described in embodiment 36, the step engaging multiple semiconductor device in described SeOI substrate includes arranging the step of additional optical sensing device in described SeOI substrate.

Embodiment 38: according to the method described in embodiment 37, described method is further comprising the steps of: be operatively coupled to described additional optical sensing device and form at least one light-sensitive device described on the described semiconductor material layer of described SeOI substrate.

Embodiment 39: according to the method described in embodiment 37 or embodiment 38, described method is further comprising the steps of: select described additional optical sensing device to include the optical transmitting set being configured to launch electromagnetic radiation, and select to form at least one light-sensitive device described on the described semiconductor material layer of described SeOI substrate, to include the photodetector being configured to the transmitting of the electromagnetic radiation that detection is launched by described optical transmitting set.

Embodiment 40: according to the method described in embodiment 39, described method is further comprising the steps of: select described optical transmitting set, to include germanium on silicon emitter apparatus.

Embodiment 41: according to the method that any one in embodiment 26 to 40 is described, described method is further comprising the steps of: arrange described three-dimensionally integrated semiconductor system, to include at least one in electromagnetic radiation transmitter and electromagnetic radiation receiver, this electromagnetic radiation transmitter is configured to export ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and this electromagnetic radiation receiver is configured to export the signal of telecommunication in response to ELECTROMAGNETIC RADIATION SIGNATURE input.

The scope of the present invention is not limited by the illustrative embodiments of the above-mentioned disclosure, because these embodiments are only the example of embodiments of the present invention, the scope of the present invention limits according to the scope of appended claims and legal equivalents thereof.Any equivalent embodiments is all in the scope of the present invention.It practice, except illustrated and described herein, according to description, the various amendments (the useful combination of the alternative of element as described) of the disclosure will be apparent from for a person skilled in the art.In other words, one or more feature of an illustrative embodiments described herein can be combined with one or more feature of another embodiment embodiment described herein, to provide the Additional embodiments of the disclosure.This amendment and embodiment are also intended to fall in the scope of the appended claims.

Claims

1. the method manufacturing three-dimensionally integrated semiconductor system, the method comprises the following steps:

Forming at least one light-sensitive device on the semiconductor material layer of quasiconductor SeOI substrate on insulator, wherein, this SeOI substrate includes semiconductor material layer and electrical insulation material layer, and the first type surface of this electrical insulation material layer and described semiconductor material layer is disposed adjacently；

Forming at least one waveguide, at least one waveguide described includes a part for the described semiconductor material layer of described SeOI substrate, and is operatively coupled at least one waveguide described and at least one light-sensitive device described；

The described semiconductor material layer of described SeOI substrate is formed at least one current/voltage converter；

At least one light-sensitive device described in electric coupling and at least one current/voltage converter described；

In described SeOI substrate, at least one semiconductor device is engaged by direct joint technology at 500 DEG C or lower temperature, wherein, at least one semiconductor device described and at least one light-sensitive device described are arranged on the public side of described electrical insulation material layer of described SeOI substrate.

2. method according to claim 1, wherein, the step forming at least one current/voltage converter on the described semiconductor material layer of described SeOI substrate includes: form at least one current/voltage converter described in described SeOI substrate, wherein, at least one current/voltage converter described and at least one light-sensitive device described are arranged on the public side of described electrical insulation material layer of described SeOI substrate.

3. the method manufacturing three-dimensionally integrated semiconductor system, the method comprises the following steps:

Arranging semiconductor-on-insulator SeOI substrate, described SeOI substrate includes semiconductor material layer and electrical insulation material layer, and the first type surface of this electrical insulation material layer and described semiconductor material layer is disposed adjacently；

The described semiconductor material layer of described SeOI substrate is formed at least one light-sensitive device；

In described SeOI substrate, at least one semiconductor device is engaged by direct joint technology at 500 DEG C or lower temperature, wherein, at least one semiconductor device described and at least one light-sensitive device described are arranged on the two opposite sides of described electrical insulation material layer of described SeOI substrate；And

At least one current/voltage converter described in electric coupling and at least one semiconductor device described being bonded in described SeOI substrate.

4. method according to claim 3, wherein, forms the step of at least one light-sensitive device and includes being formed the step of photodetector, and this photodetector is configured to generate electric current in response to electromagnetic radiation impact on described photodetector.

5. method according to claim 4, wherein, the step forming at least one current/voltage converter includes being formed the step of transimpedance amplifier.

6. method according to claim 3, wherein, the step forming at least one light-sensitive device includes being formed the step of optical transmitting set, and this optical transmitting set is configured to generate ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input.

7. method according to claim 6, wherein, the step forming optical transmitting set includes being formed the step of laser device, and this laser device is configured to launch at least substantially relevant electromagnetic radiation in response to the input of the described signal of telecommunication.

8. method according to claim 6, wherein, the step forming optical transmitting set includes being formed the step of germanium on silicon emitter.

9. method according to claim 3, wherein, the step engaging at least one semiconductor device in described SeOI substrate includes engaging the step of E-signal processor in described SeOI substrate.

10. method according to claim 9, wherein, the step engaging at least one semiconductor device in described SeOI substrate is additionally included in the step engaging electronic memory device in described SeOI substrate.

11. method according to claim 3, wherein, the step engaging at least one semiconductor device in described SeOI substrate includes engaging the step of multiple semiconductor device in described SeOI substrate.

12. method according to claim 11, the step engaging the plurality of semiconductor device in described SeOI substrate includes arranging the step of additional optical sensing device in described SeOI substrate.

13. method according to claim 12, described method is further comprising the steps of: is operatively coupled to described additional optical sensing device and forms at least one light-sensitive device described on the described semiconductor material layer of SeOI substrate.

14. method according to claim 13, described method is further comprising the steps of: select described additional optical sensing device to include the optical transmitting set being configured to launch electromagnetic radiation, and select to form at least one light-sensitive device described on the described semiconductor material layer of described SeOI substrate, to include photodetector, this photodetector is configured to the transmitting of the electromagnetic radiation that detection is launched by described optical transmitting set.

15. method according to claim 14, described method is further comprising the steps of: select described optical transmitting set, to include germanium on silicon emitter apparatus.

16. method according to claim 3, described method is further comprising the steps of: arrange described three-dimensionally integrated semiconductor system, to include at least one in electromagnetic radiation transmitter and electromagnetic radiation receiver, this electromagnetic radiation transmitter is configured to export ELECTROMAGNETIC RADIATION SIGNATURE in response to signal of telecommunication input, and this electromagnetic radiation receiver is configured to export the signal of telecommunication in response to ELECTROMAGNETIC RADIATION SIGNATURE input.