CN102956496A - Fin type field effect transistor and manufacturing method thereof - Google Patents
Fin type field effect transistor and manufacturing method thereof Download PDFInfo
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- CN102956496A CN102956496A CN2011102522271A CN201110252227A CN102956496A CN 102956496 A CN102956496 A CN 102956496A CN 2011102522271 A CN2011102522271 A CN 2011102522271A CN 201110252227 A CN201110252227 A CN 201110252227A CN 102956496 A CN102956496 A CN 102956496A
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Abstract
The invention relates to a fin type field effect transistor and a manufacturing method thereof. The manufacturing method comprises the steps of: providing a substrate; forming a semiconductor layer and a medium layer sequentially on the substrate; patterning the medium layer to form a first opening; forming a side wall on the side wall of the first opening, wherein the side wall and the bottom of the first opening are encircled to form a second opening; removing the semiconductor layer exposed from the second opening till the substrate is exposed to form a third opening; filling an insulating material in the third opening to form insulating layers; and removing the medium layer and removing the semiconductor layer exposed from the side wall by using the side wall as a mask to form fins. The fin type field effect transistor comprises the substrate, the fins on the substrate, the insulating layers among the fins, and a grid layer covering the fins, the insulating layers and the substrate. According to the fin type field effect transistor and the manufacturing method thereof provided by the invention, damage of the fins is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of manufacture method, fin formula field effect transistor of fin formula field effect transistor.
Background technology
In the evolution of semiconductor very lagre scale integrated circuit (VLSIC), transistor is under the guiding of cmos device scaled (scaling), and density and performance are followed Moore's Law and obtained ensured sustained development and systematization growth.But the characteristic size (CD when device, Critical Dimension) when further descending, even grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also can't satisfy the demand to device performance, and the multiple-grid device is paid close attention to widely as alternative having obtained of conventional device.
Fin formula field effect transistor (FinFET) is a kind of common multiple-grid device, and Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, be formed with outstanding fin 101 on the described Semiconductor substrate 10, fin 101 is generally by to obtaining after Semiconductor substrate 10 etchings; Dielectric layer 11 covers the part of the sidewall of the surface of described Semiconductor substrate 10 and fin 101; Grid layer 12 across on described fin 101, covers top and the sidewall of described fin 101, and grid layer 12 comprises gate dielectric layer (not shown) and the gate electrode (not shown) that is positioned on the gate dielectric layer.For FinFET, the top of fin 101 and the sidewall of both sides and grid layer 12 contacted parts all become channel region, are conducive to increase drive current, improve device performance.In the prior art, the section of grid layer 12 can be various shape, such as ∏ type, Ω type etc.
Fig. 2 to Fig. 7 shows the formation method of a kind of FinFET of prior art.
With reference to figure 2, Semiconductor substrate 20 is provided, be formed with hard mask layer 21 on the Semiconductor substrate 20.Semiconductor substrate 20 generally is silicon substrate, and the material of hard mask layer 21 can be silicon nitride.
With reference to figure 3, hard mask layer 21 is carried out graphically defining the figure of fin.
With reference to figure 4, the hard mask layer 21 after graphical carries out etching as mask to Semiconductor substrate 20, forms the fin 201 that protrudes.
With reference to figure 5, form dielectric layer 22, cover described Semiconductor substrate 20, fin 201 and graphical after hard mask layer 21.The material of dielectric layer 22 generally is silica.
With reference to figure 6, use chemico-mechanical polishing (CMP) that planarization is carried out on the surface of dielectric layer 22, to the hard mask layer 21 that exposes after graphical.
With reference to figure 7, etching remove dielectric layer 22 surface portion and graphical after hard mask layer, expose top and the partial sidewall of fin 201.
Again, can form the grid structure across fin 201, finish the forming process of FinFET device.
But, because height, the larger of width of fin 201 (for example highly are 28nm, width is 12nm), so fin 201 is relatively more fragile, fin 201 sustains damage easily in manufacture process, the fin 201 impaired performances that can affect fin formula field effect transistor for example reduce transistorized operating voltage etc.
And along with the decline of CD size, fin 201 is easier to be impaired, and the yield of fin formula field effect transistor manufacturing process is lower.
Summary of the invention
The technical problem that the present invention solves provides a kind of manufacture method, fin formula field effect transistor of fin formula field effect transistor, to improve the yield of fin formula field effect transistor.
In order to address the above problem, the invention provides a kind of manufacture method of fin formula field effect transistor, comprising: substrate is provided; On substrate, form successively semiconductor layer, dielectric layer; Graphical described dielectric layer forms the first opening; Sidewall at described the first opening forms side wall, and the bottom of described side wall and described the first opening surrounds the second opening; Remove the semiconductor layer that described the second opening exposes until expose substrate, form the 3rd opening; Fill insulant in described the 3rd opening forms insulating barrier; Remove dielectric layer, remove the semiconductor layer that described side wall exposes take described side wall as mask, form fin.
Alternatively, the described step that forms successively semiconductor layer, dielectric layer on substrate also comprises, after forming semiconductor layer, form before the dielectric layer, forms hard mask layer at semiconductor layer; The semiconductor layer that described the second opening of described removal exposes is until expose substrate, and the step that forms the 3rd opening comprises: remove successively hard mask layer that described the second opening exposes, semiconductor layer until expose substrate, form the 3rd opening; Describedly remove the semiconductor layer that described side wall exposes take described side wall as mask, the step that forms fin comprises: remove the hard mask layer that described side wall exposes take described side wall as mask, form hard mask graph, remove the semiconductor layer that described hard mask graph exposes take described hard mask graph as mask, form fin.
Alternatively, also comprise: after forming fin, form the grid layer that covers described fin, insulating barrier and substrate.
Alternatively, after the described step of removing the semiconductor layer that described hard mask graph exposes take described hard mask graph as mask, reduce the horizontal width of remaining semiconductor layer by trim process, form fin.
Alternatively, make the horizontal width of remaining semiconductor layer in the scope of 1～3nm by trim process.
Alternatively, described trim process comprises the horizontal direction etching.
Alternatively, the described step of removing the semiconductor layer that described side wall exposes take described side wall as mask comprises: remove the semiconductor layer that described side wall exposes by etching.
Alternatively, described sidewall at described the first opening step that forms side wall comprises: in the process that forms side wall, also form protective layer at dielectric layer.
Alternatively, the material of described insulating barrier comprises silica.
Alternatively, the material of described hard mask layer comprises polysilicon or amorphous silicon.
Alternatively, the material of described side wall comprises silicon nitride.
Alternatively, the material of described dielectric layer comprises silica.
Alternatively, the horizontal width of described the second opening is in the scope of 1～5nm.
Alternatively, remove the hard mask layer that described side wall exposes take described side wall as mask, forming after the step of hard mask graph, removing the semiconductor layer that described hard mask graph exposes take described hard mask graph as mask, form before the step of fin, also comprise the removal side wall.
Alternatively, after forming fin, also comprise by etching and remove hard mask graph.
Alternatively, the material of described hard mask layer comprises polysilicon or amorphous silicon, and the material of described side wall is silicon nitride, and the step of described removal side wall comprises: remove described side wall by hot phosphoric acid.
Correspondingly, the present invention also provides a kind of fin formula field effect transistor, comprises substrate, at a plurality of fins on the substrate, the insulating barrier between fin, is covered in the grid layer on described fin, insulating barrier and the substrate.
Alternatively, the material of described fin comprises silicon.
Alternatively, the material of described insulating barrier comprises silica.
Alternatively, the horizontal width of described fin is in the scope of 1～3nm.
Alternatively, the horizontal width of described insulating barrier is in the scope of 1～5nm.
Compared with prior art, the present invention has the following advantages:
1. formed the insulating barrier between fin before forming fin, insulating barrier can have certain supporting role to fin, has reduced the probability of fin damaged, and then has improved yield;
2. alternatively, after forming fin, remove hard mask graph by etching, perhaps remove side wall by chemical solution, thereby avoided the impact of the mechanical pressures such as CMP on fin, reduced the probability of fin damaged, further improved yield;
3. alternatively, can obtain the fin of less horizontal width by trim process, when obtaining the small size fin, reduce the impaired problem of fin.
Description of drawings
Fig. 1 is the perspective view of a kind of fin formula field effect transistor of prior art;
Fig. 2 to Fig. 7 shows the formation method of a kind of FinFET of prior art;
Fig. 8 is the schematic flow sheet of fin formula field effect transistor manufacture method one execution mode of the present invention;
Fig. 9 to Figure 19 is the side schematic view of fin formula field effect transistor one embodiment of manufacture method formation of the present invention.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
In order to solve the problems of the prior art, the invention provides a kind of manufacture method of fin formula field effect transistor.With reference to figure 8, show the schematic flow sheet of manufacture method one execution mode of fin formula field effect transistor of the present invention, described method roughly may further comprise the steps:
Step S1 provides substrate, forms successively semiconductor layer, hard mask layer, dielectric layer on substrate;
Step S2 forms the first opening that exposes hard mask layer in dielectric layer;
Step S3 forms side wall at the sidewall of described the first opening, and the hard mask layer that described side wall and described the first opening expose surrounds the second opening;
Step S4 removes the hard mask layer that the second opening exposes until expose semiconductor layer, continues to remove the semiconductor layer that the second opening exposes until expose substrate, forms the 3rd opening;
Step S5, fill insulant in described the 3rd opening forms insulating barrier;
Step S6 removes dielectric layer;
Step S7 removes side wall take side wall as mask and exposes hard mask layer, forms hard mask graph, removes side wall;
Step S8 removes the semiconductor layer that hard mask graph exposes take described hard mask graph as mask, until expose substrate, forms fin;
Step S9 removes hard mask graph.
Below in conjunction with specific embodiment technical solution of the present invention is described further.
To Figure 19, show the side structure schematic diagram of fin formula field effect transistor one embodiment of manufacture method formation of the present invention with reference to figure 9.Present embodiment is take two grid FinFET as example, but the present invention is not restricted to this.
With reference to figure 9, substrate 300 is provided, on substrate 300, form successively semiconductor layer 301, hard mask layer 302, dielectric layer 303;
With reference to Figure 10, in dielectric layer 303, form the first opening 304 that exposes hard mask layer 302; The semiconductor layer 301 corresponding with the position of described the first opening 304 is used to form fin.The material of described hard mask layer 302 is silica, forms described the first opening 304 by doing the quarter method.
With reference to Figure 11, form protective layers 305, form side wall 306 at the sidewall of the first opening 304 at described dielectric layer 303.
Described side wall 306 and hard mask layer 302 surround the second opening 307, described the second opening 307 follow-up the 3rd openings that are used to form the housing insulation material, and then the insulating barrier between two fins of formation FinFET.
Wherein, be positioned at the protective layer 305 on described dielectric layer 303 surfaces; be used as hard mask layer 302, semiconductor layer 301 that follow-up removal the second opening 307 exposes; form the mask graph of the 3rd opening; simultaneously; in follow-up formation the 3rd opening step, can also play the effect of protective dielectric layer 303, side wall 306.
Described side wall 306 is positioned on the sidewall of the first opening 304, the horizontal breadth that the horizontal width of the first opening 304 deducts described side wall 306 is the horizontal width of the second opening 307, and the horizontal width of the second opening 307 determines the horizontal width of the insulating barrier of follow-up formation, the horizontal width of described insulating barrier equals the spacing of two fins, therefore, in the practical application, can deduct according to the horizontal width of the first opening 304 spacing of the fin of FinFET, to obtain the thickness of side wall 306 horizontal directions.
Need to prove, the side wall 306 that is positioned on described the first opening 304 sidewalls can make the horizontal width of the second opening 307 accomplish very little, for example the horizontal width of the second opening 304 is in the scope of 1～5nm, thereby the horizontal width of insulating barrier that makes follow-up formation is in the scope of 1～5nm.
Need to prove; can be on the first opening 304 bottoms, sidewall and dielectric layer 301 the deposition medium material, the side wall 306 that the dielectric layer material of selective etch the first opening 304 bottoms and forming is positioned on the first opening 304 sidewalls, be positioned at the protective layer 305 on the dielectric layer 303.Side wall 306 is identical with the material of protective layer 305 like this, and for example the material of side wall 306 and protective layer 305 is silicon nitride.But the present invention is not restricted to this, and the material of described side wall 306 and protective layer 305 can also be different.
With reference to Figure 12, remove hard mask layer 302 that the second opening 307 exposes until expose semiconductor layer 301, the semiconductor layer 301 that continuation removal the second opening 307 exposes is until expose substrate 300, form the 3rd opening 308, described the 3rd opening 308 is used for the housing insulation material to form the insulating barrier between two fins of FinFET, in the present embodiment, remove successively hard mask layer 302, the semiconductor layer 301 that the second opening 307 exposes by doing the quarter method.
With reference to Figure 13, fill insulant in described the 3rd opening 308, when having filled unnecessary insulating material, remove unnecessary insulating material, particularly, can pass through flatening process (for example CMP) or pass through back to carve the unnecessary insulating material of (etch back) technique removal, to form insulating barrier 309.
Described insulating barrier 309 is used for insulation, the different fin of isolation, and in the present embodiment, the material of described insulating barrier 309 is silica.
Need to prove, in removing unnecessary insulating material process, can also remove protective layer 305.
With reference to Figure 14, remove dielectric layer 303 by returning carving technology, thereby expose hard mask layer 302, and keep the side wall 306 that is positioned on the hard mask layer 302;
Need to prove in the process of removing dielectric layer 303 and also can remove partial insulative layer 309, in the present embodiment, the thickness of the insulating barrier 309 of removal is identical with the thickness of dielectric layer 303.
With reference to Figure 15, take described side wall 306 as mask, remove the hard mask layer 302 that side wall 306 exposes, form hard mask graph 310, described hard mask graph 310 is as the mask graph of follow-up formation fin.Particularly, the hard mask layer 302 that exposes by doing method removal at quarter side wall 306.
After forming hard mask graph 310, remove side wall 306, the material of described side wall 306 is silicon nitride, can remove described side wall 306 by hot phosphoric acid solution.
With reference to Figure 16, remove the semiconductor layer 301 that hard mask graph 310 exposes take described hard mask graph 310 as mask, until expose substrate 300, form fin 311, in the present embodiment, the material of described semiconductor layer 301 is silicon, can remove the semiconductor layer 301 that hard mask graph 310 exposes by etching method.
Preferably, with reference to Figure 17, removing semiconductor layer 301 take described hard mask graph 310 as mask, until expose after the substrate 300, can also carry out horizontal etching to remaining semiconductor layer 301 by trim process (trimming), to reduce the horizontal width of remaining semiconductor layer 301, with formation fin 311, thereby obtain the less fin 311 of size.Particularly, can obtain horizontal width by trim process is fin 311 in 1～3nm scope.
With reference to Figure 18, execution in step S9 removes hard mask graph 310 by doing the quarter method, also can remove partial insulative layer 309 in the process of removing hard mask graph 310, and residue insulating barrier 309 is used for making insulation between the fin 311, isolation.
With reference to Figure 19, the manufacture method of fin formula field effect transistor of the present invention also is included in selectivity deposited semiconductor material on fin 311 and the residue insulating barrier 309, forms grid layer 312.
Two fins 311, at the residue insulating barrier 309 between two fins 311, be covered in the grid structure that grid layer 312 on fin and the residue insulating barrier 309 consists of fin formula field effect transistors.
Need to prove, in other embodiments, can also be to be formed at side wall 306 in the dielectric layer 303 as mask graph semiconductor layer 301, to form fin 311, the present invention does not limit this.
Particularly, form semiconductor layer 301, dielectric layer 303 (need not to form the hard mask layer 302 between semiconductor layer 301 and dielectric layer 303) at substrate 300; Graphical described dielectric layer 303 forms the first opening 304; Sidewall at described the first opening 304 forms side wall 306, and the bottom of described side wall 306 and described the first opening 304 surrounds the second opening 307; Remove the semiconductor layer 301 that described the second opening 307 exposes until expose substrate 300, form the 3rd opening 308; Fill insulant in described the 3rd opening 308 forms insulating barrier 309; Remove dielectric layer 303 and keep side wall 306, remove the semiconductor layer 301 that described side wall 306 exposes take described side wall 306 as mask, form fin 311.
In the embodiment of above-mentioned manufacture method, before forming fin 311, form the insulating barrier 309 between fin 311, insulating barrier 309 can have certain supporting role to fin 311, has reduced the probability of fin 311 damaged, has improved yield;
In addition, after forming fin 311, remove hard mask graph 310 by etching, perhaps remove side wall 306 by chemical solution, thereby avoided the impact of the mechanical pressures such as CMP on fin, reduced the probability of fin 311 damaged, further improved yield;
Can obtain the fin 311 of less horizontal width by trim process, when obtaining small size fin 311, reduce fin 311 impaired problems.
Correspondingly, the present invention also provides a kind of fin formula field effect transistor, continuation is with reference to Figure 19, described fin formula field effect transistor comprises: substrate 300, at two fins 311 on the substrate 300, the insulating barrier 309 between fin 311, described insulating barrier 309 and described fin 311 are contour, are covered in the grid layer 312 on described fin 311, insulating barrier 309 and the substrate 300.
Wherein, substrate 300 can be silica, silicon or silicon-on-insulator (SOI);
The material of fin 311 is silicon, and the horizontal width of fin 311 is in the scope of 1～3nm;
The material of described insulating barrier 309 is silica, and horizontal width is in the scope of 1～5nm.
The material of described grid layer 312 comprises silicon, and described insulating barrier 309 comprises silica.
Need to prove above-described embodiment take bigrid FinFET as example, but the present invention being not restricted to this, can also be three grid FinFET, or other multiple-grid utmost points FinFET, and those skilled in the art can correspondingly revise, are out of shape and replace.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (21)
1. the manufacture method of a fin formula field effect transistor is characterized in that, comprising: substrate is provided; On substrate, form successively semiconductor layer, dielectric layer; Graphical described dielectric layer forms the first opening; Sidewall at described the first opening forms side wall, and the bottom of described side wall and described the first opening surrounds the second opening; Remove the semiconductor layer that described the second opening exposes until expose substrate, form the 3rd opening; Fill insulant in described the 3rd opening forms insulating barrier; Remove dielectric layer, remove the semiconductor layer that described side wall exposes take described side wall as mask, form fin.
2. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that,
Described step forming successively semiconductor layer, dielectric layer on the substrate also comprises: after forming semiconductor layer, form before the dielectric layer, form hard mask layer at semiconductor layer;
The semiconductor layer that described the second opening of described removal exposes is until expose substrate, and the step that forms the 3rd opening comprises: remove successively hard mask layer that described the second opening exposes, semiconductor layer until expose substrate, form the 3rd opening;
Describedly remove the semiconductor layer that described side wall exposes take described side wall as mask, the step that forms fin comprises: remove the hard mask layer that described side wall exposes take described side wall as mask, form hard mask graph, remove the semiconductor layer that described hard mask graph exposes take described hard mask graph as mask, form fin.
3. the manufacture method of fin formula field effect transistor as claimed in claim 2 is characterized in that, also comprises: after forming fin, form the grid layer that covers described fin, insulating barrier and substrate.
4. the manufacture method of fin formula field effect transistor as claimed in claim 2, it is characterized in that, after the described step of removing the semiconductor layer that described hard mask graph exposes take described hard mask graph as mask, reduce the horizontal width of remaining semiconductor layer by trim process, form fin.
5. the manufacture method of fin formula field effect transistor as claimed in claim 4 is characterized in that, makes the horizontal width of remaining semiconductor layer in the scope of 1～3nm by trim process.
6. the manufacture method of fin formula field effect transistor as claimed in claim 4 is characterized in that, described trim process comprises the horizontal direction etching.
7. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the described step of removing the semiconductor layer that described side wall exposes take described side wall as mask comprises: remove the semiconductor layer that described side wall exposes by etching.
8. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the step that described sidewall at described the first opening forms side wall comprises: forming in the process of side wall, also forming protective layer at dielectric layer.
9. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the material of described insulating barrier comprises silica.
10. the manufacture method of fin formula field effect transistor as claimed in claim 2 is characterized in that, the material of described hard mask layer comprises polysilicon or amorphous silicon.
11. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the material of described side wall comprises silicon nitride.
12. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the material of described dielectric layer comprises silica.
13. the manufacture method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the horizontal width of described the second opening is in the scope of 1～5nm.
14. the manufacture method of fin formula field effect transistor as claimed in claim 2, it is characterized in that, removing the hard mask layer that described side wall exposes take described side wall as mask, form after the step of hard mask graph, removing the semiconductor layer that described hard mask graph exposes take described hard mask graph as mask, form before the step of fin, also comprise the removal side wall.
15. the manufacture method of fin formula field effect transistor as claimed in claim 14 is characterized in that, after forming fin, also comprises by etching and removes described hard mask graph.
16. the manufacture method of fin formula field effect transistor as claimed in claim 14, it is characterized in that, the material of described hard mask layer comprises polysilicon or amorphous silicon, and the material of described side wall is silicon nitride, and the step of described removal side wall comprises: remove described side wall by hot phosphoric acid.
17. a fin formula field effect transistor is characterized in that, comprises substrate, at a plurality of fins on the substrate, the insulating barrier between fin, is covered in the grid layer on described fin, insulating barrier and the substrate.
18. fin formula field effect transistor as claimed in claim 17 is characterized in that, the material of described fin comprises silicon.
19. fin formula field effect transistor as claimed in claim 17 is characterized in that, the material of described insulating barrier comprises silica.
20. fin formula field effect transistor as claimed in claim 17 is characterized in that, the horizontal width of described fin is in the scope of 1～3nm.
21. fin formula field effect transistor as claimed in claim 17 is characterized in that, the horizontal width of described insulating barrier is in the scope of 1～5nm.
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| CN201110252227.1A CN102956496B (en) | 2011-08-30 | 2011-08-30 | Fin type field effect transistor and manufacturing method thereof |
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| CN201110252227.1A CN102956496B (en) | 2011-08-30 | 2011-08-30 | Fin type field effect transistor and manufacturing method thereof |
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| CN104078332A (en) * | 2013-03-26 | 2014-10-01 | 中国科学院微电子研究所 | Manufacturing method of fin |
| WO2015032279A1 (en) * | 2013-09-04 | 2015-03-12 | International Business Machines Corporation | Trench sidewall protection for selective epitaxial semiconductor material formation |
| CN105390399A (en) * | 2014-08-25 | 2016-03-09 | 三星电子株式会社 | Semiconductor device and method of fabricating same |
| CN106935506A (en) * | 2015-12-31 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
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| US20040262676A1 (en) * | 2003-06-30 | 2004-12-30 | Deok-Hyung Lee | Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers and devices related thereto |
| CN1925119A (en) * | 2005-08-30 | 2007-03-07 | 三星电子株式会社 | Method of fabricating a semiconductor device |
| CN101183678A (en) * | 2006-11-15 | 2008-05-21 | 三星电子株式会社 | Fin-fet device with a void between pairs of fins and method of manufacturing the same |
| WO2010123750A1 (en) * | 2009-04-21 | 2010-10-28 | International Business Machines Corporation | Multiple vt field-effect transistor devices |
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| US20040262676A1 (en) * | 2003-06-30 | 2004-12-30 | Deok-Hyung Lee | Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers and devices related thereto |
| CN1925119A (en) * | 2005-08-30 | 2007-03-07 | 三星电子株式会社 | Method of fabricating a semiconductor device |
| CN101183678A (en) * | 2006-11-15 | 2008-05-21 | 三星电子株式会社 | Fin-fet device with a void between pairs of fins and method of manufacturing the same |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104078332A (en) * | 2013-03-26 | 2014-10-01 | 中国科学院微电子研究所 | Manufacturing method of fin |
| WO2014153799A1 (en) * | 2013-03-26 | 2014-10-02 | 中国科学院微电子研究所 | Fin manufacturing method |
| WO2015032279A1 (en) * | 2013-09-04 | 2015-03-12 | International Business Machines Corporation | Trench sidewall protection for selective epitaxial semiconductor material formation |
| US9252014B2 (en) | 2013-09-04 | 2016-02-02 | Globalfoundries Inc. | Trench sidewall protection for selective epitaxial semiconductor material formation |
| US9269575B2 (en) | 2013-09-04 | 2016-02-23 | Globalfoundries Inc. | Trench sidewall protection for selective epitaxial semiconductor material formation |
| CN105390399A (en) * | 2014-08-25 | 2016-03-09 | 三星电子株式会社 | Semiconductor device and method of fabricating same |
| CN105390399B (en) * | 2014-08-25 | 2020-08-28 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN106935506A (en) * | 2015-12-31 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
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| CN102956496B (en) | 2015-06-03 |
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