CN102948060B - For the integrated circuit utilizing the lead-edge-blanking equipment of current signal to control the switch of current path - Google Patents
For the integrated circuit utilizing the lead-edge-blanking equipment of current signal to control the switch of current path Download PDFInfo
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- CN102948060B CN102948060B CN201180030370.4A CN201180030370A CN102948060B CN 102948060 B CN102948060 B CN 102948060B CN 201180030370 A CN201180030370 A CN 201180030370A CN 102948060 B CN102948060 B CN 102948060B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33538—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type
- H02M3/33546—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current
- H02M3/33553—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current with galvanic isolation between input and output of both the power stage and the feedback loop
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Electronic Switches (AREA)
Abstract
Describe a kind of integral control circuit of switch, this integral control circuit is suitable for disconnecting or closed path path; Described integrated circuit comprises the comparator that the secondary signal for the electric current of described current path is flow through in the first signal and representative compares.Comparator is according to described secondary signal whether the 3rd variable signal between low logic level and high logic level lower than described first signal or phase reinfusion; Integrated circuit has for continuing first blanking time section and second blanking period for driving the driver of the signal of described switch and being configured to the spike detected on the forward position of described secondary signal with the 3rd signal described in blanking in response to the 3rd signal generation, first blanking time section depends on the switch on delay of described switch, and the second blanking period depends on the duration of the described spike on the forward position of described secondary signal.
Description
Technical field
Present disclosure relates to a kind of integral control circuit utilizing the switch for current path of the lead-edge-blanking equipment of current signal.
Background technology
In switching converter other circuit with utilization power switched transistor, the operation of circuit often depends on the electric current flowing through described transistor.
Such as, be called in the switching converter of the control model of " peak current pattern " or " current programming mode " in use, the connection of power transistor is controlled by clock signal (this clock signal such as generated by local oscillator or relevant with the particular event in power circuit), and cut-off depends on that the electric current flowing through described transistor reaches threshold level.In addition, if the electric current that most switching converter has through power transistor is excessive, "off" transistor is to avoid the protective circuit damaging transducer.Such as Fig. 1 shows the circuit block diagram of the typical commercial integral control circuit of the peak current mode type comprised in typical converter.Figure 2 illustrates the example waveforms of the control circuit of Fig. 1.Integral control circuit 1 is suitable for the gate terminal controlling the transistor MOSM1 that electric current I p flows through.Integral control circuit 1 receives the current signal I that feedback block 2 generates
f.Electric current I
fit is the function of output voltage Vout.Electric current I is drawn from the input of integral control circuit 1
fthus generated error signal Ve.Inverting terminal to PWM comparator 4 applies error signal Ve, and this PWM comparator has the voltage Vcs that electric current I p is formed at the resistance Rs two ends be connected between the source electrode of transistor M1 and ground connection GND in noninverting input.The output of comparator 4 is replacement input R of PWM latch 5, and this PWM latch has clock signal C LOCK arranging on input S.The output Q of PWM latch is connected to the input of driver 6, this driver gate terminal of signal G driving transistors M1.Vdrain is the voltage between the drain terminal and ground connection GND of transistor M1; Is is the electric current flowed on the secondary side of the transformer, and the electric current I p flowing through M1 flows through transformer primary.
Be positioned over the source terminal of M1 and the level conversion of described electric current I p become with the resistor Rs between ground connection GND the voltage signal Vcs provided to the control in Fig. 1 and/or protective circuit.
Summary of the invention
In one embodiment, a kind of integrated circuit of switch for utilizing the equipment for the forward position of blanking current signal to control current path contributes to the duration of blanking period to be set to the ideal needs of circuit close.
In one embodiment, a kind of integrated circuit for controlling the switch being suitable for disconnection or closed path path comprises: comparison means, the secondary signal be suitable for the electric current of described current path is flow through in the first signal and representative compares, and whether described comparison means is suitable for according to described secondary signal lower than described first signal or the 3rd variable signal that exports on the contrary between low logic level and high logic level.Described integral control circuit comprises: first device, be suitable for exporting for closed or disconnect the drive singal of described switch in response to described 3rd signal, it is characterized in that it comprises: the second device, be configured to detect spike on the forward position of described secondary signal and described in blanking, the 3rd signal continues the first blanking time and the second blanking time, first blanking time depended on the switch on delay of described switch, and the second blanking time depended on spike and exceedes described first signal and how long have.
In one embodiment, a kind of integrated circuit comprises: comparator, the secondary signal be configured to the electric current of current path is flow through in the first signal and representative compares, and exports the 3rd signal variable between low logic level and high logic level based on the comparison; Driver-level, is configured to based on described 3rd signal output drive signal and is configured to be coupled to the switch of current path; And blanking apparatus, to be coupled between comparator and driver-level and to be configured to: sheltering the 3rd signal when switching cycle starts and continue first time period; Based on the spike on the forward position of secondary signal described in the 3rd input; And optionally shelter described 3rd signal when spike being detected and continued for the second time period.In one embodiment, shelter described 3rd signal when blanking apparatus is configured to the spike on the forward position that described blanking apparatus detects described secondary signal in first time period and continued for the second time period.In one embodiment, blanking apparatus is configured to described 3rd signal in described first time period when low logic level rises to high logic level, detects the spike the forward position of described secondary signal.In one embodiment, described switch is power transistor.In one embodiment, blanking apparatus is configured to make the multiple time periods of sheltering the 3rd signal in each switching cycle be limited to first time period and the second time period.In one embodiment, described first time period has the duration based on estimating maximum switch on delay.In one embodiment, the duration that duration with the spike detected described second time period is given.In one embodiment, blanking apparatus is configured in response to clock signal to start first time period.In one embodiment, described second time period has the maximum duration equal with first time period.In one embodiment, blanking apparatus comprises: arrange replacement trigger, is configured to arranging the described clock signal of input reception; AND door, is configured to receive from arranging the output and described 3rd signal that reset trigger; OR door, is configured to receive described clock signal and the output from AND door; And can the monostable device of flip-over type again, be coupled to the output of OR door and be configured in each switching cycle, trigger first time period and optionally triggered for the second time period.In one embodiment, blanking apparatus comprises: non-can the first monostable device of flip-over type again, be configured to trigger first time period; And non-can the second monostable device of flip-over type again, be configured to triggering second time period, described first time period has the duration different from the duration of described second time period.In one embodiment, blanking apparatus be configured to described drive singal have just along time trigger described first time period.In one embodiment, blanking apparatus comprises: AND door, be configured to receive from non-can the negate of the output of the first monostable device of flip-over type and described 3rd signal again, wherein the first monostable device be configured in response to described drive singal just along and activate, and non-can the second monostable device of flip-over type be again configured in response to AND door output just along and activate; And control logic, be configured to receive from non-can again flip-over type the first monostable device and from non-can the signal that exports of the second monostable device of flip-over type again and generate sheltering of the 3rd signal each switching cycle based on the output signal of the first monostable device and the second monostable device.In one embodiment, control logic is configured to reception the 3rd signal and generates sheltering of the 3rd signal based on the output signal of the first monostable device, the output of the second monostable device and the 3rd signal.In one embodiment, the second time period had the duration of the estimation maximum duration based on spike.In one embodiment, first time period has the fixing duration of estimation maximum duration based on section turn-on time, and the second time period had the duration substantially equal with the duration of the spike detected.In an embodiment, the first and second time periods are overlapping.In one embodiment, switch is the power transistor of the power switched supply with input voltage and output voltage, the electric current of described current path and the input voltage of rectification proportional, and described first signal and the error voltage between reference voltage and the feedback voltage representing output voltage proportional.
In one embodiment, a kind of system comprises: rectifier, is configured to rectification AC signal; Power transistor, is configured to disconnect and the closed current path being coupled to rectifier; Export; And controller, controller comprises: comparator, and the secondary signal be configured to the electric current of current path is flow through in the first signal of the voltage error of representative output and representative compares, and generates the 3rd signal with logic level based on the comparison; Driver-level, is configured to based on the drive singal of described 3rd signal output for power transistor; And blanking apparatus, to be coupled between comparator and driver-level and to be configured to: sheltering the 3rd signal when switching cycle starts and continue first time period; Based on the spike on the forward position of secondary signal described in the 3rd input; And optionally shelter described 3rd signal when spike being detected and continued for the second time period.In one embodiment, described first time period has longer fixing duration estimation maximum turn-on time of specific power transistor.In one embodiment, the second time period had by the duration of the spike the detected given duration.
In one embodiment, a kind of equipment comprises: for being compared with secondary signal by the first signal and generating the device of logical signal based on the comparison, secondary signal representative is through the electric current of current path; For the device of the switch at least part of logic-based signal drive current path; And for the device of masking logic signal, be coupled in device for comparing and between the device that drives, wherein, the device masking logic signal when switching cycle starts for sheltering continue turn-on time section and when spike being detected optionally masking logic signal continue peak hour section.In one embodiment, the device for sheltering comprises the device for detecting spike.In one embodiment, described turn-on time, section had the fixing duration longer than the estimation of switch maximum turn-on time.In one embodiment, section has the fixing duration of the estimation maximum duration based on spike described peak hour.In one embodiment, section has given duration duration of the spike detected described peak hour.
In one embodiment, a kind of method comprises: the first signal and secondary signal are compared, thus formation logic signal, secondary signal representative is through the electric current of current path; At least part of logic-based signal generates the drive singal for the switch in drive current path; In each cycle of switch, masking logic signal continues section turn-on time; And logic-based signal-selectivity ground masking logic signal continues peak hour section, wherein compare, generate drive singal and shelter and performed by one or more electronic equipment.In one embodiment, described turn-on time, section had the fixing duration longer than the estimation of switch maximum turn-on time.In one embodiment, the logical signal sheltered in each switching cycle be limited to one turn-on time section and one peak hour section.In one embodiment, section has the fixing duration of the estimation maximum duration based on spike described peak hour.In one embodiment, section has given duration duration of the spike detected described peak hour.
Accompanying drawing explanation
The example features of various embodiment and advantage by from the accompanying drawings by becoming clear in the hereafter specific descriptions of its exemplary embodiments shown in non-limiting examples, in the accompanying drawings:
Fig. 1 shows the circuit for controlling switching converter according to known technology;
Fig. 2 shows some time diagrams of the signal relevant with the circuit in Fig. 1;
Fig. 3 shows another circuit for controlling switching converter according to known technology;
Fig. 4 shows some time diagrams of the signal relevant with the circuit in Fig. 3;
Fig. 5 shows the integrated circuit controlling switching converter according to the equipment in the forward position for utilizing the current signal for blanking power transistor of an embodiment;
Fig. 6 is the circuit block diagram of the equipment in the forward position of the current signal for blanking power transistor according to an embodiment;
Fig. 7 is the circuit diagram of the equipment in the forward position of the current signal for blanking power transistor according to an embodiment;
Fig. 8 shows some example time diagrams of the signal relevant with the circuit in Fig. 5 that the equipment in Fig. 7 is applied to;
Fig. 9 is the circuit diagram of the equipment in the forward position of the current signal for blanking power transistor according to embodiment;
Figure 10 shows the execution mode of the logical circuit of the equipment in Fig. 9 and some time diagrams of the signal relevant with the circuit in Fig. 5 that the equipment in Fig. 9 is applied to together with the execution mode of logical circuit;
Figure 11 shows the execution mode of the logical circuit of the equipment in Fig. 9 and some time diagrams of the signal relevant with the circuit in Fig. 5 that the equipment in Fig. 9 is applied to together with the execution mode of logical circuit.
Embodiment
In the following description, some details is set forth to provide the thorough understanding of the various embodiments to equipment, method and product.But it will be understood by those skilled in the art that and still can realize other embodiment without these details.In other example, the known features and method that such as associate with power transistor, error amplifier, comparator etc. are not yet specifically illustrated or have described in some of the figures to avoid the description of unnecessarily fuzzy embodiment.
Unless the context requires otherwise, in following specification and claims, wording " comprises " and changes, such as " to comprise " and " comprising " will open to comprise meaning to explain, namely " to include but not limited to ".
Quote " embodiment " or " embodiment " in this specification and mean that special characteristic, structure or the characteristic described in conjunction with this embodiment is contained at least one embodiment.Therefore, occur that phrase " in one embodiment " or " in an embodiment " may not refer to identical embodiment or all embodiments at specification various places throughout.In addition, in one or more embodiment, special characteristic, structure or characteristic can be combined in any appropriate manner to obtain more embodiments.
Title is provided only conveniently and not explain scope or the implication of present disclosure or claim.
The size of the unit in accompanying drawing and relative position may not be drawn in proportion.Such as, the shape of various unit and angle can not drawn on scale, and some unit that can amplify and locate in these unit are to provide accompanying drawing legibility.In addition, the given shape of unit as drawn may not be intended to pass on any information about the true form of discrete cell and has been only by selection and is easy in the accompanying drawings identify.Reference, such as geometry or other reference are not intended to refer to desirable embodiment.
The problem of the circuit of its operation based on the electric current I p of senses flow overpower transistor is that the parasitic signal Sp in fact not representing electric current to be controlled may cause the comparison and/or protective circuit that activate the described electric current of sensing by mistake.
The condition of this type may (namely on the forward position of current signal Ip) occur immediately continuing Short Interval after connection power transistor.For several reasons, the Reverse recovery etc. of the rectifier diodes in such as parasitic capacitance discharge, power circuit, has the spike Sp superposed on the forward position of current signal Ip usually.The duration of such spike is usually short, but the amplitude of spike may apparently higher than the operation amplitude of current signal Ip.These spikes Sp may the terminating of control time of trigger power transistor too early, and this may make transducer operate brokenly.
Usually the problem of the spike Sp on the forward position of current signal is solved in two different ways.
First method is the filtering mode usually by using low pass RC circuit to realize between inputting at the sensing of current-sense resistor Rs and control appliance.Described RC filter time constant should be long enough to reduce below peak amplitude to the peak value of useful signal.On the other hand, time constant can not be oversize, otherwise the delay introduced on useful signal (equaling time constant) has the risk making current protective device inefficient when actual overcurrent.Usually, this time constant counts in hundred nanoseconds, but find that appropriate the trading off between two factors mentioned above is not always easy.In addition, two additional external component can also be used.
Second method introduces Spike suppression circuitry in the current sense input of control appliance.The such peak restrained circuit of one class is the peak restrained circuit being commonly referred to lead-edge-blanking circuit.Fig. 3 shows the same circuits figure in Fig. 1, has wherein added spike blanking block 50 with the spike Sp (see Fig. 4) in the forward position of the blanking signal Vcs proportional with flowing through the electric current I p of power transistor M1.Block 50 blanking signal Vcs continues blanking period Tleb, therefore obtains signal Vcs_b.In addition or replace, the AND door 7 that the signal Lb of the output and block 50 that receive PWM comparator 4 exports as input prevents the reset signal R of PWM latch to have high level in blanking period Tleb.
Usually, these circuit to be activated immediately before power transistor and operates so that the signal of blanking in the sensing input and/or output of the circuit of the signal of process sensing during Short Interval up after switching connecting.This Short Interval is often called " blanking period ".Such as, sensing input can temporarily be kept to be shorted to ground connection or to compare from downstream and/or protective circuit isolation, thus they do not receive spike; Or, to replace or in addition, can temporarily masking ratio compared with and/or the output of protective device, thus do not receive error signal at the circuit in the latter downstream.Fig. 4 shows the example of the signal relevant with the circuit in Fig. 3.
Monostable, the non-multivibrator that can again trigger is depended in beginning and the end of blanking time section usually, and this multivibrator provides the pulse with preset durations.Monostable trigger-action circuit is activated by the identical signal Q1 of the connection determining power transistor M1; Monostable trigger-action circuit determination blanking period.
This mode is not no problem.Fixing blanking period may seriously limit the frequency range that wherein can use control appliance, and this may make troubles in common apparatus.In fact, consider the tolerance of the duration of blanking period, minimum duration must be long enough to blanking spike.On the other hand, the maximum duration should so not grow to such an extent as to due to minimal turn-on time of power transistor oversize and obviously reduce the validity of protective circuit under overcurrent situations.
Relate on the other hand the switch on delay of power transistor, this switch on delay depends on power transistor itself, the characteristic of gate drivers 6 and the interface circuit also depended between the driver output and the input terminal (grid of MOSFET or IGBT) of transistor of control appliance.This delay may be difficult to or can not predict and also can be adjusted to reduce the electromagnetic noise generated when connecting.Long switch on delay can reduce effective duration of blanking period substantially.
Alternate manner is proposed to overcome problem mentioned above.U.S. Patent No. 5,418,410 describe a kind of circuit, and in the circuit, the end of blanking time section depends on that driving voltage exceedes the value determined, anticipated capability transistor are connected entirely and the disappearance of forward position spike.It is a kind of self adaptation lead-edge-blanking form, and namely this form makes the duration of blanking period adapt to the characteristic of power transistor.But always may not sense the voltage (such as when transistor is discrete parts beyond control appliance and there is interface circuit mentioned above) of the actual applying of input terminal to transistor.Because the voltage on the input terminal of transistor is always lower than the voltage of the output at drive circuit, so it may cause than required shorter blanking period.
In U.S. Patent No. 6,144, in 245, describe a kind of system, wherein blanking period is when the electric current that last driving stage provides exceedes the threshold value determined, and terminates when described electric current is down to below this value.
Even if this method forms driving voltage and directly can not obtain and still applicable self adaptation lead-edge-blanking, but the parasitic element that its operation may be flow through by drive current (inductance and electric capacity) is present in circuit and affects.These parasitic antennas resonance and generating may temporarily may reduce the vibration of drive current extremely below threshold value mentioned above before transistor is connected entirely.This will cause terminating ahead of time of blanking period.In addition, as driven MOS FET or IGBT, should ensure that the supply voltage of drive circuit is apparently higher than steady voltage, otherwise drive current is reduced to below threshold value may occur owing to having the natural wastage of the current capacity of the driver of low differential voltage.
In U.S. Patent No. 7,151, in 679, a kind of circuit with variable blanking time section is described.Duration is the function of the output loading of transducer: it is longer, shorter when load is lighter when load is heavy.This intersystem problem is that the minimizing of the blanking time section when load is light may easily make blanking invalid: in fact, and when the electric discharge of spike mainly owing to parasitic capacitance ahead of the curve, the duration of described spike is almost independent of loading condition.
Fig. 5 shows switching converter 10, and this switching converter comprises the integral control circuit (as shown being power transistor M1) for switch, and this switch is suitable for current path that is closed or turn-off current Ip stream.Integral control circuit 1 comprises equipment, and this equipment as shown is blanking block 100, and this blanking block is configured to the forward position of the blanking signal Vcs proportional with the electric current I p flowing through power transistor M1.
Integrated circuit 1 comprises comparator 4, and the secondary signal Vcs that this comparator is suitable for the first signal Ve and representative to flow through the electric current I p of described current path compares; Whether comparator 4 is suitable for according to described secondary signal Vcs lower than described first signal Ve or export the 3rd signal Vc variable between low logic level and high logic level on the contrary.Integral control circuit comprises driver 6, and this driver is suitable for exporting for drive singal G that is closed or disconnection power transistor M1 in response to the 3rd signal Vc.In addition, it comprises equipment 10, when this equipment is suitable for occurring that the forward position of secondary signal Vcs exists spike Sp in the first time period T1 connecting from M1, blanking the 3rd signal Vc continues the following time period, and this time period depends on the Tsmax of the duration of described spike Sp.
Integral control circuit 1 is specifically suitable for the gate terminal controlling the transistor MOSM1 that electric current I p flows through, and this electric current is proportional with the input voltage vin as commutating voltage Vac.Integral control circuit 1 receives the current signal I that feedback block 2 generates
f.Electric current I
fit is the function of output voltage Vout.From the electric current I that the input of integrating control electric current 1 is drawn
f, thus cause generated error signal Ve.Anti-phase input to PWM comparator 4 provides signal Ve, and this PWM comparator has the voltage Vcs that electric current I p is formed at the current-sense resistor Rs two ends be connected between the source electrode of M1 and ground connection GND in noninverting input.The output of comparator 4 is the 3rd signal Vc be fed to the input of equipment 10, and the output of equipment 10 is replacement inputs of PWM latch 5, and PWM latch 5 has clock signal C LOCK arranging on input S.To driver 6 input/output signal Q, this driver uses the gate terminal of signal G driving transistors M1 as shown in the figure.Vdrain is the voltage between the drain terminal and ground connection GND of transistor M1; Is is the electric current flowed in the primary side of transformer T, and the electric current I p flowing through M1 flows through transformer primary.Can to the various circuit block supply of control circuit 1 supply voltage equal or lower with common supply voltage (not shown), and these circuit blocks have the circuit part being connected to the ground connection GND associated with common supply voltage.
Fig. 6 shows the schematic block diagram of the embodiment of equipment 10, and this equipment is used for the forward position of the current signal Ip of blanking power transistor M1.The output function of described equipment 10 pairs of PWM comparators 4, and generate signal R in the replacement input of PWM latch 5.Equipment 10 comprises evaluate logic 11, and this evaluate logic is suitable for whether assessment signal Vc is significant signal or disturbance, such as spike.Equipment 10 comprises disturbance blanking interval, and this disturbance blanking interval comprises block 12 and AND door 13, if as long as the value that this disturbance blanking interval is suitable for signal Vc is disturbance and described signal Vc is disturbance, utilize signal T1 blanking signal Vc to continue blanking period.Signal Vc and signal T1 is coupled to the input of AND door 13, and this AND door is configured to provide signal R to PWM latch 5.Signal Vc is following logical signal, and this logical signal is in high logic level when signal Vcs reaches signal Ve and is held in low logic level at signal Vcs lower than during signal Ve, i.e. ground connection GND.When the forward position of signal Vcs exists spike Sp (forward position spike Sp), signal Vc becomes the duration that high logic level continues described spike; This be considered as equipment 10 disturbance and by blanking.
Fig. 7 shows the lead-edge-blanking equipment 10 of the current signal of the power transistor according to the first embodiment; Fig. 8 shows the waveform relevant with the embodiment of the circuit in Fig. 5, and this embodiment uses the embodiment of the equipment 10 of Fig. 7.
Signal CLOCK is the pulse of the very short duration of local oscillator or another circuit evolving particular event occurred in power circuit being detected.As already described, clock signal is the input signal S of PWM latch 5, and transistor M1 is connected.What this clock signal was also gone to one of OR door 101 input and arranged-reset trigger FF1 arranges input S.The output of PWM comparator 4 is inputs for two AND doors 102 and 103.Another input of AND door 102 is the output Q of trigger FF1, and the output A1 of AND door 102 is another both inputs of replacement input R1 and the OR door 101 of trigger FF1.Evaluate logic 11 comprises trigger FF1 and AND door 102.The monostable MF1 of flip-over type again the output of OR door 101 can be fed to along responsive to aligning.The output LEB of monostable MF1 apply to become to its input just along time step-down, namely become ground connection GND sustainable utilization internal counter regular time T1.
When applying CLOCK signal, Vcs is initially zero, and thus Vc is in low level, is ground connection GND, and the output of door 102 is zero.Monostable MF1 is activated on the follow-up just edge of the pulse that the output of OR door 101 occurs, and its output LEB becomes logic low duration T 1.By longer for usual maximum switch on delay Tdmax time T1 being chosen to certain specific power transistor.
During the duration of opening when clock pulse CLOCK arrives is the time window of T1, if signal Vc becomes high logic level, then door 102 allows this signal to pass through, and AND door 103 blocks it towards the replacement of PWM latch.Then, if the forward position spike Sp be present in signal Vcs has abundant amplitude (namely it is Vcs >=Ve), then it at certain Td≤T1 triggering in a flash PWM comparator 4, and will apply another just edge by by AND door 102 in the input of MF1.Because monostable MF1 can trigger again, so will the inside counting of monostable MF1 be reset and again count from this time period T1 of low output level in a flash, thus extended the blanking of signal Vc by door 103.Time period T also should be long enough to cover the maximum duration T smax of forward position spike to suppress it.During the trigger action again of monostable MF1, the output of AND door 102 resets trigger FF1, therefore it does not allow again to trigger monostable MF1 again during this switching cycle: in fact, in order to again realize the triggering again of monostable MF1, follow-up CLOCK pulse needs again to arrange trigger FF1.This function prevents the possible resilience of the signal Vcs caused by noise from triggering monostable MF1 repeatedly.Such resilience may cause the very long blanking time, and these very long blanking times easily may damage the operation of whole transducer.Therefore, trigger FF1 performs and removes rebound.
At the end of period Tb=Td+T1, signal LEB becomes high level, and the blanking of AND door 103 couples of signal Vc terminates, and then described signal can reset PWM latch 5 to allow stop power transistor M1.
If forward position spike Sp is not even as big as triggering PWM comparator 4 (this illustrates by dotted line in fig. 8), then MF1 can not be triggered and blanking period will be limited to very first time window T1.Therefore utilize this circuit to obtain, between T1 and 2*T1, there is successional variable blanking period.
Disclosed circuit uses should the longer single blanking period T1 of maximum both duration T smax of the maximum switch on delay Tdmax of specific power transistor and forward position spike, i.e. T1 > max (Tdmax, Tsmax).
This may be a problem when large gauge power transistor: switch on delay may be obviously longer than the duration of forward position spike, therefore causes the oversize duration of blanking period.
Fig. 9 shows the equipment 10 of the lead-edge-blanking for the current signal to power transistor according to the second embodiment.
Signal Q is the output of PWM latch 5.The high logic level of Q keeps gate drivers 6 to connect.Therefore when having the just edge of signal Q when connecting, activate align along responsive non-can the monostable MF10 of flip-over type again, and its output LEB1 step-down, namely becomes GND duration section T2.Similar to the previous circuit of Fig. 7, the maximum switch on delay Tdmax usually time T2 being chosen to certain specific power transistor M1 is longer.
By signal
(i.e. the signal LEB1 of negate) takes the input of AND door 201 to, and this AND door is Received signal strength Vc in another input, and this signal is the output of PWM comparator 4.Therefore limit the time window of duration T 2, during this time window, if signal Vc uprises, then door 201 allows signal Vc to pass through.Then, if the forward position spike Sp in signal Vcs has abundant amplitude (namely it is higher than Ve), then certain in a flash Td≤T2 the input of the monostable MF20 of flip-over type again can apply just edge by by door 201 to non-.Because MF20 aligns along responsive, so step-down is continued following time T1 by its output LEB2, this time is long enough to the duration covering forward position spike Sp.
There is provided signal LEB1 and LEB2 to functional block 202, this functional block also can input Received signal strength Vc its another.Block 202 generates signal MASK, and this signal, by the output Vc of door 203 blanking PWM comparator 4, therefore prevents from resetting PWM latch 5 sustained periods of time Tb.At the end of Tb, signal Vc will be allowed by resetting PWM latch 5 and stop power transistor M1.
From the different internal configurations of the logical network of processing signals LEB1, LEB2 and Vc corresponding be possible for generating the various criterion of signal MASK.
Figure 10 illustrates functional block 202 the first example embodiment and with it once the relevant waveform of the operation in the circuit be inserted in Fig. 5.
In this case, the logic AND Setting signal MASK of two signal LEB1 and LEB2.If described spike continues sufficient time section higher than Ve, then result is the blanking period Tb=Td+T1 that can continuously change from minimum value T2 to maximum of T 1+T2.Therefore: T2≤Tb=Td+T1≤T1+T2.
Even if it should be noted that forward position spike is loss in time period T2, still there is Tb=Td+T1.
As compared with the equipment 10 of the first embodiment, advantage likely selects T1 and T2 dividually, to make their adaptations to the duration T d of influential two the different phenomenons of their selection and Ts:T2 > Tdmax, T1 > Tsmax.
Figure 11 illustrates functional block 202 the second execution mode and with it once the relevant waveform of the operation in the circuit be inserted in Fig. 5.
In this case, signal LEB1 and signal
the logic AND Setting signal MASK of the logic OR of (i.e. the Vc signal of negate) and signal LEB2.Result to have the blanking period Tb of minimum value T2.Equally, if spike Sp extends beyond time period T2, as long as then signal Vc keeps high, as long as namely spike Sp does not exceed more than aforementioned triggering level, the duration of period Tb will extend beyond T2, but the duration is no longer than time period T1.Therefore: T2≤Tb=Td+Ts≤T1+T2 and Ts are duration of spike Sp, Ts lower than or equal Tsmax.
Therefore, also in this case, the maximum duration of Tb is T1+T2; But the duration that advantage is Tb is in the middle regime enough to suppress spike and not longer than required.
Also it should be noted that monostable MF1 and MF2 is non-can again triggering, the possible resilience therefore on signal Vcs can not affect circuit operation.This makes anti-rebound trigger unnecessary.
Also in this case, T1 and T2 can be selected to make them adapt to the maximum duration of Td and Ts: T2 > Tdmax, T1 > Tsmax.
It should be noted that when electric current being taken to the transducer overload of signal Vcs always in the such value of more than Ve, the minimal turn-on time of power transistor will be at least Tbmax, when this Tbmax equipment in figure 6 for 2*T1 and equipment in fig .9 when be T1+T2 (having two options).
Also it should be noted that in exemplary embodiments, signal Vcs available if having time because operating principle based on cause from disturbance affect itself refuse disturbance.
Due to the switch on delay of power transistor M1, by the impact using the equipment 10 in PWM comparator 4 downstream to reduce the minimizing of actual blanking time.In addition, the duration of blanking period T1 can the needs of adaptive circuit.Therefore, suppress the ability of forward position spike can with maintain efficiently limit the electric current through power transistor ability, even combine with relative high switching frequency.In fact, the short minimal turn-on time of power transistor M1 can be realized.Finally, if the amplitude of forward position spike Sp makes it not cause the non-required switching of PWM comparator 4 (if power transistor works under so-called " soft handover " condition when connecting, then this non-required switching may easily occur), then reduce the duration of lead-edge-blanking.
Above-described various embodiment can be combined to provide more embodiments.If necessary then can revision for execution example aspect with use various patent, application and open source literature concept to provide more embodiments.
Can be carried out these and other according to the description described in detail to embodiment above to change.Generally speaking, in the following claims, the term of use should not be construed as make claim be limited to disclosed specific embodiment in the specification and in the claims and should be interpreted as comprising likely embodiment and such claim are had the right the gamut of the equivalents had.Thus, disclosure does not limit claim.
Claims (31)
1. an integrated circuit, comprising:
Comparator, the secondary signal be configured to the electric current of current path is flow through in the first signal and representative compares, and relatively exports the 3rd signal variable between low logic level and high logic level based on described;
Driver-level, is configured to based on described 3rd signal output drive signal and is configured to be coupled to the switch of described current path; And
Blanking apparatus, to be coupled between described comparator and described driver-level and to be configured to:
Shelter described 3rd signal when switching cycle starts and continue first time period;
Based on the spike on the forward position of secondary signal described in described 3rd input; And
Optionally shelter described 3rd signal when spike being detected and continued for the second time period.
2. integrated circuit according to claim 1, shelters described 3rd signal and continues described second time period when wherein said blanking apparatus is configured to the spike detected in described first time period at described blanking apparatus on the described forward position of described secondary signal.
3. integrated circuit according to claim 2, wherein said blanking apparatus is configured to the spike detected when described 3rd signal rises to described high logic level from described low logic level in described first time period the described forward position of described secondary signal.
4. integrated circuit according to claim 1, wherein said switch is power transistor.
5. integrated circuit according to claim 1, wherein said blanking apparatus is configured to make the multiple time periods of sheltering described 3rd signal in each switching cycle be limited to described first time period and described second time period.
6. integrated circuit according to claim 1, wherein said first time period has the duration based on the maximum switch on delay estimated.
7. integrated circuit according to claim 1, wherein said second time period had by the duration of the detected spike given duration.
8. integrated circuit according to claim 6, wherein said blanking apparatus is configured in response to clock signal to start described first time period.
9. integrated circuit according to claim 8, wherein said second time period has the maximum duration equal with described first time period.
10. integrated circuit according to claim 8, wherein said blanking apparatus comprises:
Replacement trigger is set, is configured to receive described clock signal arranging input;
AND door, is configured to reception and arranges from described the output and described 3rd signal that reset trigger;
OR door, is configured to receive described clock signal and the output from described AND door; And
Can the monostable device of flip-over type again, be coupled to the output of described OR door and be configured to trigger described first time period in each switching cycle and optionally trigger described second time period.
11. integrated circuits according to claim 1, wherein said blanking apparatus comprises:
Non-can the first monostable device of flip-over type again, be configured to trigger described first time period; And
Non-can the second monostable device of flip-over type again, be configured to trigger described second time period, described first time period has the duration different from the duration of described second time period.
12. integrated circuits according to claim 11, wherein said blanking apparatus be configured to described drive singal have just along time trigger described first time period.
13. integrated circuits according to claim 11, wherein said blanking apparatus comprises:
AND door, be configured to receive from described non-can the negate of the output of the described first monostable device of flip-over type and described 3rd signal again, wherein said first monostable device be configured in response to described drive singal just along and activate, and described non-can the described second monostable device of flip-over type be again configured in response to described AND door output just along and activate; And
Control logic, be configured to receive from described non-can again flip-over type described first monostable device and from described non-can the signal that exports of the described second monostable device of flip-over type again, and generate sheltering of described 3rd signal in each switching cycle based on the output signal of described first monostable device and described second monostable device.
14. integrated circuits according to claim 13, wherein said control logic is configured to receive described 3rd signal and generate described in described 3rd signal based on the described output signal of described first monostable device, the output of described second monostable device and the 3rd signal shelter.
15. integrated circuits according to claim 1, wherein said second time period has duration of the maximum duration of the estimation based on spike.
16. integrated circuits according to claim 1, wherein said first time period has the fixing duration of estimation maximum duration based on section turn-on time, and described second time period has the duration substantially equal with the duration of detected spike.
17. integrated circuits according to claim 16, wherein said first time period and described second time period overlapping.
18. integrated circuits according to claim 1, wherein said switch is the power transistor of the power switched supply with input voltage and output voltage, the described electric current of described current path is proportional with the input voltage through rectification, and described first signal and the error voltage between reference voltage and the feedback voltage representing described output voltage proportional.
19. 1 kinds, for controlling the system of the switch of current path, comprising:
Rectifier, is configured to rectification AC signal;
Power transistor, is configured to disconnect and closed path path, is coupled to described rectifier;
Export; And
Controller, described controller comprises:
Comparator, the secondary signal that the first signal being configured to the voltage error by representing described output flows through the electric current of described current path with representative compares, and relatively generates the 3rd signal with logic level based on described;
Driver-level, is configured to based on the drive singal of described 3rd signal output for described power transistor; And
Blanking apparatus, to be coupled between described comparator and described driver-level and to be configured to:
Shelter described 3rd signal when switching cycle starts and continue first time period;
Based on the spike on the forward position of secondary signal described in described 3rd input; And
Optionally shelter described 3rd signal when spike being detected and continued for the second time period.
20. systems according to claim 19, wherein said first time period has the fixing duration longer than the maximum turn-on time of the estimation of described power transistor.
21. systems according to claim 20, wherein said second time period had by the duration of the detected spike given duration.
22. 1 kinds, for controlling the equipment of the switch of current path, comprising:
For being compared with secondary signal by the first signal and comparing based on described the device generating logical signal, described secondary signal representative is through the electric current of current path;
For at least part of device driving the switch in described current path based on described logical signal; And
For sheltering the device of described logical signal, be coupled between described device for comparing and the described device for driving, the wherein said device for sheltering described logical signal is sheltered described logical signal and is continued section and optionally shelter described logical signal when the spike on the forward position of described secondary signal being detected and continue peak hour section turn-on time when switching cycle starts.
23. equipment according to claim 22, the wherein said device for sheltering comprises the device for detecting spike.
24. equipment according to claim 22, wherein said turn-on time, section had the fixing duration longer than the maximum turn-on time of the estimation of described switch.
25. equipment according to claim 22, wherein said peak hour section there is the fixing duration of the maximum duration of the estimation based on spike.
26. equipment according to claim 22, wherein said peak hour section have by the duration of the detected spike given duration.
27. 1 kinds, for controlling the method for the switch of current path, comprising:
First signal and secondary signal are compared, formation logic signal, described secondary signal representative is through the electric current of current path;
The drive singal for driving the switch in described current path is generated at least partly based on described logical signal;
Shelter described logical signal when switching cycle starts and continue section turn-on time; And
Optionally shelter described logical signal when spike being detected and continue peak hour section, wherein said comparison, the described drive singal of described generation and described sheltering are performed by one or more electronic equipment.
28. methods according to claim 27, wherein said turn-on time, section had the fixing duration longer than the maximum turn-on time of the estimation of described switch.
29. methods according to claim 27, the wherein said described logical signal sheltered in each switching cycle be limited to one turn-on time section and one peak hour section.
30. methods according to claim 27, wherein said peak hour section there is the fixing duration of the maximum duration of the estimation based on spike.
31. methods according to claim 27, wherein said peak hour section have by the duration of the detected spike given duration.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| ITMI20100778 | 2010-05-04 | ||
| ITMI2010A000778 | 2010-05-04 | ||
| PCT/EP2011/056956 WO2011138276A2 (en) | 2010-05-04 | 2011-05-02 | Integrated circuit for controlling a switch of a current path with leading edge blanking device of the current signal. |
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| Publication Number | Publication Date |
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| CN102948060A CN102948060A (en) | 2013-02-27 |
| CN102948060B true CN102948060B (en) | 2016-01-20 |
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| US (1) | US9397573B2 (en) |
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Also Published As
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| US20130057323A1 (en) | 2013-03-07 |
| WO2011138276A2 (en) | 2011-11-10 |
| WO2011138276A3 (en) | 2012-11-22 |
| US9397573B2 (en) | 2016-07-19 |
| CN102948060A (en) | 2013-02-27 |
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