CN102945847A - Electrostatic discharge circuit with low-noise interference for interior of chip - Google Patents
Electrostatic discharge circuit with low-noise interference for interior of chip Download PDFInfo
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- CN102945847A CN102945847A CN2012105006664A CN201210500666A CN102945847A CN 102945847 A CN102945847 A CN 102945847A CN 2012105006664 A CN2012105006664 A CN 2012105006664A CN 201210500666 A CN201210500666 A CN 201210500666A CN 102945847 A CN102945847 A CN 102945847A
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- esd
- protection circuit
- earth terminal
- electrostatic storage
- storage deflection
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Abstract
The invention provides an electrostatic discharge protective circuit with low-noise interference for the interior of a chip. The electrostatic discharge circuit protective circuit is arranged in the chip, the chip comprises a main circuit, and a first power supply end and a first ground end which are connected with the main circuit; the electrostatic discharge protective circuit at least comprises an electrostatic discharge protective circuit unit connected with the main circuit, a second power supply end and a second ground end which are connected with the electrostatic discharge protective circuit, and a plurality of bonding lines used for respectively connecting the first power supply end to a first power supply pin, connecting the first ground end to a first ground pin, connecting the second power supply end to a second power supply pin, and connecting the second ground end to a second ground pin. The electrostatic discharge protective circuit with the low-noise interference for inside of the chip has advantage that the noise interference caused to the main circuit can be effectively reduced.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed that has.
Background technology
The input/output end port of existing semiconductor chip and power port place all can arrange the Electrostatic Discharge protective circuit, avoid the high voltage destruction that extraneous static is produced with the protection semiconductor chip.Fixed (Bonding) line efficient circuit of common ESD protection circuit and nation thereof as shown in Figure 1, wherein, left-half is the ESD protection circuit, and right half part is the pad (PAD) of chip internal is connected to packaging pin (PIN pin) by the Bonding line equivalent circuit diagram.This ESD protection circuit is formed by PMOS pipe P1 and the NMOS pipe N1 serial connection that diode connects, the source (source) of PMOS pipe P1, grid end (gate) is connected to the VDDA pad with body end (body), during encapsulation, this VDDA pad connects the VDD pin by the Bonding line, the source of NMOS pipe N1, grid end and body end are connected to the GNDA pad, during encapsulation, this GNDA pad connects the GND pin by the Bonding line, the drain terminal (drain) of PMOS pipe P1 links to each other with the drain terminal of NMOS pipe N1, and when connecting I/O (In/Out) pad (PAD) encapsulation, this In/Out pad connects the I/O pin by the Bonding line.Because the main circuit of this ESD protection circuit and chip shares high level VDDA and ground level GNDA.In order to reduce the impact on main circuit, usually ESD protection circuit and main circuit respectively from VDDA PAD, and GNDA PAD draw separately required VDD level and GND level, namely the two adopts Kelvin to connect (Kelvin Connection) mode.But there is defective in this processing mode, and especially when I/O pin access high-frequency signal, this high-frequency signal is through the stray inductance L of Bonding line
2Afterwards, can produce serious high-frequency noise, this noise is by PMOS pipe P1 and the NMOS pipe N1 parasitic capacitance (C of drain terminal and grid end separately
Gd) be coupled to VDDA pad and GNDA pad, and then enter main circuit, even can cause main circuit to work.
Summary of the invention
The shortcoming of prior art the object of the present invention is to provide a kind of electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed that has in view of the above.
Reach for achieving the above object other relevant purposes, the invention provides a kind of electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed that has, it is arranged in the chip, and described chip also comprises: main circuit and connect the first power end and first earth terminal of described main circuit; Described electrostatic storage deflection (ESD) protection circuit comprises at least:
The electrostatic storage deflection (ESD) protection circuit unit that connects described main circuit;
The first power end and the first earth terminal that connect described main circuit;
The second source end and the second earth terminal that connect described electrostatic storage deflection (ESD) protection circuit unit;
Many nation's alignments are connected to described the first power end respectively the first power pins, the first earth terminal and are connected to that the first grounding pin, described second source end are connected to the second source pin, the second earth terminal is connected to the second grounding pin.
Preferably, when the voltage potential that accesses separately when the first power end and second source end equated, the first power pins and second source pin were same pin.
Preferably, when the earth potential that accesses separately when the first earth terminal and the second earth terminal equated, the first grounding pin and the second grounding pin were same pin.
Preferably, the electrostatic storage deflection (ESD) protection circuit unit connects signal input part, the first power end and first earth terminal of described main circuit.
Preferably, when the voltage potential that accesses separately when the first power end and second source end equated, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode that is connected between the first power end and the second source end.
Preferably, when the earth potential that accesses separately when the first earth terminal and the second earth terminal equated, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode that is connected between the first earth terminal and the second earth terminal.
Preferably, when the voltage potential that accesses separately when the first power end and second source end was unequal, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode chain that is connected between the first power end and the second source end.
Preferably, when the earth potential that accesses separately when the first earth terminal and the second earth terminal was unequal, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode chain that is connected between the first earth terminal and the second earth terminal.
As mentioned above, the electrostatic storage deflection (ESD) protection circuit that has the interference of chip internal low noise of the present invention has following beneficial effect: reduce the suffered noise jamming of circuit in the chip.
Description of drawings
Fig. 1 is shown as ESD protection circuit of the prior art and Bonding line schematic equivalent circuit.
Fig. 2 is shown as the electrostatic storage deflection (ESD) protection circuit schematic diagram that the chip internal low noise is disturbed that has of the present invention.
Fig. 3 and Fig. 4 are shown as the circuit diagram between the power supply/ground level with electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed of the present invention.
The element numbers explanation
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, person skilled in the art scholar can understand other advantages of the present invention and effect easily by the disclosed content of this specification.
See also Fig. 2 to Fig. 4.Notice, the appended graphic structure that illustrates of this specification, ratio, size etc., equal contents in order to cooperate specification to disclose only, understand and reading for person skilled in the art scholar, be not to limit the enforceable qualifications of the present invention, so technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously, quote in this specification as " on ", D score, " left side ", " right side ", " centre " reach the term of " " etc., also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when also being considered as the enforceable category of the present invention.
As shown in the figure, the invention provides a kind of electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed that has, it is arranged in the chip 1.Described chip 1 comprises at least: main circuit 11, the electrostatic storage deflection (ESD) protection circuit unit 12(that connects described main circuit 11 are the ESD protection circuit), the first power end 13, the first earth terminal 14, second source end 15, the second earth terminal 16 and nation's alignment (Bonding line) 171,172,173,174,175.
Described main circuit 11 comprises the circuit that is integrated on the semiconductor base, and it can realize predetermined function and purposes as the core of chip 1, and for example, the main circuit that micro-chip processor comprises can be realized the functions such as control, logical operation.Those skilled in the art should understand that described main circuit, so no longer described in detail at this.
Described ESD protection circuit 12 connects described main circuit 11, is used for protection chip 1 and avoids the high-tension destruction that extraneous static produces.Preferably, described ESD circuit 12 comprises the PMOS pipe P of serial connection
11With NMOS pipe N
11, wherein, PMOS manages P
11Source (source), grid end (gate) be connected with body end (body), NMOS manages N
11Source, grid end be connected with the body end, PMOS manages P
11Drain terminal (drain) and NMOS pipe N
11Drain terminal link to each other after, connect again the signal input part (input) of main circuit 11.
Described the first power end 13 is connected described main circuit 11 with the first earth terminal 14.For example, as shown in Figure 2, described the first power end 13 is for connecting the VDDA pad of main circuit 11, and described the first earth terminal 14 is for connecting the GNDA pad of main circuit 11.
Described second source end 15 is connected described electrostatic storage deflection (ESD) protection circuit 12 with the second earth terminal 16.For example, as shown in Figure 2, described second source end 15 is for connecting the VDDE pad of described electrostatic storage deflection (ESD) protection circuit unit 12, and described the second earth terminal 16 is for connecting the GNDE pad of described electrostatic storage deflection (ESD) protection circuit unit 12.
Described nation alignment 171 is connected to the first power pins VDD1 with described the first power end 13, described nation alignment 172 is connected to the first grounding pin GND1 with described the first earth terminal 14, described nation alignment 173 is connected to the first power pins VDD2 with described second source end 15, described nation alignment 174 is connected to the second grounding pin GND2 with described the first earth terminal 16, and described nation alignment 175 is connected to signal input pin IN with described signal input part (input); Wherein, the equivalent electric circuit of each binding line as shown in Figure 2.
As a kind of optimal way, when the voltage potential that accesses separately when the first power end 13 and second source end 15 equated, the first power pins VDD1 and second source pin were same pin VDD2.
As a kind of optimal way, when the earth potential that accesses separately when the first earth terminal 14 and the second earth terminal 16 equated, the first grounding pin GND1 and the second grounding pin GND2 were same pin.
As a kind of optimal way, when the voltage potential that accesses separately when the first power end 13 and second source end 15 equated, described electrostatic storage deflection (ESD) protection circuit unit 12 comprised a pair of back-to-back diode that is connected between the first power end 13 and the second source end 15.
For example, as shown in Figure 3, described electrostatic storage deflection (ESD) protection circuit unit 12 comprises the diode D that is connected between VDDA pad and the VDDE pad
1, D
2
As a kind of optimal way, when the earth potential that accesses separately when the first earth terminal 14 and the second earth terminal 16 equated, described electrostatic storage deflection (ESD) protection circuit unit 12 comprised a pair of back-to-back diode that is connected between the first earth terminal 14 and the second earth terminal 16.
For example, as shown in Figure 3, described electrostatic storage deflection (ESD) protection circuit unit 12 comprises the diode D that is connected between GNDA pad and the GNDE pad
3, D
4
As a kind of optimal way, when the voltage potential that accesses separately when the first power end 13 and second source end 15 was unequal, described electrostatic storage deflection (ESD) protection circuit unit 12 comprised a pair of back-to-back diode chain that is connected between the first power end 13 and the second source end 15.
For example, as shown in Figure 4, described electrostatic storage deflection (ESD) protection circuit unit 12 comprises the diode chain D that is connected between VDDA pad and the VDDE pad
11, D
12... D
1n, and diode chain D
21, D
22... D
2n, wherein, the value of n is decided by the potential difference of the voltage that VDDA pad and VDDE pad access separately.
As a kind of optimal way, when the earth potential that accesses separately when the first earth terminal 14 and the second earth terminal 16 was unequal, described electrostatic storage deflection (ESD) protection circuit unit 12 comprised a pair of back-to-back diode chain that is connected between the first earth terminal 14 and the second earth terminal 16.
For example, as shown in Figure 4, described electrostatic storage deflection (ESD) protection circuit unit 12 comprises the diode chain D that is connected between GNDA pad and the GNDE pad
31, D
32... D
3m, and diode chain D
41, D
42... D
4m, wherein, the value of m is decided by the potential difference of the ground voltage that GNDA pad and GNDE pad access separately.
Need to prove, be simplicity of illustration, the part of electrostatic storage deflection (ESD) protection circuit unit 12 only is shown among Fig. 2, wherein, a part that connects the first power end 13, the first earth terminal 14 is not shown, is chatted bright at this.
In sum, of the present invention have the power end of the electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed and power end and the earth terminal of earth terminal and main circuit is independently, signal input part IN arrives power end and the earth terminal of ESD protection circuit with noise coupling, but can directly not affect power end and the earth terminal of main circuit; And, the noise signal of signal input part IN access through the ESD protection circuit after the grid end of MOS device of input main circuit, this barrier from technology also reduced the interference of noise to main circuit.If the height of the height/ground level of ESD protection circuit and chip main circuit/ground level equipotential, then during chip package, two pad VDDE are connected with VDDA and are connected same power pins by the Bonding line, and two pad GNDE are connected same grounding pin with GNDA.This has not only reduced the number of pin, and Kelvin's connected mode at this pin place, compares Kelvin's connected mode at existing pad place, has greatly reduced the noise jamming to main circuit.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (8)
1. one kind has the electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that, described have the electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed and be arranged in the chip, and described chip also comprises: main circuit and connect the first power end and first earth terminal of described main circuit; Described electrostatic storage deflection (ESD) protection circuit comprises at least:
The electrostatic storage deflection (ESD) protection circuit unit that connects described main circuit;
The second source end and the second earth terminal that connect described electrostatic storage deflection (ESD) protection circuit unit;
Many nation's alignments are connected to described the first power end respectively the first power pins, the first earth terminal and are connected to that the first grounding pin, described second source end are connected to the second source pin, the second earth terminal is connected to the second grounding pin.
2. according to claim 1 have an electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that: when the voltage potential that accesses separately when the first power end and second source end equated, the first power pins and second source pin were same pin.
3. according to claim 1 have an electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that: when the earth potential that accesses separately when the first earth terminal and the second earth terminal equated, the first grounding pin and the second grounding pin were same pin.
4. according to claim 1 have an electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, and it is characterized in that: the electrostatic storage deflection (ESD) protection circuit unit connects signal input part, the first power end and first earth terminal of described main circuit.
5. according to claim 1 or 4 describedly have electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that: when the voltage potential that accesses separately when the first power end and second source end equated, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode that is connected between the first power end and the second source end.
6. according to claim 1 or 4 describedly have electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that: when the earth potential that accesses separately when the first earth terminal and the second earth terminal equated, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode that is connected between the first earth terminal and the second earth terminal.
7. according to claim 1 or 4 describedly have electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that: when the voltage potential that accesses separately when the first power end and second source end was unequal, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode chain that is connected between the first power end and the second source end.
8. according to claim 1 or 4 describedly have electrostatic storage deflection (ESD) protection circuit that the chip internal low noise is disturbed, it is characterized in that: when the earth potential that accesses separately when the first earth terminal and the second earth terminal was unequal, described electrostatic storage deflection (ESD) protection circuit unit comprised a pair of back-to-back diode chain that is connected between the first earth terminal and the second earth terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105006664A CN102945847A (en) | 2012-11-29 | 2012-11-29 | Electrostatic discharge circuit with low-noise interference for interior of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105006664A CN102945847A (en) | 2012-11-29 | 2012-11-29 | Electrostatic discharge circuit with low-noise interference for interior of chip |
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| Publication Number | Publication Date |
|---|---|
| CN102945847A true CN102945847A (en) | 2013-02-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012105006664A Pending CN102945847A (en) | 2012-11-29 | 2012-11-29 | Electrostatic discharge circuit with low-noise interference for interior of chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110086434A (en) * | 2019-02-28 | 2019-08-02 | 厦门优迅高速芯片有限公司 | A kind of circuit promoted across RSSI foot anti-noise ability in resistance amplifying circuit |
| CN114501967A (en) * | 2022-01-20 | 2022-05-13 | 绵阳惠科光电科技有限公司 | Display panel and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208407A (en) * | 2010-03-31 | 2011-10-05 | 上海宏力半导体制造有限公司 | Composite power circuit and bidirectional thyristor |
| US8068319B1 (en) * | 2006-09-14 | 2011-11-29 | Marvell International Ltd. | Circuits, systems, algorithms and methods for ESD protection |
-
2012
- 2012-11-29 CN CN2012105006664A patent/CN102945847A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8068319B1 (en) * | 2006-09-14 | 2011-11-29 | Marvell International Ltd. | Circuits, systems, algorithms and methods for ESD protection |
| CN102208407A (en) * | 2010-03-31 | 2011-10-05 | 上海宏力半导体制造有限公司 | Composite power circuit and bidirectional thyristor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110086434A (en) * | 2019-02-28 | 2019-08-02 | 厦门优迅高速芯片有限公司 | A kind of circuit promoted across RSSI foot anti-noise ability in resistance amplifying circuit |
| CN114501967A (en) * | 2022-01-20 | 2022-05-13 | 绵阳惠科光电科技有限公司 | Display panel and electronic device |
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Application publication date: 20130227 |